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In a monolayer of hBN, the boron and nitrogen atoms form a 2D honeycomb structure similar to graphene with strong in-plane covalent bonds and weak ...

Received 3 March 2014; revised 11 May 2014; accepted 23 May 2014. Date of publication 3 June 2014; date of current version 21 August 2014. The review of this paper was arranged by Editor-in-Chief Renuka P. Jindal. Digital Object Identifier 10.1109/JEDS.2014.2328032

Graphene for Electron Devices: The Panorama of a Decade G. N. DASH1 (Senior Member, IEEE), SATYA R. PATTANAIK2 (Member, IEEE), AND SRIYANKA BEHERA1 2

1 Electron Devices Group at the School of Physics, Sambalpur University, Sambalpur 768019, India Department of Electronics and Communication Engineering, Apex Institute of Technology and Management, Bhubaneswar 752101, India

CORRESPONDING AUTHOR: G. N. DASH ([email protected])

ABSTRACT Graphene emerged in 2004 as the first 2-D material with exotic properties. Since then the

literature has been flooded with reports, with physicists, material scientists, and engineers grabbing their respective shares. Numerous reviews have also been published. While these reviews have done excellent works in their own ways, new reports are coming up faster than they could draw the attentions of researchers. The authors, therefore, feel that there is a demanding scope for a fresh review. Further, many aspects of graphene are not covered in the reviews so far. New concept devices are also entering into the arena of graphene day by day. The purpose of this paper is therefore to present a comprehensive review on the conventional as well as novel device applications of graphene. While we believe that graphene is the material which will transform the electron devices from the classical regime to the quantum world, it is difficult to believe that it will be a complete substitute to silicon in the near future. INDEX TERMS Graphene, growth process, logic devices, magneto-electronic devices, optoelectronic devices, RF devices.

I. INTRODUCTION

Graphene emerged in 2004 [1] as the first two-dimensional (2D) material with exotic electronic [1]–[3], magnetoelectronic [1]–[3] and optoelectronic [4], [5] properties. This boosted the electron devices community not only to recast the existing devices into the realm of the new paradigm but to contemplate a multitude of new emerging devices based on the material. As a consequence graphene entered into almost all the existing devices. While the first entry can be traced in the Field Effect Transistor (FET) in 2007 [6], the other noteworthy devices with graphene, investigated theoretically or experimentally, include the Bipolar Transistor [7], Resonant Tunnelling Diode [8], Tunnelling FET [9], Spin Transistor [10], Quantum Dot [11] and the Quantum Hall Effect devices [12]. Numerous reviews have also appeared in the published literature [13]–[19]. The reviews at [13] and [16] provide an exhaustive account of the physics of graphene. Other reviews have also done excellent works within their respective scopes. Nonetheless, we feel that a comprehensive review of graphene based devices is still a need of the hour, partly because new publications are coming up very fast and partly because the existing reviews are

VOLUME 2, NO. 5, SEPTEMBER 2014

lacking in topics like modelling, and magneto-electronic and spintronic devices. The purpose of this review is therefore, to offer a comprehensive account of the state-of-the-art graphene based devices. Additionally, this review aims at providing a concrete framework based on which a practicing engineer can probe further into the rich aggregation of graphene based electron devices. It has to be therefore, self content forcing us to go over some of the topics which are already available in published reviews. To start with, we present, in Section II, a brief account of the properties of graphene, which have made it so distinct from the rest. We have however, emphasized on the properties which are relevant to electron devices. The processing technology of graphene, which has not yet crossed its formative years, is crucial to the successful implementation of graphene based devices and circuits. We have elucidated this in Section III. MOSFET is by far the most widely explored electronic device. The device has been predominantly employed in two categories of integrated circuits: the digital logic circuits and the analog RF circuits. For the device as well as circuit designers, the channel length has always remained a critical

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DASH et al.: GRAPHENE FOR ELECTRON DEVICES: THE PANORAMA OF A DECADE

parameter. A continual effort to shrink the channel length has been beneficial to both the circuits in terms of augmenting the cut off frequency of the RF circuit and enhancing the switching speed of the logic circuit in addition to increasing the packing density in both cases. For a balanced device performance however, the decrease in channel length should be accompanied by change in other design parameters in some calculable proportion. This is what is referred to as MOSFET scaling. Since the scaling is likely to reach its fundamental limit in not so far a future, an alternative to Si technology has become a global demand. It is at this juncture, graphene has cropped up with a lot of expectations. We discuss the issues customary to graphene based MOSFETs in Section IV (digital logic devices) and Section V (analog RF devices). Triggered with experimental progress in graphene, a number of device modelling and simulation works have spanned the pages of published literature. A concise review of all such works has been the subject matter of Section VI. The wonders that graphene has shown in its magneto-electronic properties [2], [3] cannot be understated and novel devices based on them are worth consideration [12]. These are presented in Section VII. The optoelectronic properties of graphene are as mystifying as others. These have set off a plentiful of work on graphene based optoelectronic devices burgeoning the pages of highly reputed journals (see [20]–[24]). Section VIII has been devoted for a succinct assessment of these devices. In each of these sections we have first discussed the issues ubiquitous in the concerned category of devices, how graphene can make into them and where do we get to after that. Finally, we conclude the paper in Section IX. II. PROPERTIES OF GRAPHENE AND RELATED MATERIALS

In this section first we shall discuss the properties of graphene in Section II-A. Then we shall highlight the salient features of bilayer graphene and graphene nanoribbons in Section II-B and finally we shall touch upon the properties of other graphene-like materials with their impacts on graphene based electron devices. A. PROPERTIES OF GRAPHENE

Graphene constitutes a hexagonal lattice of carbon atoms that mimics a honeycomb structure [Fig. 1(a)]. The distance between carbon atoms is 1.42 Å. By looking at the electronic configuration of carbon, 1s2 2s2 2p2 it may be noted that the two 1s electrons, which constitute the electron core of the atom, do not take part in the conduction process and hence are unimportant from the electron devices point of view. The remaining four valence electrons, which command all the properties of graphene, redistribute among themselves with one electron each in the four orbitals, s, px , py and pz. The three orbitals s, px and py combine together and form three new equivalent orbitals; the process is known as sp2 hybridization. The three sp2 hybridized orbitals, which are symmetrically distributed (at angles of 120 degree), form three σ -bonds with those of the three nearest carbon atoms [Fig. 1(b)]. The strength of the σ -bonds 78

FIGURE 1. Structure of graphene. (a) Honeycomb lattice of carbon atoms, the dark circles and the unfilled circles represent carbon atoms at two different sites designated respectively as A and B, the shaded region indicates a unit cell. (b) sp2 hybridized orbitals of carbon atoms symmetrically distributed in the molecular plane at angles of 120◦ forming three σ -bonds with those of the three nearest neighbors. (c) Orbitals of the remaining electrons distributed perpendicular to the molecular plane form π -bonds with those of one of the nearest neighbor, assigning four bonds to each carbon atoms. (d) Two different orientations of the arrangement of carbon atoms at lattice sites A and B, the honeycomb lattice can be viewed as two interpenetrating triangular lattices of A and B carbon atoms.

makes graphene one of the strongest materials. The orbitals of the remaining pz electrons are distributed perpendicular to the molecular plane and they form what is known as the π -bonds with those of one of the three nearest carbon atoms [Fig. 1(c)]. These bonds can have two different orientations as in Fig. 1(d) and hence the graphene structure can be viewed as two interpenetrating triangular sub lattices A and B [Fig. 1(d)] with two atoms per unit cell [Fig. 1(a)]. Interaction among the atoms splits the energy levels of π electrons into two bands. The bonding π -electrons (at lower energy) constitute the valence band and the anti-bonding π ∗ electrons (at higher energy) comprise the conduction band. The electronic band structure of graphene was calculated by Wallace way back in 1947 [25] considering graphene as two interpenetrating triangular sub-lattices A and B, using a tight binding Hamiltonian. The dispersion relation from such calculation may be represented as [16]  E± (k) = ±t 3 + f (k) − t f (k)

(1)

where √ f (k) = 2cos( 3 ky a) + 4cos

√

3ky a 2



 cos

 3kx a , (2) 2

− → kx and ky are the components of the wave vector k , a = 1.42 Å is the carbon-carbon distance, t ∼ = 2.8 eV is the nearest neighbour hopping energy and t ∼ = 0.1 eV is the next nearest neighbour hopping energy. A 3D plot of this equation, adapted from the web resources of the Royal Swedish Academy of Sciences [26], is shown in Fig. 2(a). VOLUME 2, NO. 5, SEPTEMBER 2014

DASH et al.: GRAPHENE FOR ELECTRON DEVICES: THE PANORAMA OF A DECADE

FIGURE 2. Dispersion relation of graphene. (a) 3-D view indicating six cones for the conduction band and six inverted cones for the valence band touching at six points (referred to as Dirac points) in the Brillouin zone leaving no bandgap in between (figure reprinted from “The Nobel Prize in Physics 2010—Advanced Information,” http://www.nobelprize.org/nobel_ prizes/physics/laureates/2010/advanced.html with permission from the c 2010). (b) Six Dirac points in Royal Swedish Academy of Sciences  k-space, symmetry insists that the six points are not all different reducing them into two equivalent points K and K’.

It is observed that the cone-like conduction band for the π ∗ electrons and the inverted cone-like valence band for the π electrons touch at six points in the Brillouin zone. These points are referred to as Dirac points. From symmetry consideration they are equivalent to two points K and K  in the momentum space [Fig. 2(b)]. The dispersion relation plot at Fig. 2(a) reveals two important points. First it signifies that graphene is a zero-band-gap semiconductor (rather semimetal). In order to emphasize the second point we note that by applying the low energy approximation (so that the result is valid near the Dirac points) equation (1) reduces to [13], [27] − → E± (k) ∼ = ±  q  vF

(3)

− → − → → where − q = ( k − K ) is the electron momentum measured with respect to the Dirac point,  = h/2π , h is Planck’s constant and vF is referred to as the Fermi velocity whose value is 1 × 106 ms−1 [2]. This equation implicates that graphene has a linear dispersion relation, at least near the Dirac points. Such dispersion relation is an attribute of zeromass particles like the photons. It is thus reminiscent of the fact that the electrons in graphene behave like massless Dirac fermions moving with an effective velocity of light equal to the Fermi velocity. The density of states plays a crucial role to estimate the carrier density and hence bears a profound significance in the study of electron devices. This parameter calculated per unit cell near the Dirac point can be approximated as [25], [27] D(E) =

2Ac |E| π (vF )2

(4)

where Ac is the area of the unit cell. Thus, in contrast to the step-like density of states exhibited by 2D electron gas, graphene shows a linear density of states, although it is a 2D material. VOLUME 2, NO. 5, SEPTEMBER 2014

Due to the massless nature and velocity comparable to that of light (0.003×c, c is the velocity of light in vacuum), electron motion in graphene is governed by the relativistic Diraclike equation instead of the non-relativistic Schrödinger equation. While Dirac equation has a four-component spinor wave function that accounts for the two spin states of electron (particle) and positron (antiparticle) [28], the Dirac-like equation for graphene has two-component (pseudo) spinor wave function that determines the relative electron population on the two lattice sites A and B. The spinor in the latter case has nothing to do with electron spin and hence is usually referred to as the pseudo spinor state. One of the distinctive features of graphene is the absence of back scattering as in carbon nanotube [29]. It turns out that the carrier mobility in graphene is astoundingly high. Measured values show that it could be as high as 2.3 × 105 cm2 V−1 s−1 [30]. But such high mobility is possible only for pristine samples where care has been taken to minimize the scattering centers (discussed below), so that carrier transport is entirely ballistic. In most of the practical samples however, the carrier transport is strongly limited by scattering from extrinsic sources, thus making the transport diffusive. The charged impurities on the graphene surface as well as in the graphene-substrate interface (refer to Fig. 3(a) for a typical geometry for experimental study of graphene), and the interfacial and substrate phonons constitute the external sources of scattering. These scattering centers limit the carrier mobility drastically to values ranging from 10000 cm2 V−1 s−1 (Chemical Vapour Deposited graphene transferred to SiO2 and epitaxial graphene on SiC) to 15000 cm2 V−1 s−1 (exfoliated graphene on SiO2 ) under ambient condition [17]. In order to enhance the mobility by reducing the effect of extrinsic charge impurities, three methods are in practice. In one of them, the substrate beneath the graphene is etched out to form what is known as “suspended graphene.” By this way the graphene is now free from the charged impurities on the substrate. In order to further reduce the charged impurities that might have clung to the graphene surface, the sample is annealed by passing a heavy current through it. Bolotin et al. [31] have enhanced the mobility from 2.8×104 cm2 V−1 s−1 to 1.7×105 cm2 V−1 s−1 by this process. The other way is to use a high-K (dielectric constant) material for the gate dielectric and graphene substrate. The high dielectric constant reduces the strength of the long range coulomb scattering between the carriers and the charged impurities and thereby enhances the mobility of the carriers. Chen et al. [32] varied the gate dielectric constant from 2 to 47 and observed mobility enhancement from 102 cm2 V−1 s−1 to 7×104 cm2 V−1 s−1 . Change in substrate dielectric beneath the graphene to higk –K material, in addition to gate dielectric, is likely to further enhance the mobility. The third approach is to sandwich the graphene sample between two atomically flat and inert crystals (such as hBN, discussed in Section II-C) referred to as “encapsulated graphene.” Encapsulation saves the graphene sample from ambient conditions and protects the surface from roughness. 79

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FIGURE 3. Some electronic properties of graphene. (a) Typical gated structure to study the properties. (b) Variation of Hall coefficient as a function of gate voltage (figure reprinted from Science, vol. 306, pp. 666–669, 2004, with permission from AAAS). (b) Variation of conductance as a function of gate voltage (figure reprinted by permission c 2005). from Macmillan Publishers Ltd: Nature, vol. 438, pp. 197–200, 

The report by Bolotin et al. [31] has revealed some more interesting facts about transport in graphene. While the supported (on substrate) graphene shows a linear dependence of conductivity on the carrier density, the behavior becomes sub linear in the suspended graphene. Further, they observed that the mean free path of supported graphene (150 nm) was much less than the device dimension (2 μm) leading to the conclusion that transport is diffusive. For the diffusive transport, Boltzmann Transport Formalism can be applied by considering carrier scattering from charged impurities on the substrate and interface. For charged impurity scattering an expression for the conductivity can be derived as [31] 80

√ σ = (2q2 /h)kF vF τ where kF = πρ s is the Fermi wave vector, ρs the surface charge density and τ the scattering time [17]. For screened coulomb potential, τ ∝ kF justifying the linear dependence of σ on ρs . On the other hand, Bolotin et al. observed that the carrier mean free path of the suspended graphene was more than 1 μm and was comparable to their device dimension with the implication of ballistic transport in the sample. In the ballistic regime an expression for conductivity can be written as [31] √ σ = (4q2 /h) × (WkF /π ) ∝ ρs where W is the width of the sample. This equation thus accounts for the sublinear behavior of σ with ρs . It may however, be noted that when the ratio of carrier density to charged impurity density is large, the long range coulomb scattering becomes ineffective and the transport becomes dominated by short range scatterers like the point defects and dislocations. This may also lead to sublinear behavior of σ versus ρs [17]. Mayorov et al. [33] have studied ballistic transport in encapsulated graphene. They observed that the sample could exhibit a low temperature (below 50 K) mobility of 5×105 cm2 V−1 s−1 at a carrier density of 1012 cm−2 . This translates into a carrier mean free path of nearly 3 μm. Even at room temperature, their devices exhibited ballistic transport over 1 μm distance with a mobility exceeding 105 cm2 V−1 s−1 at carrier density as low as 1011 cm−2 . Carrier velocity is also an important transport parameter. For low source to drain field, the velocity first linearly increases with increase in electric field as long as the transport is dominated by the elastic scattering processes discussed above. But at higher electric field the inelastic optical phonon scattering increases and the velocity saturates [34]. Nonetheless, under the most ideal condition the carrier velocity in graphene may approach as high as the Fermi velocity (106 ms−1 ). The high mobility and high velocity in graphene are particularly attractive for high frequency circuits (both digital and analog). Thus in principle, graphene should be a potential candidate for the FET industry. But several other factors, which cause hindrance in the performance of graphene FET, need to be addressed. These are discussed in Sections IV and V. Apart from being zero-band-gap semimetal, graphene exhibits a strong ambipolar characteristic to the transverse electric field applied due to the low density of states. This has been demonstrated by Novoselov et al. [1] from the Hall coefficient (RH = 1/nq, n is the carrier volume density and q the magnitude of electronic charge) measurement of a gated structure of graphene [schematics of the structure shown in Fig. 3(a)]; the graph is reproduced in Fig. 3(b). It is edifying to note that the same graphene sample could be p-type or n-type depending on the gate bias applied. This implies that the carriers could be continuously tuned from electron to hole and vice versa by adjusting the applied gate bias. Such electric field induced carrier type as well as carrier density modulation shall offer a great deal of flexibility to the device designers to conceive a p-n junction, without physically doping the material. VOLUME 2, NO. 5, SEPTEMBER 2014

DASH et al.: GRAPHENE FOR ELECTRON DEVICES: THE PANORAMA OF A DECADE

Concomitant to the large mobility, graphene conductivity is also high and is observed to be better than that of Cu. With a most conservative estimate, the conductivity of graphene, at a carrier density of 1012 m−2 is arrived at 9.6×105 −1 cm−1 as against a value of 6.0 × 105 −1 cm−1 for Cu [26]. But the more interesting part is the conductivity modulation with gate bias. The results from [1] shown in Fig. 3(c) clearly indicates a linear rise in conductivity with rise in both positive and negative gate bias. The nature of the graph is indicative of a simple linear relation of the carrier density with gate bias, n = α × Vg where α = 7.3 × 1010 cm−2 V−1 [2]. Surprisingly the conductivity never goes to zero even at zero gate bias when the carrier density goes to zero. This is referred to as the minimum conductivity problem. Initially it was thought that the minimum conductivity is due to the quantum of conductivity, q2 /h. But measurements on several samples deny this because the value is observed to vary from sample to sample. On an average the experimental values huddle up around the point 4q2 /h although a recent experiment [35] demonstrates insulating behaviour around the Dirac point in pristine quality graphene down to a temperature of 20 mK. On the other hand, the theories predict widely divergent values of the minimum conductivity such as 4q2 /π h, π q2 /2h, 0 and even ∞ [16]. The first of these theoretical values (4q2 /π h) looks similar to the clustering point of the experimental values (4q2 /h) except for the pi. This is popularly known as the “mystery of the missing pi” [36]. It is now well understood that graphene transport near the Dirac points at low carrier density is dominated by a random distribution of carrier inhomogeneity referred to as “electron and hole puddles” [37]. Even at the zero gate voltage, these puddles cannot vanish all at a time. Therefore, although the average carrier density goes to zero, some electron and hole puddles still remain. As a result, the conductivity never goes to zero. Since most of the earlier theories did not take such inhomogeneity in carrier distribution into consideration, there was discordance between theory and experiment. The relativistic nature of electrons in graphene has revived an age old concept known as Klein tunnelling. With the advent of Dirac theory for a relativistic electron [38], Klein tried to study the step barrier problem within the framework of the new theory [39]. He obtained some strange results like the reflection coefficient R > 1 and transmission coefficient T < 0. The former implies that more number of electrons are reflected than are incident on the barrier while the latter implicates that transmission inside the barrier takes place in the reverse direction. When the height of the potential step tends to infinity, for a fixed energy of the incident electrons, it is observed that the transmission coefficient tends to a non-zero limit. This seemingly paradoxical result leads to the conclusion that, Dirac equation permits the relativistic electrons to pass through strong repulsive potentials without the exponential decay which is observed in quantum tunnelling process. This is referred to as the Klein tunnelling. VOLUME 2, NO. 5, SEPTEMBER 2014

FIGURE 4. Some magneto-electronic properties of graphene. (a) Conductance oscillation (Subnikov–deHass effect) with gate voltage at temperatures 20, 80, and 140 K at a constant magnetic field of 12 T. (b) Hall conductance variation showing quantized Hall effect in single-layer and bi-layer (inset) graphene along with plot of longitudinal resistance as a function of carrier concentration (which in turn depends on the gate voltage) at a magnetic field of 14 T and temperature of 4 K (figures reprinted by permission from Macmillan Publishers Ltd: Nature, c 2005). vol. 438, pp. 197–200, 

When the theory was proposed by Klein some seventy years ago, there was no scope, using elementary particles, to experimentally verify the prediction. Therefore, it remained buried in the pages of history. With the discovery of graphene, Katsnelson et al. [40] unearthed it and showed that Klein’s prediction can indeed be tested in a simple experiment with graphene using electrostatic barriers. Since then other authors [41], [42] have also established the existence of Klein tunnelling experimentally by studying the transport of ballistic carriers across the potential step of a graphene p-n junction. Such exotic behaviour of carriers in graphene has become attractive for electron devices with exceptionally new concepts [43], [44]. We now move onto the magneto-electronic properties. First we probe into those which are observed in a relatively weak magnetic field. Next we elucidate those observed in strong field. When a 2-dimensional electron system (2DES) is subjected to weak magnetic fields B at low temperatures T, an oscillation in the conductivity of the system is observed [Fig. 4(a)]. This is the well known Shubnikov–de Haas (SdH) oscillation [45]. It is a macroscopic manifestation of the inherent quantum nature of 2DES. These oscillations are 81

DASH et al.: GRAPHENE FOR ELECTRON DEVICES: THE PANORAMA OF A DECADE

periodic in the inverse magnetic field, 1/B. Studies of SdHO helps to determine some very important physical parameters. The minima of these oscillations occur at integer values of the quantity ν = nh/qB, where n is the electron density, h the Planck’s constant and q the magnitude of electronic charge. Thus the difference between two neighbouring minima can be used to estimate the carrier density directly. The cyclotron effective mass is another important parameter which can be determined by studying the temperature dependence of SdHO. Novoselov et al. [2] measured the temperature dependence of the amplitudes of SdHO at several gate voltages and magnetic fields and found that their results could be accurately fitted to an expression of the form 

Asdho = sinh

T 2π 2 kB Tmc qB



(5)

From this expression they obtained the best estimate of cyclotron effective mass mc to be somewhere between 0.02m0 and 0.07m0 where m0 is the rest mass of electron. Thus, although the Dirac fermions in graphene are massless, their cyclotron effective mass is non-zero. The SdH oscillations that we have discussed above are manifestations of longitudinal resistance phenomena of a 2DEG. Graphene also shows some interesting behaviour in its transverse resistance phenomenon which we call the Hall effect. In order to figure out the distinctive feature that graphene has shown, we have to digress a while into the arena of Hall effect [46]. For a 3D material the Hall resistivity ρxy = RH B, varies linearly with the applied magnetic field B. Klitzing measured Hall effect of a 2DEG formed in the inversion layer of a MOSFET [47]. He observed that the Hall resistance of the 2DEG shows distinct plateaus at values of RQ /N where RQ is the quantum of resistance (RQ = h/q2 = 25.812807 k) and N is an integer. This phenomenon is named the integral quantum Hall effect (IQHE). Later Tsui, Stormer and Gossard repeated Klitzing’s experiment with a sample of higher purity and at a higher magnetic field [48]. They observed plateaus of Hall resistance (or for that matter RH ) at values of RQ (P/Q) where P/Q is a fraction with no common factor. This behaviour is referred to as the fractional quantum Hall effect (FQHE). Novoselov et al. [2] and Zhang et al. [3] measured Hall effect in graphene. Although graphene is a 2D material, they observed that it neither showed IQHE nor FQHE discussed above. Single layer graphene showed Hall conductivity plateaus at half-integral values (N ± 12 , N = 0, ±1, ±2, ±3 · · · ) of 4q2 /h where as bilayer graphene had plateaus at integral values of the same with a missing plateau at N = 0 [Fig. 4(b)]. Since such behaviour could not be fit into the existing observations people called it the anomalous quantum Hall effect. That the quantum of conductivity in graphene differs from other materials by a factor of 4 is its speciality. This is understood to be due to the double spin and double valley degeneracy in graphene. Such behaviour of graphene will 82

offer the device designers with a wide scope to conceptualize novel magneto-electronic and spintronic devices. The Giant Magneto Resistance (GMR) is yet another link in the chain of magneto-transport properties of graphene. For the GMR we have to recall the absence of back scattering in graphene for long range scattering centres. However, this property disappears in the presence of magnetic field [49]. Intuitively a huge positive Magneto Resistance (MR) is expected from such behaviour of graphene. On the contrary, Bai et al. have reported experimental observation of enhanced conductance from a graphene nano-ribbon (GNR) FET by the transverse magnetic field [50]. A negative magnetoresistance of nearly 100% at lower temperature (1.6 K and 5 K) and 50% at room temperature observed by them is really surprising. More recently, adding to the list of surprises, Zhou et al. [51] have experimentally reported a linear magnetoresistance in exfoliated graphene in the extreme quantum limit. With their finding they state: “The linear MR under high magnetic fields in graphene with varying gate voltage is still mysterious.” But whether it will replace the current status of hard-disk technology is a topic worth exploration. Optical and optoelectronic properties of graphene have also fetched a lot of opportunities and challenges for electron devices. These properties are as startling as those discussed above. Although graphene is one atom thick, it absorbs a considerable 2.3% of visible light that passes through it. This figure comes out to be π times the fine structure constant α = 1/137, which can be accounted for by the Fresnel’s theory of transmittance of a thin film. Augmenting to the neverending list of distinctive features, the absorption in graphene is observed to be independent of wavelength; the (absorption) curve is flat from terahertz to ultraviolet frequencies [4]. In addition graphene shows saturable absorption when subjected to intense illumination [20]. This is attributed to the fact that a relatively slower decay process in the conduction band keeps it occupied longer and further (photoexcited) electrons from the valence band trying to get into it are prevented by the Pauli blocking. The slowly decaying electrons are expected to offer ample opportunities to harness the optical energy in a variety of ways [20]. It is rather exciting to note that a single (highly energetic) photon can generate several (hot) electron-hole pairs in graphene [52]. Although energy conservation is fundamental to any process, a quantum efficiency of more than 100% is evocative, a figure not yet achieved in any material. Such a process, together with the broad spectrum absorption property of graphene, is expected to bring a revolution in the silicon dominated solar cell industries. In a step forward to the understanding of the photoconductivity mechanism, Freitag et al. measured photocurrent in biased graphene [53] and observed polarity reversal of it with back gate voltage sweep. Their contention to such behaviour is attributed to the photoresponse competing between two mechanisms what they termed the photovoltaic effect and the photoinduced bolometric effect. From the device designers’ point of view, such findings will open up new ways for a novel VOLUME 2, NO. 5, SEPTEMBER 2014

DASH et al.: GRAPHENE FOR ELECTRON DEVICES: THE PANORAMA OF A DECADE

optoelectronic device. Setting aside some more common optoelectronic properties of graphene to Section VIII we move on to another interesting property referred to as the chirality. Chirality is in fact an addition to the wonders of graphene. The electron states in graphene are chiral in the sense that the amplitude of electron wave function is not independent of its direction of propagation. Apart from chirality, Berry’s phase is another term which pervades the literature on graphene physics. Berry’s phase is an extra phase acquired by the electron wave function from a cycle, when the system undergoes a cyclic adiabatic process. This results from the geometrical properties of the parameter space of the Hamiltonian. Although the phenomenon existed since 1956 it was rediscovered in 1984 by M. V. Berry [54]. Making out fundamental details of these electronic properties is vital to the development and optimisation of graphene-based electron devices. In this respect Liu et al. [55] have demonstrated, through a novel experiment, that electron states in graphene are not only chiral but also possess a non-trivial Berry’s phase of π in monolayer graphene and 2π in bilayer graphene. A succinct assessment of graphene for electron devices would not be complete without considering its thermal behavior. In fact, the thermal conductivity of a material has a strong bearing on its suitability for application in nanoelectronic devices. It is desirable that the heat generated in the device should be conducted away efficiently for safe operation. A high thermal conductivity is therefore an added advantage. In this respect graphene is also distinct. The inplane thermal conductivity of isotropically purified freely suspended sample of graphene at room temperature has an incredibly high value of 4000 Wm−1 K−1 [56], [57] surpassing the most familiar Cu by an order. However, for practical samples supported on SiO2 , the value reduces to 600 Wm−1 K−1 [58]. Encasing the graphene in SiO2 further reduces the thermal conductivity to 160 Wm−1 K−1 [59]. Similarly, GNR supported on SiO2 records a drastically low value of 80 Wm−1 K−1 [60]. It is instructive to compare these figures with Si as 150 Wm−1 K−1 in bulk, 25 Wm−1 K−1 in 20 nm film and 2 Wm−1 K−1 in 20 nm nanowire [56]. Notably one can observe that there is a systematic degradation of thermal conductivity with increase in interfacial surfaces and edges with other materials. Therefore, the environmental conditions strongly influence the thermal conductivity of graphene. The heat conduction mechanism in graphene is mostly through acoustic phonons. The electronic contribution is only 1-2%; but it can be significant in doped samples. The strong sp2 bonding results in efficient heat transfer by lattice vibration. When the phonon modes of graphene are coupled with or scattered from the vibrational modes of the interfacial material, thermal conductivity decreases [56]. It is surprising to note that the out of plane thermal conductivity of graphene is only 6 Wm−1 K−1 because of the weak interlayer van der Waals interaction. The weak VOLUME 2, NO. 5, SEPTEMBER 2014

coupling of graphene with the substrate (like SiO2 ) through the same van der Waals interaction is also responsible for poor cross-plane heat flow from the graphene to the substrate. The excellent in-plane heat conduction property is potentially valuable for all electronic and photonic devices. Nonetheless, the poor cross plane conduction of heat may pose a serious bottle-neck. Additional issues relating to thermal behavior of graphene can be referred from the independent reviews at [56], [57]. B. BILAYER GRAPHENE AND GRAPHENE NANORIBBONS

Bilayer graphene shares almost all the properties that monolayer graphene has. But the electronic band structure has a notable difference at the low energy. Unlike the linear dispersion in monolayer graphene, bilayer graphene has a parabolic dispersion but without a bandgap as in monolayer. Therefore, bilayer graphene is characterized by massive chiral quasi particle rather than masssless ones [61], [62]. This gives an integral QHE in bilayer graphene compared to the half integral QHE in monolayer sample [Fig. 4(b)]. The other advantage of bilayer graphene is the possibility to address each layer separately with the advantage of new functionalities [63]. In addition it has a tunable bandgap capable of control through the gate bias and doping. All the electronic and photonic devices which can be visualized with monolayer graphene can also be envisioned with bilayer graphene. The opening of bandgap in bilayer graphene has the particular advantage in digital logic devices (discussed in Section IV) for switching off the FET. Graphene nanoribbon (GNR) is the outcome of the pursuits for novel engineered structures motivated to induce a bandgap in the otherwise gapless graphene. As the name suggests, GNR is a long graphene sheet with substantially reduced width so that the carriers are confined in the lateral (width) direction. Carrier confinement in the quasi onedimensional structure gives rise to sub bands (with gaps in between), within the conduction and valance bands, leading to the possibility of a bandgap. The bandgap and other electrical properties of GNR are different for its two variations known as Zig-Zag (ZZ) GNR and the Arm-Chair (AC) GNR. The names bear a close resemblance with the type of confining edges of the GNR. In ZZ GNR the carbon atoms at the edges are arranged in a zig-zag fashion with (only) A-type carbon atoms on one boundary line and B-type atoms at the other (Fig. 5). On the other hand, the arrangement of atoms in the AC GNR mimics an arm chair with each of the boundary lines containing both A and B atoms in alternation (Fig. 5). Due to such difference in arrangement of carbon atoms at the edges, the electron wave function has different boundary conditions in the two cases of the GNR, leading to somewhat different electrical properties. While the ZZ GNR is always metallic in nature, the AC GNR could be metallic or semiconducting depending on the width of GNR [16]. GNR can be synthesized using different approaches such as lithographic patterning [64], chemical derivation [65] and unzipping carbon nanotube [66]. The report at [64] observed 83

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FIGURE 5. Lattice structures of zig-zag and arm-chair graphene nanoribbons.

that the width (W) dependence of energy gap (Eg ) of all the devices they considered, followed an empirical relation of the form Eg = α/(W − W ∗ ) where α and W ∗ are fitting parameters with values α = 0.2 eV nm, and W ∗ = 16 nm. Energy gap as high as 200 meV is obtained by an engineered width as narrow as 15 nm. However, they did not observe any dependence of bandgap on crystallographic direction. The report at [65] developed a chemical route to synthesize GNR of ultra smooth edges and observed that all the sub10-nanometer GNRs were semiconductors which facilitated the fabrication of GNR FET with an on-off ratio of 107 at room temperature. While GNR research started with a view to induce bandgap, researchers have also explored other possibilities. To this end a recent report is noteworthy [67]. Here the authors prepared a 40 nm wide GNR, epitaxially grown on SiC, and observed a ballistic transport in excess of a distance of 10 μm. In addition, they observed an equivalent sheet resistance of their GNR below 1 ohm per square which surpasses the theoretical prediction by more than an order of magnitude. The epitaxial GNR is thus expected to be significantly important in advanced nanoelectronics. C. GRAPHENE-LIKE MATERIALS

With the emergence of graphene as a 2D material, researchers have explored the possibility of monolayers of other graphene like materials. In this context, the 2D hexagonal Boron Nitride (hBN) can be seen with a lot of prospects [68]. In addition, monolayers of transition metal dichalcogenides MX2 (M = Mo, Nb, W, Ta; X = S, Se, Te) have also drawn considerable attention [69]. These reduced dimensional materials (particularly MoS2 ), in themselves can find independent places in the arena of electron devices. But when combined with graphene, these materials can not only address many of the issues that graphene is currently facing but can lead to novel functionalities with graphene based electron devices. We shall discuss the 84

impact of graphene-like materials on graphene devices in this subsection. Boron Nitride exists in four polymorphs: hexagonal, cubic, rhombohedral, and wurtzite. The hexagonal phase is structurally similar to graphite except that graphite has AB stacking sequence (A carbon atom over B and vice versa) while BN is stacked with boron on top of nitrogen and vice versa. In a monolayer of hBN, the boron and nitrogen atoms form a 2D honeycomb structure similar to graphene with strong in-plane covalent bonds and weak interlayer bonds. The micromechanical cleavage is therefore an effective method to extract monolayer from bulk BN [68]. Despite the structural similarity, properties of graphene and hBN differ considerably. While graphene is gapless, hBN has a large bandgap of about 5.9 eV. Thus hBN is an insulator (some people call it a wide-bandgap semiconductor) where as graphene is a semimetal. But the properties of hBN which are more suited for graphene based nanoelectronics are its atomically flat inert surface free from dangling bonds, and a close crystal matching (with only 1.7% difference) with graphene. These properties help in reducing the surface roughness that graphene otherwise develops on oxide surfaces. Consequently the charged impurity scattering centers in the supporting and gate dielectrics and graphenedielectric interfaces, are strongly suppressed. It turns out that graphene mobility on hBN dielectric is significantly augmented. This is demonstrated by several researchers for exfoliated graphene [70], [71], CVD graphene [72], [73] and also for epitaxial graphene [74]. Novel device architecture with BN/Gr/BN heterostructures [75] and Gr-BN stitched atomic layers [76] have also been demonstrated. A more detailed account of the state-of-the-art and prospects of graphene based on h-BN dielectric can be seen from the review at [77]. Out of the numerous transition metal dichalcogenides, monolayer of MoS2 has attracted a great deal of attention for theoretical study and nanoelctronics applications [78]– [82]. MoS2 is also capable of forming layered structure like graphene. The weak interlayer force helps to obtain monolayer of MoS2 with mechanical exfoliation. Monolayer of MoS2 is a semiconductor with a direct bandgap of 1.79 eV. The carrier mobility is however much less (∼ 190 cm2 V−1 s−1 ) than that of graphene. Although the above reports reveal that the monolayer of MoS2 is capable of an independent material for electron devices, when combined with graphene, it promises novel functionalities with outstanding performance [83]–[85]. A more detailed account is however, the subject matter of an independent review. III. GRAPHENE PROCESSING TECHNOLOGY

The growth in graphene process technology has been instrumental in the recent development of graphene based electron devices. Novoselov et al. [1] laid the foundation for graphene process technology, in 2004, with the ground breaking report on the micromechanical exfoliation method for obtaining graphene in its isolated form. VOLUME 2, NO. 5, SEPTEMBER 2014

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Since then numerous reports from researchers are flooding into the domain of graphene growth and process technology with persistent efforts to transfer graphene from the research laboratory to the industry. Today, graphene has been obtained following many different methods like the epitaxial method [86]–[88], Chemical Vapour Deposition (CVD) [89]–[91], Liquid Phase Exfoliation (LPE) [92], electrochemical method [93]–[95], thermal decomposition [96], and chemical synthesis [97], [98]. Recently, Bonaccorso et al. [99] have reviewed the potential methods for graphene synthesis. But as yet, the industry is not decisive to choose a particular process since no report is able to meet all the required industry standards like size, quality, reliability, scalability and minimum variability. Further, the cost of production and the development in characterization tools for graphene matter a lot. In the chain of the device fabrication process, the first challenge is to obtain a high quality graphene. Out of the several methods stated above three major ways to obtain high quality graphene are worthwhile considering here. They are (i) micromechanical exfoliation, (ii) thermal decomposition of SiC, and (iii) chemical vapor deposition. Micro mechanical exfoliation, though not an industry standard process, is an easy and low cost way to obtain flat and single layer graphene. The electrical quality is also high as supported by reports on high mobility [30] and low defect density [36]. It is also a widely used process for university level researches. But, there are several drawbacks that limit its uses by a device engineer. One has to have patience as it is a matter of probability to get graphene single layer out of many attempts. One has also no control over the size and number of layers of the graphene obtained following this process. It is also not scalable and fails to meet the high volume manufacturing (HVM) requirements. The issues to be addressed also include the interfaces of graphene with metal and dielectrics [19]. The authors therefore feel that this process cannot be helpful in accelerating the journey towards the feasibility of graphene based electron devices. Graphene is also grown on SiC (Si and C faces) which is widely referred to as the epitaxial graphene. The process, pioneered by De Heer [86]–[88], [100], is useful for large scale production of graphene needed for the electronics chip industry. Here SiC is thermally decomposed at a temperature higher than 1000◦ C whereby Si evaporates from the substrate and C rearranges itself into hexagonal form, unlike the conventional epitaxial growth where one material gets deposited over a substrate. The growth rate of graphene on SiC depends on the SiC crystal face. Faster growth of graphene has been observed on the C-face than on the Si-face. Hass et al. [101]–[102] have reported growth of rotationally disordered, large domains (200 nm) of multilayered graphene on the C- face whereas small domains (30–100 nm) of multilayered graphene are obtained by UHV annealing on Si face. Annealing causes morphological changes in the surface leading to small domains. As expected, the material properties differ for graphene grown on Si- face and C-face [87]. The room temperature mobilities for graphene VOLUME 2, NO. 5, SEPTEMBER 2014

grown on the Si-face have been reported to be smaller (500 – 2000 cm2 V−1 s−1 ) [87] than those grown on the C-face (10000 – 30000 cm2 V−1 s−1 ) [87]. Some other authors report mobility as high as 150000 cm2 V−1 s−1 on the C-face and 5800 cm2 V−1 s−1 on the Si-face for near intrinsic samples [103], [104]. The success of epitaxial graphene can be seen from the numerous reports published. These include top gated transistors on a wafer scale [105] and high frequency transistors with 100 GHz cut-off frequency [106] which is higher than the state-of-the-art Si transistors of the same gate length [14]. In addition, epitaxial graphene has been developed as a novel resistance standard based on the quantum Hall effect (QHE) [107]. The favourable features of this process technology lies with the facts that SiC as a substrate is already established and its technology has come of the age. We get excellent electrical quality flat surface single layer or multilayer graphene without the need to transfer it to a substrate. It thus seems a viable route for the industry to fabricate graphene devices. On the other hand, there are some drawbacks to be addressed. This is an expensive process as the cost of SiC wafer is high. It is also a high temperature process and the size is limited to available SiC crystal. The small grain size is a severe drawback for (High Volume Manufacturing) HVM requirements of industry. Further, there is a large crystal mismatch between graphene and SiC substrate resulting in defects, which in turn corrupts the device properties. When one wishes to transfer it to a matched substrate or exfoliate SLG (Single Layer Graphene) for specific purpose, the transfer is difficult and it has not yet been achieved. Chemical vapour decomposition (CVD) is the most favoured process in semiconductor industry. Composition control and large scale manufacturability are the main two advantages in addition to the excellent electrical quality of the grown graphene. In this process a mixture of methane and hydrogen gas is passed through a chamber at 800◦ C containing a substrate coated with some catalyst metal like Ni, Cu, Co, Pt and Ru. In presence of the catalyst metal, at high temperature, methane decomposes into carbon and hydrogen. The hydrogen gas passes out of the chamber while the carbon gets deposited on the metal to form graphene. Ni was the first metal to be used for this purpose. Mostly graphene multilayers were grown on Ni by CVD while single layer graphene appeared with only small patches [89]. The reported mobility values were in the range from 100 to 2000 cm2 V−1 s−1 . Li et al. [108] successfully demonstrated the growth of graphene single layer on large Cu foil. They also developed graphene film transfer process to arbitrary substrate. The reported room temperature carrier mobility (∼4050 cm2 V−1 s−1 ) for a dual gated FET fabricated on Si/SiO2 substrate signifies the superior electrical quality of graphene grown on Cu than those obtained with Ni [89]. Growth of graphene on Cu by LPCVD was scaled up in 2010 [91] to a Cu foil of size 30 inches, producing films with mobility, μ = 7350 cm2 V−1 s−1 at 6 K. Large grain (20 μm – 500 μm) graphene on Cu, with subsequent transfer to SiO2 on Si, with mobility ranging 85

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TABLE 1. Properties and performances of three major growth techniques of graphene showing their relative merits and demerits

from 16400 cm2 V−1 s−1 to 25000 cm2 V−1 s−1 at room temperature, has also been reported [109], [110]. There have also been reports on large area CVD grown single layer graphene on Co, Ir, Pt and Ru [111]–[114]. These catalysts are supposed to provide better thermal stability than Cu. But they pose an additional difficulty in etching due to high carbon solubility in them. The carbon solubility and associated cooling rate play major role in determining the number of graphene layers. It has been observed that graphene is grown on Cu substrate by a surface-catalyzed process (surface adsorption) whereas carbon dissolves in metals like Ni, Co etc. and precipitates to form graphene. The difference in process results in different types of graphene. In case of Cu, the growth process ceases as soon as the Cu surface is covered with graphene. It is thus a more suitable process for the single layer graphene compared to the multilayer graphene. On the other hand, the growth on Ni, Co etc is preferable for multilayer graphene as it is difficult to obtain large area single layer graphene from such process. CVD on dielectric surface has an advantage; there is no need of transfer through the metal intermediary [115]. In this context, the research community has been successful in growing graphene on hexagonal boron nitride, magnesium oxide, and cobalt oxide [116]–[118]. A radio frequency plasma enhanced chemical vapour deposition system has also been used to synthesize graphene on substrates like Si, W, Mo, Zr, Ti, Cr, SiO2 , and Al2 O3 [119]. This process suppresses the formation of amorphous carbon and other unwanted by-products. Despite several advantages, CVD lacks the flatness obtained in case of epitaxial graphene. It requires further cleaning and etching. The metals used have their relative merits and demerits. Although Cu is the preferred metal at present, it has the disadvantage of high Cu 86

vapor pressure. It is also a surface limited growth process and the growth ceases as the Cu surface is covered with graphene, thus making it difficult for the growth of bilayer or multilayer graphene even after extended growth period. A comparative account of the three major processes discussed above is presented in Table 1. One of the common requirements in device integration is transfer of graphene to a suitable substrate. It is very difficult to transfer graphene grown on SiC whereas the transfer of CVD graphene is easy. A number of processes like wet [120], dry [121], roll-to-roll [91], and electrochemical [122] have been adopted for the transfer of CVD graphene where as mechanical exfoliation with Ti adhesion layer has been followed for epitaxial graphene [123]. The contaminants introduced by the transfer process cause considerable deviation in the ideal material characteristics of graphene. Yet, there are high expectations from the rollto-roll process [91] for growing large area graphene with substantial material quality. The developments of graphene integration with metals and dielectrics are significant in the realization of graphene integrated circuits (IC). Dielectrics play major role in isolating the external gate electrodes from the device. Its deposition on graphene is not an easy process. This is because the surface of graphene is inert under normal process environment. Nonetheless, there are a few dielectric materials that can be deposited with some chemical constraints [124], [125]. Alternatively, functionalization of graphene surface [126]– [130] overcomes the chemical inertness facilitating dielectric deposition. Atomic Layer Deposition (ALD) is also an effective technique for high-K dielectric growth on graphene by providing intentional nucleation sites. Kim et al. [131] deposited a thin Al layer of 1-2 nm on the graphene surface by e-beam evaporation before the ALD treatment. This VOLUME 2, NO. 5, SEPTEMBER 2014

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served as the nucleation layer. After Al deposition the sample is taken out and transferred to the ALD chamber where trimethyl aluminum (TMA) and H2 O were used as source and oxidizer respectively for the deposition of Al2 O3 . Shin et al. [132] have also demonstrated atomic layer deposition (ALD) of high-K dielectrics on graphene using ultrathin functionalized graphene (FG) as an effective seed layer. Although several methods have been proposed for dielectric deposition on graphene there are several challenges such as deposition of uniformly thin dielectrics, minimization of defect density, surface cleaning, deposition of scaled dielectrics, growth of graphene directly on dielectrics, minimizing its effect on the ideal transport properties, and finally finding an ideal (or nearly ideal) dielectrics. Hexagonal boron nitride (hBN) [133] is now being considered as a potential dielectric for graphene devices. As stated earlier, graphene and hBN are both 2-D materials and nearly lattice matched to each other. It is thus expected to reduce the substrate induced disorder and can yield high electrical quality. Excellent carrier mobility has been reported for exfoliated graphene with boron nitride as substrate [133]. Extensive research works [134]–[136] are in progress for industrial realization of graphene growth on hBN. Successful device application involves development of metal contacts with low resistance. The chemical reaction of graphene with metals is of prime consideration. Some metals react to either damage or dissolve the carbon on graphene while some others like Cu, Ag, Au, Pd and Ir form good contacts without causing harm. A good review on the graphene-metal contact has been reported by Robinson et al. [137]. The reported metal contact resistances are still very high compared to the industry standard available for Si devices. In addition there may be defects arising out of the metal contacts [138]. The defects as well as contaminants contribute a significant amount of noise [139]–[141]. Some efforts to reduce the noise are noteworthy [142]–[144]. Finally, the interconnects between graphene devices are also facing challenge. In this connection, the report by Kang et al. [145] has not only addressed the interconnects using CVD graphene but has addressed the issues like variability and feasibility. IV. DIGITAL LOGIC DEVICES

Silicon based CMOS inverters are the basic building blocks of digital ICs. Their performance is limited by the speed with which the FET can be switched on and switched off. This in turn depends on, among other factors, how fast the electrons can move and how far they have to move for an effective switching. These two factors ultimately put down the leverage on the mobility/velocity of the material and the channel length of the FET. Silicon, in spite of its low mobility/velocity, continued to rule over the digital industry because of its most matured processing technology with multibillion investments. The technology however, is fast approaching its limit due to the rapidly shrinking device dimensions resulting from the scaling effect. With VOLUME 2, NO. 5, SEPTEMBER 2014

the discovery of graphene, researchers were very hopeful that it would be a potential candidate to replace silicon. But very soon graphene tumbled into difficulty. Being gapless, graphene does not allow the FET to switch off resulting in a high leakage current and prohibitive energy dissipation. Several attempts to induce bandgap in graphene include cutting the graphene into nanoribbons [146], surface functionalisation [147], subjecting bi-layer graphene to electric field [148], [149] and strain engineering [150]. These attempts nonetheless, have resulted in bandgaps of few hundred meV only where as practically to make graphene suitable for digital logic devices, it requires a bandgap on the order of an eV at room temperature. Most researchers [97], [151], [152] tried to change the bandgap in graphene to make it more suitable for application in logic circuits, but the outcome of these efforts resulted in degradation of graphene properties like the mobility, which was the prime attraction. Although a density functional theory calculation predicts that a bandgap of 1.2 eV can be induced in graphene [153] through surface functionalisation, the experimental observation is contrary to the prediction [154]. Thus, opening of bandgap in graphene has still not yielded any industry standard breakthrough. The absence of required bandgap makes it difficult to achieve suitable on/off switching ratio for low power dissipation. Alternative graphene transistor architecture by Britnell et al. [155], based on quantum tunnelling from a graphene electrode through thin insulating barrier layers of hexagonal boron nitride (hBN) and molybdenum disulfide, reported room-temperature switching ratios of ≈50 and ≈10,000, respectively. Such graphene FETs have shown potential for high-frequency operation and large-scale integration. The report also suggests that the switching ratio can be enhanced with optimized architecture and has opened a new area of research to explore the prospects of field effect tunnelling transistors for possible applications in graphene nanoelectronics. Zhao et al. [156] recently proposed an analytical model of a symmetric tunnelling field effect transistor (SymFET) to calculate the channel doping potential and current voltage characteristics. The model explains the current flow by tunnelling from n-type graphene layer to p-type graphene layer with a large current peak when the Dirac points are aligned by suitably controlling the drain-tosource bias potential. It also suggests that SymFET will be a fast device due to the tunnelling current. The observed symmetric resonant peak also speaks about the potential for high speed analog applications. The analytical expression for the on/off ratio indicates that it can be increased with graphene coherence length and doping. In yet another attempt, multi function and reconfigurable logic model based on graphene p-n junction was introduced by Tanachutiwat et al. [157]. Three coplanar split gates with three top contacts made to a graphene sheet are used to realize the switching characteristics and different logic functions. These gates modulate the graphene properties and can dynamically reconfigure the circuit. Significant speed advantage, excellent 87

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transfer behaviour, scaling approach, device fabrication, and its integration with CMOS are also touched upon by them. In spite of the difficulties due to zero bandgap, research on graphene FET has never relented. The fabrication of first integrated logic circuit may be credited to Traversi et al. [158]. They used exfoliated graphene to fabricate their complementary inverter. The process therefore, cannot be extended for mass production at the industrial level. In addition the inverter did not show matching between the input and output signals. To improve upon the early work [158], Rizzi et al. fabricated an inverter with CVD grown graphene on wafers [159]. This device is not only capable of room temperature operation with matched signals but also is suitable for mass production. The matter however, did not end here. A single inverter is not of any use unless it is capable of cascading to form complex integrated circuits. The output voltage from the gate should be sufficient to drive other gates ahead in the circuit. This in turn requires that the intrinsic voltage gain (ratio of transconductance to output conductance) of the FET should be greater than one. But most of the graphene FETs have this parameter less than one. As an important landmark in graphene based logic devices, Rizzi et al. realized the first integrated wafer-scale graphene logic gates capable of cascading; an intrinsic voltage gain as high as 5 and the ability to operate in ambient air and temperature are the important features of these gates. However, the graphene FETs cannot be turned off in either of the two logic states. It significantly affects the performance in terms of voltage swing and static power dissipation. The in/out voltage swing of ∼22.4% of the supply voltage reported, is much less than the voltage swing in traditional semiconductor CMOS logic (almost 100% of the supply voltage). Nonetheless, it is more than the typical swing of 15% [159] in emitter coupled logic (ECL) gates. The power remains almost the same (≈98%) and does not reach zero on either side of the operating point. Consequently graphene inverters dissipate power regardless of the operating point. On the other hand, the power reduces to zero on either side of the operating point in Si inverters approaching rail-to-rail operation and thus eliminating the static power dissipation. So, power remains a major concern in an attempt to migrate from Si logic circuits to graphene logic circuits. Yet, it will fulfil the requirements of high speed digital circuits when the economy of power shall not be a matter of concern. Gigahertz integrated graphene ring oscillator (RO) [160], fabricated from wafer scale monolayer CVD graphene, has been demonstrated recently with the highest oscillation frequency of 1.28 GHz. The largest output voltage swing for the graphene RO was 0.57 V. It is also expected to be more robust to variations in supply voltage compared to conventional ROs. It is the first integrated graphene oscillator of any kind and points towards the potential of graphene ICs. Apart from the conventional approach, researchers have also mulled over some different approaches to incorporate graphene in digital logic circuits. As an innovative approach to induce logic functionalisation in graphene, Banerjee et al. 88

FIGURE 6. Double top-gated He ion irradiated graphene FET. (a) Schematic representation of the FET structure. (b) More detailed layout of the gates and graphene with heavy dose and controlled dose irradiation. Figure reproduced from [162].

used a vertical tunneling structure using bilayer graphene resulting in a device called BiSFET (Bi-layer pseudoSpin Field Effect Transistor) [161]. The structure modulates inter-layer tunnelling in bilayer graphene by using exciton condensation. This structure seems to work with an exceptionally low energy. In another approach researchers demonstrated a new class of graphene transistors [162]. The basic structure of the transistor consists of two top gates between the source and the drain [Fig. 6(a)]. By bombardment of the graphene sheet between the two gates with a heavy dose of helium ions, the sheet goes insulating while a small region of the sheet (20 nm × 30 nm) between the gates is kept conducting by a controlled dose [Fig. 6(b)]. This small region serves as the channel. The graphene transistor can be made ON or OFF by reversing the polarity of one of the gate. An ON to OFF ratio of 103 at 200 K may not be encouraging but the approach is innovative and refrains from bandgap engineering. A third approach takes advantage of the gapless nature of graphene which prevents the current-voltage characteristic from saturation and gives rise to multiple linear regions interspaced by differential negative resistance regions. While for the conventional FET applications, these features are hazardous, Guanxiong et al. [163] have followed VOLUME 2, NO. 5, SEPTEMBER 2014

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an approach to use them as advantages. They have chosen to modify the logic of the transistor to a “viable non-boolean computational architecture.” With their results they say that “the obtained results present a conceptual change in graphene research and indicate an alternative route for graphene’s applications in information processing.” But then switching over to a new architecture relies on a lot of logistics and heavy funding. V. ANALOG RF DEVICES

RF devices are generally characterized by their cut-off frequency (fT ), maximum oscillation frequency (fmax ), and power gain. Cut-off frequency is the upper limit of the useful frequency where the short circuit gain drops off to unity. An expression for cut-off frequency, one of the most widely mentioned figures of merit for RF devices, can be written as [14] fT =

1 gm × 2π (CGS +CGD )[1+gDS (RS +RD )]+CGD gm (RS +RD ) (6)

where the symbols gm , CGS , CGD , gDS , RS and RD denote intrinsic transconductance, gate-source capacitance, gatedrain capacitance, drain conductance, source resistance and drain series resistance respectively. Higher cut-off frequency can be obtained by increasing the intrinsic transconductance gm and decreasing the values of all the capacitances CGS and CGD , drain conductance and series resistances RS and RD . It is also worth to mention here that these parameters can be optimized for higher cut-off frequency by reducing the gate length. The peak fT is inversely proportional to the square of channel length [14], [164], [165] and increases with a reduced gate length. Researchers are consistently trying to push the cut-off frequency to a higher value with the increasing demand on the high frequency applications. As mentioned earlier the reduction in gate length will soon reach its fundamental limit. Further, reduction in gate length has adverse effects on device performance commonly known as the short channel effects. The cut-off frequency can also be enhanced by boosting the transconductance which is dependent on the mobility. Mobility can be enhanced by novel design concept like the HEMT or choosing a new material. The technological roadmaps, for the existing Si and III-V compound semiconductor technology, encourage exploring new promising materials for future RF applications [166]. This is where graphene comes into the picture. The high mobility of graphene is seen with a lot of hope to push the cut-off frequency into the terahertz regime [167]. Further, graphene being a planar one atom thick material can be scaled to smaller gate length to achieve higher cutoff frequency in graphene FETs. It is also an established fact that the short channel effects can be minimized with thin channels. Thus graphene owing to its 2D structure has the potential to reduce the short channel effects. In addition it is also believed that graphene will alleviate the channel series VOLUME 2, NO. 5, SEPTEMBER 2014

resistance which is an important source of degradation in the FET performance [168]. Last five years have witnessed significant improvement in graphene based RF device technology. The first experimental report on the RF analysis of graphene FET was done by Meric et al. in 2008 [167]. They demonstrated a cut-off frequency (fT ) of 14.7 GHz for a 500 nm length device. In 2009, a comprehensive experimental study by Liu et al. [130] obtained a cut-off frequency as high as 26 GHz for a gate length of 150 nm while Moon et al. obtained a cut-off frequency of only 4.4 GHz [169]. Thereafter, the progress with cut-off frequency is enthralling with the value reaching a land mark of 100 GHz in the very next year. Lin et al. [170] were successful to measure cut-off frequency as high as 100 GHz, for a gate length of 240 nm, at a drain bias of 2.5 V. They used epitaxial graphene formed on the Si face of a semiinsulating, high purity SiC wafer by thermal annealing at 1450◦ C for that particular experiment. This value of cutoff frequency not only exceeded previously reported cut-off frequency of 4.4 GHz [169] and 26 GHz [130] but also started a kind of competition to obtain higher cut-off frequencies. In the same year Liao et al. [171] reported even higher cut-off frequency in the range 100-300 GHz using a self aligned approach to fabricate graphene FETs with ultra short gate length. Subsequently, they reported sub-100 nm channel length graphene transistors with a projected intrinsic cut-off transit frequency (fT ) reaching 700–1400 GHz [172]. Wu et al. [173] used CVD graphene for their FET and obtained a cut-off frequency of 170 GHz at 90 nm gate length. More recently, Zheng et al. have reported sub-10 nm gate length graphene transistors operating at terahertz frequencies [174]. In their simulation study, they have reported that cut-off frequency (fT ) as high as a few tens of THz is achievable by continuously shortening gate length and opening a bandgap. Other than simulation, there is no experimental report supporting the terahertz capability of graphene. Parish and Akinwande [175] using a physics based self consistent model have shown that poor contacts and large access resistance can decrease gm and fT by more than one order of magnitude. The parasitic resistances from access regions and contacts, if not minimized, may thus limit the terahertz capability of graphene FETs. One major challenge for the device community is to reduce the variability in mobility that generally creeps into the RF FET due to different growth and device integration processes involved. The charged contaminants that are trapped during the growth process have been held mainly responsible for the variability in mobility of graphene [176]. The degradation in material properties prevents graphene from exhibiting its full potential. Significant amount of work is devoted to study the effects of charged impurities. The potentials of highK dielectrics are also explored. But dielectric deposition is not up to standard. Works are also in progress to find suitable substrates to obtain mobility close to its expectation. It has thus been a tough task to exploit graphene for high mobility electron devices useful for RF applications. The first 89

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BN/graphene/BN FET [75], which has hBN both as substrate and gate dielectric, is an effort to preserve the high carrier mobility in the bilayer graphene (BLG) channel. Significant improvement in peak f T (33 GHz) is observed with this novel structure indicating its potential for RF applications. Boron Nitride thus promises a tremendous potential for next generation RF application based on graphene electronics. One more relevant figure of merit for RF transistors is the maximum frequency of oscillation, f max , at which the power gain becomes unity. Much attention is needed to focus on f max while analysing the performance of graphene transistors. The value of maximum oscillation frequency (fmax ) is lagging behind the cut-off frequency by an order and is still a few decade behind the state-of-the-art. Liao et al. have reported maximum oscillation frequency as high as 56 GHz. There is a huge gap between the reported f max performance of graphene FETs and that of industry standard Si and III-V RF FETs. Substantial amount of work is needed to fill the gap. There are two ways in this pursuit [177], [178], such as (i) lowering the contact resistance, and (ii) achieving a strong current saturation. The impact of gate electrode resistance on high frequency properties of graphene FET has been systematically analysed [179]. The f max is reported to increase with decrease in gate resistance while no change is observed in f T . The relative rate of increase of f max to f T remains the same for devices with proportionately scaled channel dimensions. Lowering the gate contact resistance is possible through progress in graphene processing technology. Unfortunately, a reliable way of significantly reducing such contact resistance is still lacking. Improving the current saturation characteristics is observed to be strongly dependent on opening a bandgap because the weak current saturation behaviour in graphene is attributed principally to the absence of bandgap. Several methods to induce bandgap in graphene have been indicated in Section IV. Whereas logic devices require a bandgap of at least 1 eV, bandgaps of a few hundred meV are sufficient to improve the saturation current behaviour of RF devices significantly. The IBM groups have been consistently pursuing to improve the RF characteristics of graphene. They have recently demonstrated performance of graphene integrated circuit [180]. The circuit was designed to operate as a radio frequency receiver capable of performing signal amplification, filtering and down conversion mixing. Digital texts were received and restored on a 4.3-GHz carrier signal. Still, there are several issues to be addressed while graphene can practically establish itself as a true competitor to the Si and III-V semiconductor based RF devices. The issues involved include growth and transfer of high quality graphene, improved contact resistance, suitable high-K dielectric deposition and proposal for new device layout. VI. MODELING AND SIMULATION

Modelling and simulation constitute an integral wing of device research. They not only enhance the understanding of the essential device physics but also save a lot of resources 90

that may be wasted in fabricating an unoptimised device. We may recall that the graphene properties have been mostly studied employing some MOSFET like structures. For that reason the modelling studies have largely clustered around the graphene based MOSFETs. Keeping these in view and to protect this document from being prohibitively large, we shall limit our discussion to modelling and simulation of such devices; we shall shortly refer to them as the GFETs. In GFET the simplest modelling approach primarily aims at deriving an expression for the drain current. Starting from the very basic, the expression can be written as

−qW L ρs (x)v(x)dx (7) IDS = L 0 where q is the electronic charge, W the channel width, L the channel length and ρs (x) and v (x) are respectively the charge per unit area called sheet density and the carrier velocity, at any point x in the channel. Now it remains to model ρs (x) and v (x). In the graphene channel the sheet charge density can have basically four sources: (i) the intrinsic charge [181], (ii) the charge induced by the gate bias [2], [181], (iii) the charge due to intentionally or unintentionally doped impurities, and finally (iv) the charge due to the quantum capacitance [181]. The intrinsic charge in graphene is its thermal equilibrium value when it is free from any source of perturbation like applied bias and illumination. In this situation the Fermi level (EF ) is exactly at the Dirac point i.e. EF = 0 eV. Following this, an expression for the intrinsic sheet density, identical for both electrons and holes, is derived as [181]   π kB T 2 ni = pi = (8) 6 vF where kB is the Boltzmann constant and T the absolute temperature. This equation is indicative of a square-law temperature dependence of intrinsic carrier concentration in graphene. This is in contrast to the exponential dependence observed for intrinsic semiconductors. Further, the intrinsic sheet density depends on only one material parameter i.e. the Fermi velocity. At room temperature this is of the order of 1011 cm−2 . The concept of quantum capacitance was introduced by Luryi in 1987 [182]. This arises whenever a 2DEG is embedded in the dielectric between two plates of a capacitor. The inversion layer of the MOSFET and the graphene layer in the GFET are best examples of this. The system can be viewed as a three plate capacitor with the top-gate contact as the first plate, the 2DEG as the second and the back-gate (or substrate) contact as he third. If the 2DEG is replaced with a metal plate (grounded), the electric field due to the top-gate is completely shielded by the second plate from reaching the third. But for 2DEG, the electric field partially penetrates through it and induces charge on the lower surface of second plate and upper surface of the third plate. This implies that the 2DEG offers a capacitance referred to as the quantum capacitance. It arises due to the Pauli’s exclusion VOLUME 2, NO. 5, SEPTEMBER 2014

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principle requiring the carriers to have some extra energy in order that they can be accommodated in the allowed bands of the 2DEG system. The quantum capacitance is a manifestation of this extra energy. An expression for the sheet carrier density due to the quantum capacitance can be written as [181]   π Cox vF 2 (9) nQ = 2 q2 where Cox = εox /tox is the capacitance per unit area of the oxide layer between the top-gate and the graphene, εox is the permittivity and tox the thickness. The gate bias influences the areal charge density in graphene. Taking into account the quantum capacitance, an expression for the gate bias dependent sheet carrier density is expressed as [181], [16]   2nG 1+ (10) nGQ = nG + nQ 1 − nQ where nG = Cox VG /q is the gate induced conventional sheet carrier density when the effect of quantum capacitance is neglected (VG is the gate bias) and nQ is the sheet carrier density solely due to the quantum capacitance. Finally the sheet carrier density due to intentional doping can be determined from the dopant density. In the absence of any intentional doping, the unintentionally doped charge that may be present in the graphene as well as in the oxide with image in graphene is modelled as a fixed charge [183]. The gate bias induces charge in the graphene channel through the shift in its Fermi level. Knowledge of the Fermi energy therefore offers an alternative way to evaluate the gate induced charge density using linear density of states and Fermi-Dirac statistics [181]. However, the charge density and Fermi level being interdependent, an accurate determination of the latter involves a transcendental equation and does not permit a closed form expression [183]. Nonetheless, Zebrev et al. have obtained an explicit expression for the Fermi energy, as a function of the gate voltages, considering the electrostatics of a double gate GFET [184]. Getting an analytical expression for the charge density, using such expression for the Fermi energy will be algebraically too cumbersome. A better alternative will be to generate a computer code for simultaneous determination of the Fermi energy and carrier density. As mentioned earlier, the carrier velocity can be modelled following two approaches: (i) ballistic transport and (ii) diffusive transport. The transport can well be a combination of the two. For diffusive transport the electric field dependent carrier velocity in the graphene channel can be written as [185], [186] μE(x) (11) v (x) =   m 1/m 1 + μvEsat(x) where μ is the low-field mobility and vsat the saturation velocity, of carriers in graphene. E (x) is the electric field at VOLUME 2, NO. 5, SEPTEMBER 2014

FIGURE 7. (a) Transfer characteristics and (b) output characteristics of the GFET obtained from the model (solid lines) at [192] compared with experimental data (symbols). Figure reproduced from [192].

any point x in the graphene channel and m is a fitting parameter. While the Monte-Carlo simulated data of Chauhan and Guo [185] have the best fit to this equation for m = 1, the experimentally observed data of Dorgan et al. [186] find the best match for m = 2. The latter also unveils other valuable information like the temperature and carrier density dependence of low field mobility and scattering limited saturation velocity, which can very well be incorporated to enrich the scope of simulation programs. To be particular, the saturation velocity at high carrier density simplifies to [186] vsat =

2 ωop √ π πρs

(12)

where ωop is the optical phonon energy. This completes a simplified modelling approach which can then be integrated, with a change of variable from x to V, to get the drain current IDS . Quite a number of authors [187]–[193] have followed this approach, with some variations, and have obtained good 91

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agreement of their models with experimental data. The output and transfer characteristics, taken from [192] are reproduced in Fig. 7. This figure, while validating the model at [192] elucidates the typical characteristics of GFET. The transfer characteristics depicted in part (a) of the figure are marked by some minima (or maxima), referred to as the Dirac points. These are typical characteristics of graphene due to its ambipolar nature. A continuous shift of the Dirac point with rise in drain to source voltage is also a distinctive characteristic of graphene. The curves to the left of the respective Dirac points are dominated by holes while those to the right are dominated by electrons with a continuous change of carrier type across the curve. The output characteristics depicted in part (b) of the figure have three distinctive features. First of all the curves have linear regions for low (absolute value) drain to source voltage (VDS ) having a tendency of very weak saturation with rise in the magnitude of VDS . Secondly the curves show kinks with possibility of multiple linear regions for higher gate biases (VGS ). Finally, the curves with higher VGS tend to cross each other with the risk of zero or negative transconductance (gm = ∂IDS /∂VGS ). The last feature, while detrimental to analog RF application, opens up new ways with opportunity for novel functionality in nanoelectronics. Apart from the intuitive first principle approach discussed above three more simulation and modelling approaches on graphene FET are seen in published literature. They may be referred to as (i) the virtual source (VS) approach, (ii) the flux theory (FT) approach and finally (iii) the Green’s function (GF) approach. The VS approach [194], [195] comprises of a semi-empirical model particularly suited for shortchannel GFET. This model takes into account the ambipolar transport characteristic of graphene in an explicit way. It considers three regimes of operation. Depending on the channel voltage distribution, the carriers in the channel may be purely electrons (for positive voltage throughout), purely holes (for negative voltage throughout) or a mixture of the two (when the voltage distribution is partly positive and partly negative in the channel). Accordingly two virtual sources of charge, one for electron at the source end (Qse ) and the other one for holes at the drain end (Qsh ), of the channel, are proposed along with their virtual source velocities, ve and vh , which in turn are determinable from the ballistic velocities. Finally a saturation factor Fs is proposed to maintain continuity of the drain current in the three different regimes of operation. The model shows excellent agreement with experimental data, both in the saturation and non-saturation region of the I∼V characteristics. For more insight into the GFET operation, let us analyze Fig. 8 reproduced from [195]. A close match between the dots (experiment) and the lines (model) confirms the validity of the VS model at [195]. In addition, the model is able to explain the kink generated in the IDS -VDS characteristics of the GFET. As an example consider curve D in part (a) of the figure for which the back gate bias VBGS = 0 V and the top gate bias VTGS = 2 V. For low drain to source (VDS ) voltage 92

FIGURE 8. (a) Output characteristics (curves A-D) obtained from the model (solid lines) at [195] compared with experimental data (dots). (b) Variation of charge neutrality level and carrier quasi-Fermi levels for a typical point of operation in the ambipolar region (region II), Ln and Lp are lengths and Vn and Vp are potential drops of the n-type and p-type sections of the channel respectively, typical variation of carrier density along the channel is also depicted through the conical band diagrams. Figure reproduced from [195].

the channel is n-type throughout. As VDS increases to about 0.8 V the device operation starts to transit from region I (purely n-type channel) to region II (mixed n and p-type channel). The p-type channel starts developing at the drain end. From VDS = 0.8 V to about 1.2 V, the device operates in the ambipolar region (region II) and the charge neutrality point (also called recombination point and Dirac point) continuously shifts from the drain end towards the source. Consequently the n-type channel region continuously shrinks and the p-type channel region expands. Since the voltage drop across the channel increases from zero at the source end to VDS at the drain end, the n-channel section voltage drop (Vn ) remains relatively constant and the p-channel section voltage (Vp ) proportionately increases with VDS . Hence in the early stage of operation in region II, when the VDS is still relatively low, the charge neutrality point is close to the drain and the electron section of the channel dominates the conduction in the channel. The current, therefore tends to remain constant due to the relatively constant Vn . This accounts for the kink in the IDS -VDS characteristics with a tendency of saturation. But as VDS increases the Dirac point moves towards the source and the hole section of the channel VOLUME 2, NO. 5, SEPTEMBER 2014

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starts dominating causing the current to rise with VDS again. At VDS = 1.2 V, the recombination point reaches the source and the channel becomes fully p-type and the device operation is shifted to region III. The current rises proportionately with VDS in region III until there is another saturation region at much higher drain bias. The model can thus address the issue of multiple saturation regions and kink in the IDS -VDS characteristics. The purely linear IDS -VDS curves [such as curves A and B in Fig. 8(a)] have also been explained by the model at [195]. In the discussion above we have seen that a GFET, initially in region I (purely n-type channel) gradually shifts to region II (ambipolar region) and finally enters into region III when VDS is continuously increased from 0 to positive. But if the GFET is initially in region III, it will never enter the ambipolar region purely by increasing positive VDS . This is because, in a purely p-type channel, the charge neutrality points, at zero drain bias, are above the hole quasi Fermi level for every point in the channel [relative positions of charge neutrality level and carrier quasi Fermi level are shown for typical general situation in Fig. 8(b)]. As VDS increases the charge neutrality points on the drain side channel is raised with little effect on the source side charge neutrality level. This has the effect that the hole quasi Fermi level throughout the channel always remains below the charge neutrality level resulting in p-type channel and no ambipolar operation for positive VDS . In such situation the IDS -VDS curve registers no kink and the curve is linear throughout. Curves A or B in Fig. 8(a) with top gate voltage −1 V and 0 V respectively have p-type channel to start with. These curves, therefore, never enters the ambipolar region and are therefore linear. The FT approach relies on McKelvey’s flux theory for drain current modelling [196], [197]. The model is based on ballistic transport. Flux is defined as the number of carriers passing through the channel per unit width per second. Using this, the drain to source current is written as [149]  IDS = Wq F + (0) − F − (0) where F + (0) and F − (0) are the positive and negative going fluxes at the source end. The former is evaluated using density of states and carrier statistics. In a similar manner, the negative going flux at the drain end, Fb− (L) can also be evaluated. The negative going flux at the source end is a function of the two and is expressed as F − (0) = rF + (0) + (1 − r) Fb− (L) where r is the back-scattering coefficient. From the knowledge of F + (0) and Fb− (L), the drain current can be evaluated. Using this technique, Hu et al. [197] have obtained good agreement of their results with experimental and other simulation results. The GF formalism is an excellent tool for first principle approach modelling of current voltage characteristics in nanoscale devices. It solves a tight-binding Hamiltonian selfconsistently with the Poisson’s equation to characterise the GFET [198]. Basically it is a ballistic transport simulation method within the non-equilibrium Green function formalism [199]. It is able to address many such issues which are beyond the purview of other methods. VOLUME 2, NO. 5, SEPTEMBER 2014

VII. MAGNETO-ELECTRONIC DEVICES

We shall broadly divide the magneto-electronic devices into three classes: (i) the Hall effect devices, (ii) the magnetoresistance devices and (iii) the spintronic devices. The concept of Hall effect devices is as old as the discovery of the effect itself. This is because the Hall bar (also called Hall plate) arrangement, which is used to study the Hall effect, in itself can be used to measure magnetic field when properly calibrated. Such an arrangement is also referred to as the Hall sensor (or Hall probe). Apart from serving in isolation, Hall sensors have also entered into Integrated Circuits [200], [201]. Improving the functionality of the Hall sensor has always remained a subject of active research [202]. The improvement is primarily based on an important figure of merit referred to as the resolution, which is the minimum magnetic field that the sensor can detect. An expression for the same, following [200], can be written as √ 4kB TRout (13) Bmin = wvs √ where 4kB T is the voltage noise spectral density at the device output, Rout the output resistance at zero magnetic field, w the device width and vs the saturated drift velocity of the carriers. The output resistance is estimated using the drift model of conduction as l 1 × (14) Rout = nqμ wt where n is the carrier volume density, q the magnitude of electronic charge, μ the carrier mobility, l the length and t the thickness of the device. The first term in Rout involves material properties and the second geometrical parameters of the device. Considering a typical geometry of l/w = 1 and replacing the carrier volume density with surface density ρs = nt one gets Rout = (ρs qμ)−1 . This leads to the conclusion that materials with high mobility, high carrier density and high saturation velocity are better choices for Hall devices. Graphene seems to fulfil these requirements. A high Hall mobility of 15 m2 V −1 s−1 at 300 K [104] is potentially attractive, but this is at the cost of reducing the sheet carrier density to the intrinsic value, 8.5 × 1014 m−2 . Therefore, unfortunately, there is a trade off between the sheet carrier density and mobility, which entails a critical adjustment for an optimised resolution. The first ever attempt to fabricate a graphene Hall probe is due to Tang et al. [203]. They used CVD graphene for the purpose. The work was however, not motivated by the mobility or saturated velocity. They considered the proximity effect because the Hall probe they were designing was meant for scanning probe microscopy, where proximity of the sensor to the surface structure is of concern. Although this is not true for a general sensor the ability to place the Hall element in the closest proximity of the source is an added advantage for better resolution. In semiconductor based Hall sensors, the Hall element is normally several tens of nanometres away from the source. This makes the magnetic flux reaching 93

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the Hall element relatively weak. Graphene, being only one atom thick, can be positioned within sub-nanometres range. Thus, in principle, graphene offers a distinct advantage over other materials for Hall element. Nonetheless, graphene technology being in the maturing stage, external and internal defects limited √ by Tang et al. to √ the resolution measured only 9 μT/ Hz at 77 K and 43 μT/ Hz√at room temperaHall ture [203] as against the values of 0.5 nT/ Hz for InSb √ √ probe, 2 nT/ Hz for GaAs Hall device, and 30 nT/ Hz for Si Hall device [202]. Panchal et al. [204] have used epitaxial graphene to fabricate Hall sensors of various sizes ranging from 0.5 μm to 20 μm. They used a size dependent Hall mobility, μ = (t/ρ)×RH , where t is the thickness, ρ the resistivity and RH the Hall coefficient. Relating to the resistance of the sample, R = (ρ/t) × (L/W), where (L/W) is length/width of the sample defined as the number of squares, one can express the mobility as μ = (RH /R) × no.of squares. Using this, they have shown that the resolution of small sized sensors below 2 μm, drastically decreases because of the reduction in mobility with decrease in size . For 10 μm size Hall sensor √ they obtained a room temperature resolution of 2.5 μT/ Hz. Although this resolution is an order of magnitude improvement over the CVD graphene based sensor, it is far above the expectation from graphene. In an attempt to improve the same, Xu et al. [205] batch fabricated graphene Hall elements and observed “high sensitivity, excellent linearity and remarkable thermal stability.” The major thermal instability occurs due to change in carrier density with temperature. While intrinsic semiconductors have an exponential carrier density dependence with temperature, intrinsic graphene has a square law dependence. Therefore, graphene enjoys a better thermal stability. The Hall voltage and Hall mobility measured by Xu et al. are testimony to this fact over a wide range of temperature from 1.8 K to 400 K. The field resolutions observed√by them have exceeded all previous records with 800 √ nT/ Hz at an operating frequency of 3 kHz and 50 nT/ Hz at 4.5 MHz. It is believed that graphene Hall elements, with proper optimisation, will be able to detect magnetic field on the order of picotesla [205]. The Giant Magnetoresistance (GMR) and Tunnelling Magnetoresistance (TMR) have ruled the computer hard disk industry for over a decade now. The magnetoresistance properties discussed in Section II are found to be widely divergent. Thus a straightforward inclusion of graphene in the hard disk technology does not seem viable. Nevertheless, a modified structure of the MR device, referred to as the van der Pauw geometry (Fig. 9) has drawn the attention of researchers [206], [207]. Graphene, in the new geometry, has exhibited an extraordinary magnetoresistance (EMR) of 55000% (with potential of 500000%) at a field of 9 T [206], [207]. Although GMR and TMR are manifestations of the spin degree of freedom, spintronics in the conventional term refers to injection, transportation, manipulation and detection of spin polarised electrons and importantly the signals 94

FIGURE 9. Structure to obtain extraordinary magnetoresistance (EMR) using a van der Pauw geometry. (a) Schematic of the structure consisting of a circular metal film of radius ra with a concentric graphene film of radius rb having four electrodes (attached to the graphene film), two for current input and two for measuring voltage; the entire structure is deposited over a substrate with a back gate to apply gate voltage VG . Magnetic field is applied perpendicular to the plane of the film. (b) SEM (scanning electron microscope) image (false color) of the EMR device fabricated by Lu et al. [207] (figure reproduced with permission from American Chemical c 2011). Society publications: Nano Letters, vol. 11, pp. 2973–2977, 

embedded in it. Despite countless efforts going into making spintronics a parallel to electronics, a concrete platform is still not at hand. The emergence of graphene at this juncture has aroused a lot of expectations owing to the inspiring properties like low intrinsic spin-orbit interaction as well as very low hyperfine nuclear-spin interaction [208]. Some initial studies on spin transport in graphene exploited its non-magnetic nature and sandwiched in between two ferromagnetic electrodes. The structure has been referred to as the spin valve device [Fig. 10(a)]. Both Conduction in Plane (CIP) [209] and Conduction Perpendicular to Plane [210] geometries have shown evidences of successful spin transport [Fig. 10(b)]. In addition, spin transport together with spin precession over micrometre length in single layer graphene up to room temperature without significant loss in spin signal is potentially encouraging [208]. Furthermore, spin diffusion length exceeding 100 μm [211] and successful spin transport over a length of 20 μm [212] may be considered as important landmarks in the timeline of intrinsic graphene. What’s more, the spin relaxation length and time for intrinsic graphene have reached values 4.7 μm and 200 ps respectively [121], [213]. These figures, in themselves are sufficient for intrinsic graphene to claim a platform VOLUME 2, NO. 5, SEPTEMBER 2014

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FIGURE 10. Spin valve device. (a) Schematics of a conduction perpendicular to plane (CPP) spin valve device. (b) current paths in conduction in plane (CIP) and CPP spin valve devices. Figure reproduced from [210].

in spintronics. Nonetheless, they have been superseded by hydrogenated graphene with overwhelming values of 7 μm and 2.7 ns [214]. These values, when compared to Si at a low doping (1014 cm−3 ) and room temperature (5 μm and 10 ns) [215] establish a firm footing for graphene on spintronics. The theoretical investigation of Zeng et al. [216] and the practical realisation also by Zeng et al. and others [10] are only the beginning of the exploration for a myriad of spin devices. The full potential of graphene is not yet harnessed. VIII. OPTOELECTRONIC DEVICES

The exotic optical and optoelectronic properties of graphene discussed in Section II are reminiscent of incorporating graphene into the realm of optoelectronic devices. Basically we have four classes of such devices: photodetectors, light emitting diodes, solar cells, and laser diodes. We discuss them in four subsections below. A. PHOTODETECTORS

A photodetector is a device that detects light (possibly embedded with signal) by converting photon energy into electrical current. The conventional semiconductor photodetectors suffer from the “long wavelength limit”; photons of energy less than the bandgap are not absorbed by the semiconductor. Therefore, the photocurrents of most of the semiconductor photodetectors drop off, when the photon energy of incident light approaches the material bandgap. This in turn limits the spectral range over which the VOLUME 2, NO. 5, SEPTEMBER 2014

photodetector can efficiently respond. It turns out that semiconductors of different bandgaps are essential for different wavelength ranges. The optical fiber communication can be taken as the best example. The three windows of optical fiber need many different semiconductors for photodetectors such as Si, GaAs and InP for the first window (800 nm – 950 nm), Gax In1−x Asy P1−y for the second window (1280 nm – 1350 nm), and Gax In1−x As for the third window (1535 nm – 1560 nm). It may be interesting to note that a single material, graphene can serve the purpose of the five semiconductors stated above because of its ability to absorb light from terahertz to ultraviolet range of frequency [217]. In addition, graphene being a zero bandgap material the possibility of a photocurrent drop off is remote. The other features of graphene which will be most suited for a photodetector include its high carrier mobility, low dark current, good internal quantum efficiency, and a small device footprint. The high carrier mobility of graphene enables ultrafast extraction of photo generated carriers, allowing high bandwidth operation which makes it possible the realization of broadband photodetectors [218]. Despite these favourable properties, graphene has some drawbacks, like the short carrier lifetime and the low responsivity, which need to be addressed to make it more suitable for an ultrafast photodetector. While the zero bandgap of graphene is considered as a boon for broadband detection, it is also a weakness for which the electron and hole pairs recombine very quickly, resulting in no free electrons to carry current. Due to the short recombination life time of the photo generated carriers, the internal quantum efficiency becomes low. In order to improve upon this, some researchers employed a scheme whereby they placed some metal fingers-like electrodes, made of palladium or titanium, over the graphene sheet [219]. These metal fingers, having different work functions, produce an electric field at the interference between electrodes and graphene which in turn separates the electrons and holes resulting in a photocurrent. In a more recent work Liu and Zhang [220] produced an asymmetrical electrical potential by placing a pair of asymmetrical electrodes parallel to the waveguide at distances of 100 nm and 3.5 μm which not only helps to separate photo carriers generated around the silicon waveguide but also reduces the recombination. As stated earlier, the photo responsivity of graphene is low, with typical value less than 10 mAW−1 [221] in comparison to the prevalent value of 1 AW−1 [166]. This is due to the small effective detection area and weak absorption resulting from the atomically thin nature. To improve upon this, microcavities [222], nanocavities [223], and plasmonic resonators [224] are integrated with graphene. Liu et al. [224] have demonstrated that metallic plasmonic nanostructures can be integrated with graphene photodetectors to improve the photocurrent and external quantum efficiency by up to 1,500%. The photo responsivity of graphene is amplified by the plasmonic nanostructures of variable resonance frequency permitting multi-colour detection. All these benefits are however, at the cost of reduced spectral bandwidth. 95

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Integration of quantum dots with graphene can also considerably increase the responsivity, but the process is too expensive [225]. Although these researchers have adopted different methods to augment the responsivity, the values obtained are still not encouraging. Wang et al. [226] reported the use of silicon waveguide in graphene photodetector which have low losses over an ultra wide bandwidth. Photons propagating in the silicon waveguide aligned parallel with a graphene sheet interact with the graphene layer along the entire length of the waveguide, significantly enhancing light– graphene interactions without reducing the bandwidth or speed, or increasing the device footprint [226]. They reported an impressive responsivity as high as 0.13 AW−1 at a bias of 1.5 V for light of wavelength 2.75 μm at room temperature. Gan et al. [227] also obtained a notable responsivity of 0.1 AW−1 for a 53-μm-long waveguide. They observed a nearly flat photocurrent response in spectrally resolved photo detection measurement with zero bias in the wavelength range of 1450–1590 nm for a fixed optical input power, which may be principally attributed to the spectrally flat absorption of graphene. Zhang et al. [228] reported a very remarkable photo responsivity of 8.61 AW−1 in pure monolayer graphene photodetectors, about three orders of magnitude higher than those reported in literature. In this study, they created a bandgap in graphene through band structure engineering by introducing electron trapping centers. They experimentally demonstrated the broadest photo response with high responsivity from the visible to infrared region. As an added benefit, graphene technology is compatible with CMOS. Taking advantage of the same, Pospischil et al. [229] have integrated optics and electronics into the same chip by demonstrating an ultra-wideband CMOS compatible graphene photodetector. The responsivity they obtained is not so high (0.05 AW−1 ) but the concept they used will open up a new area called carbon based optical interconnects. It is thus clear that researchers have been constantly addressing the issues of short carrier lifetime and weak absorption of graphene. The development over a period of 5-6 years is remarkable. But these are only prototype data. The ultimate test will depend on long-term reliability and minimization of variability. B. LIGHT EMITTING DIODES

Light Emitting Diodes (LED) are principally deployed in three major areas such as (i) communication, (ii) display, and (iii) lighting. Depending on the type of application many different semiconductors are used to fabricate LED. Because of the increasing cost of energy and the global energy crisis, a viable alternative to energy efficient home lighting has become a thrust area in optoelectronic research. In this context white light LED has emerged as the right device. Presently LED light bulbs have become more expensive because of the high cost semiconductor substrates. With a view to reduce the cost, organic light emitting diodes (OLED) have attracted a great deal of attention from the 96

research and development sectors [230] because of their high luminous efficiency and compatibility with a wide variety of substrates. The key feature of OLED is the transparent conductive electrodes which inject charge carriers and allow light to pass through. Indium tin oxide (ITO) is presently chosen for this because of its low sheet resistance of 10 /sq at 90% transmittance and simple deposition process by sputtering [231]. However it has many disadvantages such as (i) its increasing cost day by day [232], (ii) difficulty in fabrication steps and poor mechanical flexibility [233], (iii) poor electrical contact with organic materials which lead to limit the performance over time [234], and (iv) development of strain induced fracture, which is a serious obstacle for developing flexible OLEDs [235]. In addition, limitation of Indium on the Earth is a matter of concern. Therefore researchers felt that there is a significant need for a novel electrode material whose optical and electrical performance is similar to that of ITO, but without any drawbacks, which can possibly be used as an alternative to replace ITO in LED devices. Out of several alternatives such as Carbon Nano Tube (CNT) [236] and silver film, graphene is ahead in the race because of its specific properties particularly suitable for a transparent electrode. The key features are 90% optical transmittance, great mechanical flexibility, possibility of low manufacturing cost based on roll-to-roll technique and ample availability of raw materials [91], [237]. The bending stability of graphene vis-à-vis ITO is studied by Lee and Ahn [238]. Their result indicates that the graphene-anode based OLED device demonstrates outstanding bending stability, while the ITO-based OLED device broke at 800 cycles. Jo et al. [239] studied the light output power and input current characteristics of LEDs fabricated with graphene and ITO electrodes. The results they obtained led to the conclusion that the output power of graphene electrode based OLED was about 63% that of ITO electrode based OLEDs at an input current of 20 mA. This is due to the high sheet resistance of graphene (35 /sq) compared to ITO which causes a larger voltage drop in the graphene electrode. Therefore several methods have been attempted to enhance the device performance of graphene based LEDs by increasing the conductivity and tuning the work function [23], [240]. Ju et al. demonstrated a solution in which the performance of graphene can be made comparable to control devices on ITO. In this work they reduced the sheet resistance of graphene on OLEDs with solution-processed graphene thin film transparent conductive anodes [23]. In another step, Han et al., to overcome these drawbacks, fabricated flexible OLEDs by modifying the surface with conducting polymers to achieve a high WF (work function) and low sheet resistance. This helped them to attain higher luminous efficiencies compared to those of OLEDs with ITO anodes [240]. C. SOLAR CELLS

Presently the solar cell industry is dominated by Si due to its high power conversion efficiency (PCE) and better VOLUME 2, NO. 5, SEPTEMBER 2014

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reliability. But at the same time the cost of Si solar cell is high. For a compromise between the cost and efficiency poly-silicon and some organic materials are also used to fabricate low cost (but relatively less efficient) solar cells. With the advent of graphene, researchers believe that it will be able to address both of the issues: cost and efficiency. We have already hinted in Section II that the broad spectrum absorption of graphene will be potentially valuable for the purpose. But its other qualities are also harnessed by researchers to build a high efficiency low cost solar cell. An initial study [241] exploits the transparent, conducting and atomically thin nature of graphene to replace the metal oxide window electrode of a dye sensitized solar cell (DSSC). Although the graphene film they used showed a high conductivity of 550 S/cm and a transparency of 70%, the power conversion efficiency (PCE) they obtained was only 0.26%, which was much smaller than the current state-of-the-art value, 15% [242]. The effort however did not stop. Sun et al. [243] used a graphene-TiO2 composite photoanode for their DSSC. Using the composite of 0.5% by weight of graphene, they obtained a PCE of 4.28% which was 59% more than that obtained without graphene. It is understood to be due to the graphene helping in increased dye adsorption and augmented electron life time. Miao et al. [244] used a graphene/n-Si Schottky junction for their solar cell. By doping the graphene with bis(trifluoromethane-sulfonyl)amide (TFSA) they obtained an encouraging PCE of 8.6%. The result is intuitively explained by the dopant assisted Fermi level shift of graphene resulting in enhanced carrier density. It turns out that the cell resistance decreases and the open circuit voltage increases with consequent enhancement in the fill factor. The solar cell community has an added interest in replacing the transparent window electrode from the presently used Indium Tin Oxide (ITO) to graphene. The motivation behind such interest is the same as discussed in the case of LED. Koh et al. [245] have thoroughly examined ITO vis-à-vis graphene for the window electrode of a solar cell. They observed that the resistance of single layer CVD graphene is four times that of ITO of same area. This is immediately suggestive of using four layers of graphene to reduce the resistance to that of ITO. But then four layers of graphene will block more light. It is believed that, with improvement in processing technology, the graphene resistance will decrease which will enable one or two layer of graphene to outperform ITO. In continuation to the pursuit of higher PCE, Wang et al. [242] introduced nanocomposites of graphene and TiO2 as the electron collection layer in their thin film perovskite solar cells. They obtained PCE as high as 15.6% which was the highest obtained from graphene based solar cell till date. Although this value is much less than that from a Si solar cell (typically 25%) or a multijunction solar cell (typically 35%) [246], the progress with PCE of graphene based solar cell over the years (2008 to 2014) is encouraging. It has roughly doubled every two years. We believe that the target value will be achieved in a couple of years. VOLUME 2, NO. 5, SEPTEMBER 2014

D. LASERS

As far as laser in concerned, the non-linear property of graphene, referred to as saturable absorption in Section II, is widely exploited to generate ultrafast laser pulses based on mode locking. Here we can find the conversion of the continuous wave output of the laser into a train of ultra short light pulses. Whereas other semiconductor based saturable absorbers require complex fabrication procedures to provide only a very narrow tuning range [247], [248] graphene proved itself as an excellent saturable absorber over a wide spectrum range and notably it does not require any complex fabrication process [249], [250]. Researchers have demonstrated ultrafast tunable fiber laser mode locked by a graphene based saturable absorber [251] with stable mode locking and generating near transform-limited 1 ps pulses. Along with saturable absorption, the wideband operation capability of graphene is also demonstrated [252]–[254]. The obtained results present a conceptual change in graphene laser, making mode locked laser more suitable for various applications. An erbium doped fiber laser, self started mode locking and stable solition pulse emission with high energy have been achieved [255]. There are also other benefits of graphene saturable absorbers such as ultrafast carrier relaxation time, controllable modulation depth, and wide spectral range tunability [254]. In 2012 a team of researchers extended the work to include mode locking Thulium-doped fiber laser using a graphenepolymer composite saturable absorber operating at 1.94 μm wavelength, generating laser pulses of 3.6 ps at 6.46 MHz with ∼0.4 nJ pulse energy [256]. This laser, because of its simplicity, convenience, low cost and low energy output, is expected to find applications in areas like sensing and biomedical diagnostics. More recently Limmer et al. [257] have observed that graphene when used in telecommunications could dramatically accelerate internet speeds by up to hundred times. In this paper they discussed about optical switches using a few layer graphene. They have shown that the response rate of an optical switch, using a few layers of graphene could be around one hundred femto-seconds. This figure is 100 times faster than the ordinary optical switches which respond at rates of a few pico-seconds [257]. IX. SUMMARY AND CONCLUSION

If we revisit the properties of graphene we shall gather that only a few of its exotic properties are harnessed for electron devices. It is observed that graphene based electronic device research is concentrated to the two major devices such as the analog RF FET and the digital logic FET. The high mobility has been the main attraction for graphene’s incorporation into the RF FET. But the mobility is substantially low in a practical device. Suspended and hBN encapsulated graphenes have come to the rescue. The absence of bandgap in graphene (monolayer) has been the main concern for digital logic devices. Several efforts to induce a workable bandgap have not yielded any industry standard breakthrough. On the other hand they have resulted in reducing the mobility. Therefore, 97

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TABLE 2. First reports on some graphene based electron devices

a lot of research is still necessary to break the trade off between bandgap and mobility. The ambipolar nature of graphene is reasonably harnessed for electronic devices. But very few reports are available on devices utilizing the Klein tunnelling. The Klein tunnelling is a property specific to graphene. And therefore, while considering graphene for electron devices, this property should be exploited with due importance. In the magneto-electronic properties, only the 3D linear Hall Effect is put to use for Hall bar devices. The observed magneto-resistance of graphene is contrary to expectation and yet researchers have tried various ways to give it a shape such that it can find a place in the computer hard-disk technology. But they have not reached the present standard as yet. The field of optoelectronics is benefitted the most out of graphene. The special properties like broad band and saturable absorption are fully exploited to enrich the arena of all the optoelectronic devices. In addition the community believes that the transparent conductor ITO will very soon be replaced by graphene. In this context a most recent report at [258] is encouraging; here the authors report “mass-produced graphene films synthesized by hydrogenfree rapid thermal chemical vapor deposition (RT-CVD), roll-to-roll etching, and transfer methods, which enabled faster and larger production of homogeneous graphene films over 400×300 mm2 area with a sheet resistance of 249 ± 17 /sq without additional doping.” What’s more, they have also demonstrated the installation of the fabricated graphene sheet in capacitive multi-touch screen of the sophisticated mobile phone with performance level better than ITO. A comprehensive review of graphene based electron devices is presented. Graphene has been incorporated into almost all the common devices successfully. Table 2 gives 98

an account of the first reports on graphene based electron and optoelectronic devices. Apart from the classified devices discussed in different sections, some sporadic reports on graphene based other devices are also seen in the literature. They include Vertical Tunnelling FET [259], Single Electron Transistors (SETs) [260], Tunnelling Transit Time Devices [261] and Quantum Dot Devices [11]; a partial list of such devices is also available in the first paragraph of the Introduction section. All these have brought graphene to the fore front of device research. But developing a viable prototype exhibiting the expected properties, to a great extent depends on the improvement in graphene processing technology. No doubt the technology is advancing day by day. But the present status is much behind the most advanced Si technology. Although we understand that one day Si has also gone through the same stage that graphene is passing now, it is difficult to believe that graphene will be a complete substitute to Si in the near future. It will be rather judicious to take advantage of the Si technology with a role for graphene to augment the device performance. Undoubtedly, graphene being only one atom thick will always need a base (substrate) for support. The present practice with SiO2 upon Si as the base for graphene seems to go a long way. Some people in the community believe that Si technology has at least 40 years to go without any serious problem. Therefore, it will be more intelligent to pull along the Si technology to exploit the myriad of exceptional properties that graphene possesses. ACKNOWLEDGMENTS

S. Behera would like to thank the DST, Government of India for the INSPIRE fellowship to carry out this work. VOLUME 2, NO. 5, SEPTEMBER 2014

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G. N. DASH was born in 1955. He received the M.Sc., M.Phil., and Ph.D. degrees in 1977, 1983, and 1992, respectively. He joined G.M. College, Sambalpur, India, under the Government of Odisha as a Lecturer in physics in 1978 and subsequently he moved to the School of Physics, Sambalpur University, Sambalpur, India, in the same post. There he became a Reader in 1993 and since 2001, he is working as a Professor. He has published over 170 papers in journals of repute and proceedings national and international conferences. He has guided 35 scholars for the award of M.Phil. degrees and seven for the award of Ph.D. degrees in physics and engineering. Some ten more scholars are pursuing Ph.D. degrees under his guidance. He is a fellow of the IET (U.K.) and a Life Fellow of the IETE (India). He is also a Distinguished Lecturer of the IEEE Electron Devices Society. His research interests include 2T microwave devices, HEMT, graphene based devices, and new emerging materials.

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SATYA R. PATTANAIK was born in 1977 at Sambalpur, India. He received the M.Sc. degree in electronics and the Ph.D. degree from Sambalpur University, Sambalpur, India, in 1999 and 2010, respectively. He received the M.Tech. degree in computer science from Utkal University, Bhuvaneswar, India, in 2008. He is now working as an Associate Professor at the Apex Institute of Technology and Management, Bhubaneswar, India. His research interests include microwave power devices and antenna. Two scholars are working under him for Ph.D. degree. He has published 40 research papers in various journals of international repute and proceedings of national and international seminar/workshop. He is a Life Member of ISTE and Odisha Physical Society.

SRIYANKA BEHERA was born on May 20, 1989. She received the M.Sc. degree in electronics from Sambalpur University, Sambalpur, India, in 2011 with University Gold Medal for securing first position in first class. She is currently pursuing the Ph.D. degree from the School of Physics as an INSPIRE Fellow at the Department of Science and Technology, Government of India.

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