Ground-Shielded Measuring Technique for ... - Semantic Scholar

246

IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, MARCH 2000, KOLDING, JENSEN, AND LARSEN

Ground-Shielded Measuring Technique for Accurate On-Wafer Characterization of RF CMOS Devices Troels Emil Kolding, Ole Kiel Jensen, and Torben Larsen RF Integrated Systems & Circuits (RISC) group, Aalborg University, Denmark. E-mail: {tek,okj,tl}@kom.auc.dk, Internet: http://www.tele.auc.dk/risc/. Abstract— This paper presents a new test fixture with associated deembedding procedure for effecient and accurate on-wafer device measurements at microwave frequencies. The fixture is based on a substrate shield and (i) provides an accurate common ground for N-port measurements, (ii) effectively reduces substrate carried coupling, (iii) gives well-defined parasitics for simplified de-embedding, and (iv) fits arbitrarily large devices. Due to these characteristics, the accompanying de-embedding technique requires only few in-fixture standards that can be fabricated with very high accuracy; even in standard CMOS processes. The technique can advantageously be applied to a wide range of commonly used processes, but highest performance improvement is achieved with low-resistivity substrates. The performance of the technique is demonstrated to 12GHz in a 0.25µm CMOS technology and conclusions are drawn.

F

I. I NTRODUCTION

OR low-cost silicon CMOS technology to become a successful RF-IC contender, accurate and reliable device models must be contrived. However, accurate modeling calls for precise on-wafer measurements that are hard to obtain due to high substrate losses and low interconnect conductance inherent to CMOS technology [1]. For one, it implies that calibration with a ceramic impedance standard substrate (ISS) is not sufficient for establishing a reference plane close to the device under test (DUT) [2]. As sufficiently precise onwafer standards are not currently available in standard CMOS technology for accurate two-port TRL calibration, various deembedding techniques are often applied in conjunction with ISS calibration [3], [4], [5]. As addressed in [6], accurate deembedding requires that the test fixture displays a few easily identified and dominating parasitics. In this paper a test fixture design is presented that effectively provides a shield for mitigating the effect of substrate parasitics. This makes the fixture particularly useful for silicon CMOS technology, but also for other integrated processes with higher substrate resistivity. By utilizing the groundshielded measuring technique, and thereby reducing substrate effects, negligible forward coupling is achieved which makes the method scalable and very cost-efficient. The fixture is generally applicable to N-port measurements and fits arbitrarily sized devices such as transistors, inductors, and capacitors. In this paper, however, only two-port measurements are considered. Based on a detailed study of fixture parasitics, a deembedding approach is proposed that eludes over-calibration due to imperfect standards. Because of this ability, one generic test-fixture can be used to predict the performance of other similar fixtures which hold arbitrarily sized devices. This is a great advantage for CMOS technology where devices often occupy a large area to compensate for low device performance per area. As shall be seen, the test fixture may be qualitatively described by very few parameters and the de-embedding approach is therefore both simple and accurate.

II. G ROUND -S HIELDED T EST F IXTURE The proposed ground-shielded test fixture is shown in Fig. 1. The fixture is configured for ground-signal-ground (GSG) probes and a cross-section of the pads in one end is shown in Fig. 1a. Foremost, the fixture consists of a grounded shield implemented in the bottom metal layer (designated by M1). By connecting the two ground pads directly to the metal ground plane, a well-established ground-reference is established. The signal pad is separated from the ground plane by leaving out one or more of the bottom metal layers (e.g. metal layers M2 and M3 in Fig. 1a). Usually, concerns related to production yield dictate that all metal layers are employed in the pad design and the process design rules must therefore be circumvented. However, note that the structure is fundamentally compatible with standard CMOS processing and that device characterization does not call for the highest yield. In fact, most foundries will produce the structure in Fig. 1 if the designer is willing to take responsibility for the structure. However, some amusing comments should be expected along the way! Another issue is that of pad height. When one or more metal layers are excluded from the signal pad design, it cannot be expected that the physical height of the signal pad matches exactly that of the two ground pads [7]. However, as CMOS measurements call for relatively high amounts of probing skate/overtravel [8], [2], the associated effects have been observed to be negligible in practice.

a

Top metal layer (e.g. M6) G S

G

Oxide Substrate Bottom metal layer (M1) Ground shield

b

Ground shield extension

Top metal layer(s)

G

Bottom metal layer

S1 Vias and metals

G

G

DUT space

Oxide

S2 G

p- substrate

Ground shield extension

Fig. 1. Ground-shielded fixture for 2-port measurements (GSG probes).


Note from Fig. 1 that the resulting structure is a hybrid between a coplanar waveguide and a microstrip. From the topview in Fig. 1b, observe further that the ground shield provides a low-impedant path between all four ground pads. Consequently, a basic and important requirement for all two-port measurements is effectively fulfilled with the structure. As both signal pads refer to the same ground plane (since the highconductivity metal shield provides effective guarding against substrate effects) the coupling between the two pads is significantly reduced. In theory, the forward coupling of the shielded fixture will be limited to direct fringing which in most cases is negligible. Individual design rules may require small variations of the shown structure, but the basic idea is compatible with all standard CMOS processes. Some processes allow a limited maximum metallization width and in this case it is necessary to chop small squares in the metal shield. Fortunately, this can be done without significant loss of performance. Note that the large hole centered in the shield (the fixture gap) should be made just large enough to fit the device under test. To interface to the DUT, two signal paths (S1 and S2) are drawn in the top metal layer. Although they can be implemented in a number of ways, it appears to give best results if the height of the signal lead is consistent with the height of the two signal pads. In this way a continous transition from probe to DUT boundary is achieved. The ground shield that surrounds the fixture gap may be used to connect DUT terminals to ground; as is required for most NMOSFET measurements. Further, the substrate (bulk) can be separately biased by embedding a separate bias pin in the basic structure of Fig. 1. However, for the cases considered here, it is assumed that the ground shield is tied directly to the substrate with a large number of contacts. As partially illustrated in Fig. 1, the ground shield should surround the whole structure with an extension of approximately 20µm or more to properly terminate the fields at the edges. The ground shield extension may be designed with small alignment taps to ensure consistent overtravel and skate for best measuring results. For improved performance with processes that use lowly conductive metal for layer M1 (e.g. tungsten), a connection between opposing ground pads (S1 to S2 side) can be made using all available metal layers. Further, a tradeoff must be made when designing the signal leads which connect pads to the DUT. When using more of the top metal layers the series parasitics of the leads are reduced. As shall be evident from the proposed de-embedding procedure, the use of more metal layers in the signal path also improves the accuracy of the infixture short standard. However, simultaneously the coupling to the ground shield increases, thereby increasing the loss, and this may be of concern to certain high impedance measurements with high dynamic range requirements. In general, is is safe to apply at least a few of the metal layers. Note further that the use of more metal layers reduces the potential and undesired pad height variation between signal and ground pads. III. F EATURES OF

THE

T EST-F IXTURE

In the following, several experiments are conducted to illustrate the basic features of the ground-shielded test fixture. In order to emphasize the difference between a conventional two-

247

port test fixture and the ground-shielded test fixture, both types of fixtures have been fabricated in a 0.25µm bulk CMOS technology offering 6 metal layers. The two fixtures are shown in Figs. 2a-b. Care has been taken to ensure high consistency between the conventional and ground-shielded fixtures. Both test fixtures employ a fixture gap of 130µm95µm. With an ISS calibrated vector network analyzer (VNA), the S-parameters of the two open fixtures have been measured from 45MHz to 12GHz. The forward coupling is plotted in Fig. 2c. Note that the introduction of the ground-shield gives a coupling reduction at 12GHz of approximately 28dB. Usually, test fixture forward coupling is considered negligible if it resides approximately 20dB lower than the intrinsic feedback coupling of the DUT [9]. Given the performance of the ground-shielded test fixture depicted in Fig. 2c, this is largely fulfilled for practical RF CMOS devices. Hence, the ground-shielded test fixture solves the problem of forward coupling and its correction. This has been a widely disputed subject in recent literature [10]. Even better improvement has been observed for epitaxial processes and a forward coupling lower than approximately -50dB is possible with most CMOS processes up to 12-18GHz. In order to estimate and quantify the major parasitics of the ground-shielded test fixture, a number of de-embedding standards have been fabricated. These in-fixture standards are shown in Fig. 2b and includes open, short, simple open, and simple short standards. The fabricated standards facilitate the use of 4-step de-embedding (4SD) which has proven to be a very robust and accurate method when applied to RF CMOS measurements [11], [2]. The eqvivalent parasitics representation used by the 4SD method is depicted in Fig. 3a. The extracted parasitics of the fabricated test fixture are plotted in Fig. 3b. Compared to the conventional test fixture several important differences apply: 1. The test fixture forward coupling (denoted by Z f ) is reduced to a negligible level. The absolute value of the admittance corresponds to less than 90aF. This is negligible for most practical measurements as argued previously from js21 j. 2. The fixture input and output parallel parasitics are almost purely capacitive with only negligible resistive effect. This applies to both impedances Z p and Zd as shown in Fig. 3b. This greatly simplifies de-embedding and makes the test fixture very attractive for noise measurements. 3. The dangling leg impedance Zs is negligible. This is a very important feature of the fixture as it greatly simplifies the deembedding procedure. For conventional test fixtures, the consideration of dangling leg parasitics is usually very important; e.g. for common-source FET measurements. Note from Fig. 3 that contact and input lead resistances, ℜfZc g and ℜfZi g, display a slight frequency dependence. The contact reactance further displays a negative linear behaviour indicating a negative inductance of the probe-pad transition. This is not a physical property of the structure but merely indicates that load and short inductances have not been properly accounted for during the ISS calibration. As the first step of the 4SD de-embedding method takes this imperfection into account, the extracted values for the remaining parasitics can be assumed to be physically correct.

248


M6-M1+n-well 85m m pads

a G

G M6-M5 leads 130m m X 95m m

S

S grounded p+ ring

G

G Conventional fixture

M6-M1

b G

G M1

S

130m m X 95m m

S M6-M5

G

M6-M4 85m m pads

G

Open ground-shielded fixture G

Grounded p+ area

S

G S

G

G

S

S

Via stack

G

G

Simple short/open standards

|s21 | [dB]

c

0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110

G

G Short standard

Conventional fixture (bulk CMOS) Shielded fixture (bulk CMOS)

0

2

4 6 8 Frequency [GHz]

10

12

Fig. 2. Illustration of (a) conventional fixture, (b) shielded fixture including de-embedding standards, and (c) illustration of forward coupling reduction achieved by shielding.

One of the major advantages of the ground-shielded test fixture is the dominance of a few well-defined parasitics. Having established a proper common ground, the main parasitic effect originates from the coupling between signal path and ground shield. As seen, this coupling behaves like a high-Q capacitor which enables a very simple representation. Other important parasitics are due to contact effects and series parasitics of the input leads to the DUT. Based on the extracted values a possible representation of the fixture parasitics can be derived. Such an equivalent model is shown in Fig. 4 and is basically a simplification of the 4SD model depicted in Fig. 3a. The eqvivalent model in Fig. 4 includes general impedances which may be converted into lumped circuit elements if desired. This impedance-based model is chosen over a general two-port model to represent the major parasitics. Although potentially more accurate, the two-port representation requires more in-fixture standards in order to determine all parameters. As shall be seen, only very few accurate standards are available in CMOS technology and, hence, the impedancebased approach gives the best overall result. The impedance Zc denotes the additional contact impedance which is present when moving the probes from the ISS to the CMOS chip. As CMOS technology is most often based on aluminum metallization this impedance may be quite significant at gigahertz frequencies [2]. The impedance Z p denotes the pad-shield coupling that originates from the area of the pads and the direct airborne coupling between signal and ground pads. In most cases it is safe to assume that the pads are alike, but separate de-embedding is possible by introducing an additional standard. Impedances Z1 and Z2 denote the series losses of the signal leads between pads and DUT interface. Although the test fixture is most often symmetrical, the two parasitics are not assumed equal leading to high generality. Additional coupling between input/output leads and the ground-shield is denoted by impedances Z3 and Z4 . Compared to letting Z p denote all parallel parasitics, increased accuracy is obtained using this distributed configuration. Parameter Z f denotes the direct coupling between input and output ports of the fixture. As indicated previously, its effect is mainly due to the direct fringing between input and output leads since the substrate carried coupling has been effectively reduced by the grounded shield. As direct fringing is the major cause of the forward coupling of the ground-shielded fixture, it is relevant to investigate how the fixture gap length affects this coupling. A ground-shielded test fixture similar to the one in Fig. 2b has been implemented in a 0.5µm epitaxial process. Several variants have been fabricated with different fixture gap lengths. The measured coupling for these structures at various frequencies is listed in Table I. Note that even for a very short fixture gap, the coupling remains relatively unchanged. Since the coupling does not change significantly with fixture gap size, this indicates that the test fixture and associated method can be considered completely scalable. This is a vital point for on-wafer measurements. It basically means that two differently sized test fixtures as examplified in Figs. 5a-b display identical parasitics provided that high design consistency has been used when laying out the input leads. The ultimate impact of this feature is that only one set of de-embedding


249

TABLE I

Zf

a Zc

T EST FIXTURE FORWARD COUPLING VERSUS GAP SIZE .

S1

Zd

S2

Zd

DUT

Zp

Zp Zs

G1

G2

Extracted Impedamces (real/imag) [W ]

Extracted Admittances (real/imag) [mS]

b 0.04

5.0 Â {1/Z d }

0.02

4.0

2.5

-0.01

2.0 Â {1/Z f }

-0.02

Á {1/Z d }

1.5 1.0

-0.03

0.5

Â {1/Z p } 0

0.0

5 10 Frequency [GHz]

0.30

0.8

0.25

0.6

0.20 Â {Z } i

0.2 0.0

0.10

-0.2

Â {Zc }

0.05

Á {Z s }

S

G

G

-0.6

0.00 Â {Zs } 0

Zc Zp

Z3

S

S

G

G

Large-size device measurement

-1.0 -1.2


Z1

G

Á {Z c }

-0.8

-0.05

G

-0.4

Fig. 5. Illustration of fixture scalability.

0


Zf

G

S

b

Á {Z i }

0.4

0.15


Fig. 3. Illustration of (a) general representative model for CMOS measuring fixture, and (b) parasitic values for shielded fixture extracted from measurements on in-fixture standards.

S1

G

Medium-size device measurement

Á {1/Z f } 0

Gap size 92µm 145µm -68 -70 -58 -59 -52 -52 -52 -50

G

3.0

0.00

-0.10

Á {1/Z p }

3.5

0.01

37µm -76 -57 -51 -50

standards is required to predict and de-embed parasitics of all on-wafer test-fixtures; regardless of their size! This gives a huge reduction in area and cost when producing chips with many test structures. This is very attractive and is obtained by slightly bending the process design rules.

a

4.5

0.03

-0.04

Forward Coupling js21 j@3GHz [dB] js21 j@6GHz [dB] js21 j@9GHz [dB] js21 j@12GHz [dB]

Zc

Zi

Zi

Z2 Z4

Zc

S2

Zp G

Fig. 4. Equivalent impedance model for ground-shielded test fixture.

IV. D E -E MBEDDING P ROCEDURE The de-embedding procedure which relates to the eqvivalent model of Fig. 4 is most conveniently based on two-port Z- and Y -parameters. Although Z f may safely be ignored for most measurements it is included in the following to give a complete description. As illustrated in Fig. 6a, the starting point is a set of Z-parameters, denoted Z, that is obtained from measured S-parameters. Hereafter, the de-embedding procedure follows 4 steps as illustrated in Figs. 6a-d including a number of transformations between Z- and Y -parameter domains; Y = Z 1 . The de-embedding procedure is first described assuming that all parasitics are known: Z0

=

Z

Zc 0

0 Zc

(1)

250


Y00 Z000 Ydut

=

Y0

=

Z00

=

Y000

1=Z p 0 Z1 0

0 1=Z p 0 Z2

G

(2)

(a) Short/Open

S1

(3)

1=Z3 + 1=Z f 1=Z f

1=Z f 1=Z4 + 1=Z f

G

G

S2

(4)

(b) Open

G

G

S1 G

where Ydut denotes the de-embedded Y -matrix for the DUT. The above procedure is easily implemented as a computer program and executes very fast.

Zc

S1

Z2 DUT

Z3

G

G

Z1

Zp

Zc

Z4

G S2

p- substrate

(c) Short

G

S2

Zp

G

Fig. 7. Calibration standards needed to de-embed fixture parasitics.

G Z

Z'

Zf

(b)

Z1 Zp

Z2 DUT

Z3

Z4

Zp

Y' Y'' Zf

(c) Z1

Zf

(d) Z2

Z3

Z''

G S1

Zf

(a)

G S2

Z'''

DUT

Z4

Z3

DUT

Z4

Y''' Ydut

Fig. 6. Procedure for de-embedding DUT measurements.

V. PARAMETER E XTRACTION The de-embedding procedure described previously assumes that the fixture parameters are known. To determine these parameters, process tolerances render measurements on known standards more robust than electromagnetic simulator extraction as in [12]. When selecting and designing a set of in-fixture standards it is important that the basic test fixture parasitics are not altered due to standard imperfections. To de-embed pad parasitics, it is proposed to use a combined short/open standard as shown in Fig. 7a. By applying all metal layers, including the ground shield, the short standard may be designed with negligible series resistance. The open standard is implemented as a floating signal pad, thereby enabling a separation of padground coupling. Since the open standard refers directly to the ground pads via the grounded shield, potential problems with substrate leakage are avoided [2]. Another standard which is very useful for calibration is the open standard which consists of the full test-fixture with the DUT removed. This standard is shown in Fig. 7b. In the

general case, however, yet another standard is needed. Although the thru standard is often used, it is discarded here due to the significant over-estimation of parasitics that takes place if the length of the thru line is not properly considered [6]. Fortunately, the short standard shown in Fig. 7c is very accurate. Note, that a short standard with negligible contact resistance can be implemented at the border of the DUT hole. This is achieved by placing a thin array of via to connect the ends of input and output leads to the ground-shield. Hence, impedances Z1 and Z2 only changes marginally for the in-fixture short standard compared to the original groundshielded test fixture. Further, note that the performance improves when more interconnected metal layers are used for the signal path since (i) the length and, hence, the resistance of the short standard is reduced and (ii) the original value for Z f is maintained. The latter is less important when the short connection has very low series impedance which is typically the case. Note that for most cases where (i) forward coupling can be considered negligible and (ii) the test fixture is symmetrical, it is possible to combine the short and open standards in one fixture (e.g. S1 open, S2 short). This gives a very area-efficient solution which is applicable in most practical situations. Given measurements on the presented standards in Fig. 7, it is possible to extract the test fixture parameters. The extraction procedure is based on the equivalent circuit diagrams for the standards shown in Figs. 8a-c. From the open/short standard, Z p and Zc can be directly estimated as (5) Zc = Z11;s=o (6) Z p = Z22;s=o Zc where ’s=o’ denotes the short/open standard. In order to prevent that potential coupling mechanisms (see Fig. 8a) should influence the extraction of Zc and Z p , the two simple standards can be measured one at a time with the other probe sufficiently isolated from the setup. Next, the remaining parameters are extracted from the measurements on the open and short standards as shown in Figs. 6b-c. From the model of the short standard in Fig. 8c, 00 (7) Z1 = Z11 ;s Z2

=

00 Z22 ;s

(8)


Note that pad and contact effects have first been de-embedded from the measured Z-parameters of the short standard. Similarly, from the eqvivalent model of the open standard in Fig. 8b, 2 (9) Zf = 000 000 Y12;o + Y21 ;o Z3

=

1 000 + Y 000 =2 + Y 000 =2 Y11 ;o 12;o 21;o

(10)

Z4

=

1 000 + Y 000 =2 + Y 000 =2 Y22 ;o 12;o 21;o

(11)

These solutions employ averaging of forward and reverse admittances. Using averaging of admittances over impedances makes the extraction process less sensitive towards measuring noise. This concludes the extraction of the fixture parasitics from the three fabricated in-fixture standards. (a) Short/ Open

(b) Open

Z f2 Zc

Zc Zp

(c) Short

Zc

Zp Z1

Zf

Z3 Z1

Zp

Z2 Z4 Z2

Zc

design effectively reduces (i) resistive substrate losses of input and output pads, (ii) dangling leg parasitics, and (iii) forward coupling of the fixture, several important advantages are achieved. Foremost, the fixture parasitics are qualitatively represented by a few easily-identified and dominating parasitics which makes de-embedding less complicated and enhances accuracy. By removing the test fixture forward coupling, the method is also scalable which gives a very cost-effective solution. One set of in-fixture standards can be used to predict the parasitics of almost arbitrarily sized test fixtures. The de-embedding method is based on general impedances and extraction is conducted with few standards which can be embedded with high accuracy in the ground-shielded fixture; even with low cost technologies. Hence, the proposed deembedding method eludes over-estimation problems reported with other approaches. This is convenient for CMOS technology where devices are typically very large to compensate for low device performance per area. Other de-embedding methods can easily be transferred to the ground-shielded test fixture, but the nature of the parasitics renders the chosen representation very accurate. Due to very few resistive effects of the ground-shielded test fixture, it is almost ideal for noise measurements on active devices.

Zc Zp Zc Zp

Fig. 8. Equivalent models for standards related to fixture model.

VI. C ONCLUSIONS In this paper a new ground-shielded measuring technique has been presented that effectively mitigates the effects of lossy substrates to obtain an accurate device measurement. Although the technique is generally applicable to most commonly used integrated processes, the performance improvement is highest when the substrate resistivity is very low. This makes the technique applicable to new low-cost RF-IC contenders such as silicon CMOS technology. To achieve the performance improvement, it is often necessary to violate design rules by leaving out a few metal layers in the signal pads. This is possible since the structure is compatible with standard processing. Ground-shielded test structures have been fabricated in several different CMOS processes without problems. If the ground shield located directly under the signal pads is removed and substituted with for instance a p+ implant, the structure becomes compatible with many standard process design rules. However, some or most of the performance benefit is unfortunately removed. By using a complicated extraction method, the major parasitics of the ground-shielded test fixture were identified and compared to a conventional test fixture. Since the test fixture

251

R EFERENCES [1]

J. N. Burghartz, “Silicon RF Technology — The Two Generic Approaches,” in Proceedings of European Solid-State Device Research Conference (ESSDRC), Stuttgart, Germany, September 1997, pp. 143– 153. [2] T. E. Kolding, On-Wafer Measuring Techniques for Characterizing RF CMOS Devices, Ph.D. thesis, RF Integrated Systems & Circuits (RISC) Group, Aalborg University, Niels Jernes Vej 12, 9220 Aalborg Øst, Denmark, August 1999. [3] M. C. A. M. Koolen, J. A. M. Geelen, and M. P. J. G. Versleijen, “An Improved De-Embedding Technique for On-Wafer High-Frequency Characterization,” in Proceedings of IEEE Bipolar Circuits and Technology Meeting (BCTM), Minneapolis, Minnesota, USA, September 1991, pp. 188–191. [4] H. Cho and D. E. Burk, “A Three-Step Method for the De-Embedding of High-Frequency S-Parameter Measurements,” IEEE Transactions on Electron Devices, vol. 38, no. 6, pp. 1371–1375, June 1991. [5] P. J. van Wijnen, H. R. Claessen, and E. A. Wolsheimer, “A New Straightforward Calibration and Correction Procedure for "On-Wafer" High Frequency S-Parameter Measurements (45 MHz - 18 GHz),” in Proceedings of IEEE Bipolar Circuits and Technology Meeting (BCTM), Minneapolis, MN, USA, September 1987, pp. 70–73. [6] T. E. Kolding, “On-Wafer Calibration Techniques for Giga-Hertz CMOS Measurements,” in Proceedings of IEEE International Conference on Microelectronic Test Structures (ICMTS), Gothenburg, Sweden, March 1999, pp. 105–110. [7] Cascade Microtech, Inc., Beaverton, Oregon, USA, Application Note LAYOUT19, Layout Rules for GHz-Probing, 1989. [8] J.-L. Carbonéro, G. Morin, and B. Cabon, “Comparison Between Beryllium-Copper and Tungsten High Frequency Air Coplanar Probes,” IEEE Transactions on Microwave Theory and Techniques, vol. 43, no. 12, pp. 2786–2793, December 1995. [9] J. Plá, W. Struble, and F. Colomb, “On-Wafer Calibration Techniques for Measurement of Microwave Circuits and Devices on Thin Substrates,” in IEEE MTT-S International Microwave Symposium Digest, Orlando, Florida, USA, May 1995, vol. 3, pp. 1045–1048. [10] C.-H. Kim, C. S. Kim, H. K. Yu, and K. S. Nam, “An Isolated-Open Pattern to De-Embed Pad Parasitics,” IEEE Microwave and Guided Wave Letters, vol. 8, no. 2, pp. 96–98, February 1998. [11] T. E. Kolding, “A 4-Step Method for De-Embedding Gigahertz OnWafer CMOS Measurements,” To appear in IEEE Transactions on Electron Devices in 2000. [12] P. A. Gould and R. G. Davis, “The Use of EM Simulation in On-Wafer Microwave Device De-Embedding,” in Proceedings of IEE Colloquium on Effective Microwave CAD (Ref. No: 1997/377), London, England, December 1997, pp. 2/1–2/5.