Harmonic Minimization in Multilevel Inverters Using

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2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI), 21-22 Sept. 2017

Harmonic Minimization in Multilevel Inverters Using Numerical Series Technique Angshuman Sharma

Kallol S. Kashyap

Dept. of Electrical Engineering Tezpur University Tezpur, Assam, India [email protected]

Dept. of Electronics & Communication Engineering NERIST Nirjuli, Arunachal Pradesh, India [email protected]

Abstract— Cascaded multilevel inverters have received considerable attention from industries and researchers for high voltage and medium power applications. Numerous modulation and harmonic minimization techniques have been suggested to reduce the total harmonic distortion (THD) in multilevel waveforms. Recently a harmonic minimization technique based on numerical series has been reported. This technique was investigated for multilevel waveforms having different voltage levels and the resulting THDs were found to be satisfactory. However, no experimental result of this technique is available as yet. This paper presents the hardware design of a single-phase 50 Hz, 230 V, 84 W cascaded inverter fed by a single 12 V dc source. Wave-stepping was used to generate a 9-level voltage waveform with only two H-bridge cells. The concept of open drain mode of MOSFETs was used to drive the high side switches. Experimental results are presented to validate the feasibility of the approach. Keywords—multilevel inverter; cascaded inverter; total harmonic distortion; harmonic optimization; switching angles

I. INTRODUCTION Multilevel inverters have revolutionized inverter technology. A multilevel inverter produces a staircase-type output voltage waveform which is a stepped approximation of a pure sinusoidal waveform [1-3]. As such, the multilevel waveform contains fewer harmonics compared to a bipolar waveform and thus permits higher voltage levels to be reached easily without incurring significant losses. Multilevel inverter finds application in reactive power compensators [4], power conditioners [5], uninterruptible power supplies [6], magnetic resonance imaging systems [7], renewable energy applications [8], variable frequency drives [9], high voltage dc (HVDC) systems [10], and electric vehicles [11]. A significant advantage of the multilevel inverter is that the desired output voltage at any given frequency can be increased by increasing the number of levels [2, 12]. Additionally, increasing the output voltage levels does not require an increase in the voltage rating of the power switches. If the multilevel waveform contains infinite voltage levels, the harmonic content of the waveform should be ideally zero. However, increasing the voltage levels will proportionally

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increase the number of power switches. So, the number of achievable voltage levels is restricted by cost, footprint, switching loss, switching stress, control complexity, efficiency, voltage unbalance problem and voltage clamping requirement [5, 13, 14]. Three popular multilevel inverter topologies have been developed: diode clamped [15, 16], capacitor clamped [17] and cascaded H-bridge multilevel inverter with separate dc sources [5-6, 11]. The diode clamped inverter utilizes a capacitor bank series to provide multiple voltage levels. The output voltage can be increased by increasing the number of series connected dc bus capacitors. This inverter is highly efficient with respect to fundamental switching frequency and has a simple control mechanism. However, the primary disadvantage is the excessive number of clamping diodes that the inverter uses, and severe voltage unbalance problem which makes real power flow quite difficult. The capacitor clamped inverter is similar to the diode clamped design but allows better balancing of the voltage across the clamped capacitors. This design allows long discharge transient and lower harmonic distortion at higher voltage levels, better control of real and reactive power flow, and flexible switch redundancy for balancing different voltage levels. But large number of capacitors increases the cost, weight and footprint of the system, and a complex control mechanism will be required to maintain the voltage balance across the capacitors. Cascaded inverter is the most popular topology. Here, the output voltage is obtained by cascading the outputs of several H-bridge inverters, each powered by a separate dc source, such as a battery, fuel cell or solar cell. Fig. 1 shows a cascaded H-bridge multilevel inverter. The series power conversion cells in the cascaded inverter permits easy scaling of voltage and power levels [18]. With simple control circuitry, the cascaded inverter is easier to implement when compared to other multilevel inverters due to its circuit layout flexibility, relatively fewer bus capacitors, clamping diodes and voltage balancing capacitors, superior reliability and efficiency, and easy adjustment of the output voltage by adding or reducing the number of H-bridge cells in cascade [1, 19]. However, the cascaded inverter requires separate dc

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solutions to complex equations which are non-linear as well as transcendental in nature, and suggest a possibility of multiple solutions. Various iterative methods and evolutionary algorithms have been used to solve these complex equations for determining the optimum switching angles, which are discussed in the subsequent section. Recently a mathematical technique based on the arithmetic series of natural numbers was proposed in [27]. With simpler formulation, this technique is fast, efficient and reliable, and does not require to solve the complex non-linear equations to find the switching angles. This technique was theoretically investigated for 9-level, 11-level and 13-level waveforms and the THDs were found to be 8.99 %, 8.14 % and 7.99 % respectively, indicating significant decrease in THD with increase in the number of levels. However, no experimental result of this technique is available as yet. This paper presents the hardware design of a single-phase 50 Hz, 230 V, 84 W wave-stepped inverter fed by a single 12 V dc source, where only two H-bridge cells are capable of producing a 9-level inverted waveform. The switching angles are determined using this mathematical technique and the experimental THD is presented for validation of the hypothetical results. Fig. 1.

Cascaded H-bridge multilevel inverter.

sources to power each H-bridge cell which serves as a major difficulty. Recently a new class of hybrid multilevel inverters based on switched capacitors have been reported in [20-21], however it is beyond the scope of this paper. Current research in cascaded inverters includes reducing the number of power switches, and finding out novel modulation and harmonic minimization techniques to reduce the total harmonic distortion (THD) of the output voltage waveform [19]. Reducing the number of power switches for a given output voltage can help in achieving higher efficiency at lower cost. Several modulation techniques have been developed or adopted for multilevel inverters, such as sinusoidal PWM (SPWM), selective harmonic elimination PWM (SHEPWM), space-vector PWM (SVPWM), phaseshifted PWM (PSPWM), phase disposition PWM (PDPWM), and multi-carrier sinusoidal PWM (MSPWM) [22-26]. Besides the modulation techniques, two standard harmonic minimization techniques are frequently employed to reduce THD in multilevel inverters: optimal minimization of the total harmonic distortion (OMTHD) and optimized harmonic stepped-waveform (OHSW) [12-13]. OMTHD technique tries to adjust the switching angles in a way such that most harmonics of the multilevel waveform are reduced without emphasizing on eliminating any specific component. When this goal cannot be met, the highest possible harmonics optimization is desired. OHSW technique tries to adjust the switching angles in such a way that specific lower frequency significant harmonics are eliminated while generating the desired fundamental component of the multilevel waveform. Both these harmonic elimination techniques give efficient THD figures and thus, eliminate the requirement for additional filters. Moreover, since the power devices turn on and off only once in each cycle, switching loss and EMI are reduced considerably. However, these techniques require analytical

II. HARMONIC OPTIMIZATION IN MULTILEVEL WAVEFORM A cascaded inverter having s H-bridge cells produces a voltage waveform having (2s+1) levels, with s positive voltage levels, s negative voltage levels and 1 zero voltage level. Fig. 2 shows an odd quarter-wave symmetric stepped waveform having (2s+1)-levels, where V1 – VS are the step heights or individual voltage of the dc sources and α1 – α5 are the switching angles of the first quarter wave. Since the waveform is odd quarter wave symmetric, all even harmonics will be naturally reduced to zero and Fourier analysis of the first quarter wave from 0 to π/2 is sufficient to calculate the amplitude of the fundamental and odd harmonic components of the complete waveform. If the step heights are assumed to be equal, i.e. V1 = V2 ……= VS = E, then the amplitude of the harmonic components of the waveform can be expressed as,

 sE s   cos(n k ) H n ( )   n k 1 0 

Fig. 2.

for odd harmonics (1) for even harmonics

Odd quarter-wave symmetric nine-level stepped waveform.

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Thus the Fourier series of the output voltage waveform can be given as,   sE s  Vout (t )     cos(n k )  sin(nt ) n 1  n k 1 

(2)

The THD evaluates the extent of harmonic content in the waveform. Mathematically, it can be stated as, 

THD 

H n2

2 n

(3)

H1

Where H1 is the amplitude of the fundamental component at desired frequency ω0 and Hn is the amplitude of the nth harmonic at frequency nω0. Substituting H1 and Hn in (3), we have, 

THD 

1

s

  n  cos(n ) n2

k

k 1

s

 cos( k 1

k

2

  

(4)

)

For determining the harmonics of a multilevel waveform of s-levels, s numbers of switching angles, i.e. α1, α2,…, α5, need to be known. Mathematically, s-numbers of equations need to be set up to determine the switching angles. Unfortunately, these equations are nonlinear as well as transcendental in nature, which indicates a possibility of multiple solutions. Additionally, the switching angles must satisfy the following condition: α1, α2,…, α5 < π/2 [27]. Iterative methods, like the Newton–Raphson (N-R), were initially used to solve this set of non-linear equations [28]. However, such methods need a close initial guess, otherwise it becomes infeasible to solve the optimization problem for a large number of switching angles. Furthermore, possible divergence problem in case of higher voltage levels yields a higher value of THD [13]. Mathematical theory of resultant was also applied to solve the non-linear equations, however the scope of this method was limited by the number of voltage levels or switching angles. Moreover, this method is complicated and time-consuming [28]. Homotopy algorithm was also used for finding solutions to the set of non-linear equations. Although this method uses simpler formulation, it requires an initial guess of a good convergence-control parameter, otherwise more iterations will result [29]. Evolutionary algorithms like genetic algorithm, bee algorithm, particle swarm optimization, bacterial foraging algorithm and ant colonization have also been applied to solve the non-linear complex equations of multilevel inverters [18,

28, 29-32]. These methods are robust, popular and could efficiently reduce the lower order harmonics resulting in minimum THD. But evolutionary algorithms are cumbersome and require extensive computing, while there is still no guarantee for finding optimal solution within a finite amount of time. Moreover, a large number of parameters need to be adjusted. The mathematical technique, recently proposed in [27], does not require to solve the complex non-linear equations at all in order to determine the optimum switching angles which could significantly reduce the THD of the multilevel waveform. This technique uses the simple Arithmetic Sequence of Natural Numbers, which is 1, 2, 3, 4,……, n, to determine the step spaces of the multilevel waveform. If time is considered as the reference, this technique assigns 1 unit of time for the 1st step space, 2 units of time for the 2nd step space, and so on till the last step space is completed before π/2. This technique was theoretically investigated for 9-level, 11-level and 13-level waveforms and the corresponding THDs were observed to be 8.99 %, 8.14 % and 7.99 %. Fig. 3 shows the quarter wave of a 9-level cascaded inverter having equal step heights. Here, t1 – t4 indicate the switching instants. This quarter wave has five steps, indicating four H-bridge cells in the 9-level cascaded inverter. Considering 50 Hz as the operating frequency or 20 ms as the time period, first step space is assigned 1 unit of time, second step space is assigned 2 units of time, third step space is assigned 3 units of time, fourth step space is assigned 4 units of time, and the fifth and final step space of the first quarter wave is assigned 5 units of time. The switching instants for the four H-bridge cells in the first quarter wave were calculated in [27] using the above technique and were found to be t1 = 0.000333 s, t2 = 0.001 s, t3 = 0.002 s and t4 = 0.003333 s. The corresponding switching angles were found to be α1 = 6˚, α2 = 18˚, α3 = 36˚, α4 = 60˚. Using these switching angles, the theoretical THD of the 9-level waveform was calculated, which was found to be 8.99 %. Using quarter wave symmetry, switching angles for the full wave was calculated and is presented in Table 1. The following section presents the hardware design of a singlephase 50 Hz, 230 V, 84 W cascaded inverter fed by a single 12 V dc source. The calculated switching angles were implemented to check the validity of the hypothetical results.

Fig. 3.

Quarter wave of a 9-level inverter waveform.

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TABLE I SWITCHING ANGLES FOR THE COMPLETE WAVE Quarter 1 φ

Quarter 2 180˚ - φ

Quarter 3 180˚ + φ

Quarter 4 360˚ - φ



180˚

180˚

360˚



174˚

186˚

354˚

18˚

162˚

198˚

342˚

36˚

144˚

216˚

324˚

60˚

120˚

240˚

300˚

Fig. 5.

Fig. 4. Circuit configuration of the 9-level inverter circuit using wavestepping.

III. HARDWARE MODELLING

Desired 9-level waveform using wave-stepping.

A single 12 V, 7 A-H hour lead-acid battery was used as the voltage source. Using a single voltage source helps in maintaining equal voltage at the primaries of the two transformers. The outputs of the two H-bridge cells were fed to two transformers whose secondary voltages should maintain a ratio of 3:1. Since the desired output voltage was 230 V while the input voltage was 12 V, the turns ratio of the two transformers were accurately calculated and found to be 1:14.4 for the transformer associated with inverter I (Transformer I) and 1:4.8 for the transformer associated with inverter II (Transformer II). Two transformers were appropriately designed so that the voltage across the secondary of Transformer I is (14.4 × 12 V =) 172.8 V, while that across Transformer II is (4.8 × 12 V =) 57.6 V. The desired 9-level voltage waveform was obtained by superimposing the secondary voltages of these two transformers as shown in Fig. 6, i.e. 172.8 V + 57.6 V = 230.4 V ≈ 230 V, which is the desired output voltage of the inverter. Further, the primary sides of the two transformers were designed to carry more than 10 A of current. The use of transformer helps in providing galvanic isolation between the source and the load, which adds to the safety and reliability of the system.

A. Circuit configuration The main disadvantage of the cascaded inverter is that to produce a 9-level voltage waveform, four H-bridge cells are required, which adds to the cost, size and complexity of the system. Wave-stepping was used to design a cascaded inverter which produced an output voltage waveform of 9-levels using only two H-bridge cells. In this method, pulses of different widths and heights are added to produce a resultant stepped wave [33-34]. Fig. 4 shows the configuration of the 9-level inverter circuit using wave-stepping. It can be observed from Fig. 4 that the circuit configuration uses only 8 switches, 4 for each inverter, which reduces the number of switches to half of what is required for a 9-level cascaded inverter consisting of four H-bridge cells.

B. Selection of switching devices The voltage and current specifications of the cascaded inverter at the primary side of the two transformers are limited to 12 V and 7 A respectively, taking a total input power of 84 W. Additionally, the power switches must be voltagecontrolled to enable the implementation of a simple controller. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and Insulated Gate Bipolar Transistor (IGBT) are the two most popular voltage-controlled solid state switches which can be used as the primary switching device in power electronic converters. However, MOSFET is preferred over IGBT for low voltage (< 250 V) and low power (< 500 W) applications [35]. Moreover, MOSFET contains the intrinsic

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body diode that provides a path for free-wheeling current which is absent in IGBT [36]. N-channel MOSFET has some inherent performance advantage over P-channel MOSFET. In case of N-channel MOSFET, electrons serve as the majority charge carriers that have a mobility greater than the holes, which forms the majority charge carriers in P-channel MOSFET. This results in a low on-state resistance of the N-channel MOSFETS, enabling high switching frequency to be incorporated easily and hence becomes the preferred choice as the primary switching device for most converters. An N-channel depletion-type power MOSFET differs from the enhancementtype in that it is normally ON at 0 V gate bias and requires a negative gate bias for its commutation [37]. Thus additional circuit is required to apply a negative potential to the Nchannel depletion-type MOSFET for its commutation. Since N-channel enhancement-type MOSFET requires a positive gate voltage to turn ON and a zero gate voltage to turn OFF, it operates perfectly as a switch and is easy to interface with logic gates. Thus N-channel enhancement-type MOSFETs were considered to serve as the switching devices for the cascaded inverter. International Rectifier’s IRLB4132 [38] was chosen as the preferred N-channel enhancement-type MOSFET for all the eight power devices in the two H-bridge cells of Fig. 4. This MOSFET has a drain-to-source breakdown voltage of 30 V and a continuous drain current of 150 A. Moreover, it exhibits very small drain-to-source ON resistance of 3.5 mΩ and significantly lower transition times. C. Controller Microcontroller development board Arduino UNO R3 was used to generate signals required to control the switching instants of the MOSFETS of both the H-bridge cells. It was necessary to introduce a proper dead band between the OFF and ON states of the MOSFETS in the alternating legs of the H-bridge cells to avoid shoot-through problem. IRLB4132 exhibits a turn-on delay time of 23 ns, rise time of 92 ns, turnoff delay time of 25 ns and fall time of 36 ns [38]. Considering other parasitic elements present in the circuit, a suitable dead band of 3 µs was introduced through the controller board. The microcontroller was appropriately programmed to generate the required gate drive control signals. D. Design of high-side gate driver To trigger an N-channel enhancement-type MOSFET, the positive gate voltage required must satisfy the following condition, VGS > VT

or

VG > V T + V S

(5)

Where, VG is the gate voltage with respect to ground, VT is the gate threshold voltage, VS is the source voltage with respect to ground and VGS is the gate voltage with respect to source voltage. For MOSFET IRLB4132, the gate threshold voltage is 2.35 V [38]. So incidentally, VG should be greater than VS by at least 2.35 V to trigger the MOSFET.

+15V

Fig. 6.

Gate drive circuit for high side MOSFETs.

In the two H-bridge cells of Fig. 4, the source terminals of the low side MOSFETs were connected to ground, while those of the high side MOSFETs were connected to the load. This resulted in a floating voltage to appear at the source terminals of the high side MOSFETs, as VS ≠ 0 V. Since a 12 V battery was used as the power source for the two cells, considering 12 V as the maximum floating voltage that could appear across the source terminals of the high side MOSFETs at the instant of switching, VG should be equal to at least (12 V + 2.35 V =) 14.35 V in order that the high side MOSFET triggers. The output of a microcontroller, which was approximately 4.8 V, was sufficient to trigger the low side MOSFETs, but insufficient to trigger the high side MOSFETs. This brought the need for a gate driver circuit to drive the high side MOSFETs. To generate a gate drive signal of 14.35 V, the concept of open drain mode of MOSFET was used. The high side gate drive circuit is illustrated in Fig. 6. A boost converter was used to boost the 12 V dc voltage to 15 V, which was then applied across the voltage divider circuit consisting of resistance R1 and R2. Resistance R1 and R2 were so chosen that,

R2

( R1  R2)

 14.35V

(6)

Taking R1 = 47 Ω and R2 = 2.2 kΩ, a voltage of approximately 14.7 V was made available at point A, which was sufficient for driving the high side MOSFET Q1. However, this arrangement would provide a constant voltage of 14.7 V at the gate of Q1, which was not desired. In order to control the switching of Q1, an auxiliary switch Qg was introduced whose drain terminal was connected to point A and source terminal to the system ground. Since the source of Qg was grounded, the 4.8 V signal from the microcontroller was sufficient to trigger Qg. Qg was operated in a way such that it remained normally ON, so that voltage across point A was pulled down to a very low value, insufficient to trigger Q1. Q1 is triggered by commutating Qg which made a voltage of 14.7 V available at point A. Thus Q1 was triggered by commutating Qg and vice versa. Qg worked on similar principle of open collector mode in BJTs. Four additional MOSFETs were required to achieve the operation of open drain mode for the two H-bridge cells of the cascaded inverter. The same MOSFET IRLB4132 was used as the auxiliary switch Qg for the two H-bridge cells.

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IV. EXPERIMENTAL RESULTS In order to experimentally verify the validity of the harmonic optimization technique in [27], a single-phase 50 Hz, 230 V, 84 W wave-stepped inverter fed by a single 12 V dc source was designed. Fig. 7 shows the experimental test model. The waveforms at various points were recorded in an oscilloscope (Tektronix TDS 2014C) and are presented in Fig. 8 – 10.

Fig. 7.

Experimental test model of the wave stepped inverter.

Since the source terminals of the low side MOSFETs of the two H-bridge cells were grounded, a gate threshold voltage of 2.35 V was sufficient to trigger them. The output voltage of the microcontroller, which was approximately 4.8 V, was directly fed to the gates of these MOSFETs for triggering. Fig. 8 (a) shows the control signals generated by the microcontroller to drive the gates of the low side MOSFETs Q2 and Q3 of inverter I. Fig. 8 (b) shows the control signals generated by the microcontroller to drive the gates of the low side MOSFETs Q6 and Q7 of inverter II. The concept of open drain mode of MOSFETs was used to generate a boosted control signal of approximately 15 V required to drive the high side MOSFETs of the two H-bridge cells. Q1 was triggered by commutating Qg(I) and vice versa. Since Q1 and Q3 formed a pair of switches having the same switching instances, Qg would require an inverted gate drive signal with respect to Q1 or Q3. Qg(I) and Qg(II) are grounded, the 4.8 V control signal from the microcontroller was sufficient to drive the gates of these auxiliary switches. Fig. 8 (c) shows the gate drive signals for Q3 and Qg(I) of inverter I, while Fig. 8 (d) shows the gate drive signals for Q7 and Qg(II) of inverter II. Fig. 8 (e) shows the boosted gate drive signal for Q1 and the gate drive signal for Q3. Fig. 8 (f) shows the boosted gate drive signal for Q5 and the gate drive signal for Q7. The two signals in Fig. 8 (e) and (f) have the same phase and frequency as desired. Further, it can be observed that the boosted gate drive signals have a voltage of approximately 15 V, which was necessary to drive the high side MOSFETs of the two bridges. The output of the two H-bridge cells were observed in the oscilloscope. In Fig. 9 (a), curve (i) and curve (iii) are the voltage waveforms across the two complementary pairs of switches of inverter I, which have a phase difference of 180˚. Curve (ii) is the voltage waveform obtained across the output

of inverter I, which exactly matches the theoretical waveform depicted in Fig. 5. In Fig. 9 (b), curve (i) and curve (iii) are the voltage waveforms across the two complementary pairs of switches of inverter II, which have a phase difference of 180˚. Curve (ii) is the voltage waveform obtained across the output of inverter II, which exactly matches the theoretical waveform depicted in Fig. 5. The outputs of the two H-bridge cells were fed to two transformers having a varied turns ratio. The resultant output of the cascaded inverter obtained by superimposing the secondary voltages of the two transformers is fed to a resistive load of 10 kΩ. The voltage waveform was observed across an oscilloscope and is shown in Fig. 10. The waveform has a frequency of 50 Hz which is the standard power line frequency in India. Due to a minor mismatch in the turns ratio of the two transformers, the number of levels is slightly difficult to identify. The oscilloscope permits to view the Fast Fourier Transform (FFT) of the waveform and is represented in Fig. 11. FFT of the output waveform enabled us to observe the amplitudes of the fundamental and odd harmonics present in the output voltage waveform and thus to calculate the THD. The peaks of the waveform represent the amplitudes of the fundamental odd harmonic components. The THD of the waveform was calculated using the FFT and was found to be 4.79 % without the use of any filters, which was much less than the hypothetical THD of 8.99 %. V. CONCLUSION Multilevel inverters have revolutionized inverter technology. Among the various multilevel inverters, cascaded inverter has proved to be the most popular topology. Numerous modulation and harmonic optimization techniques have been suggested to reduce the total harmonic distortion (THD) of the output voltage waveform. Recently a novel harmonic optimization technique has been reported, which uses the arithmetic sequence of natural numbers to calculate the switching angles of the multilevel waveform. With simpler formulation, this technique is fast, efficient and reliable, and does not require to solve the complex non-linear equations to find the switching angles. This technique opens new doors to investigate the numerous numerical series for calculating the switching angles of cascaded inverter for minimum harmonic distortion. This paper presents the experimental verification of the hypothetical technique. A single-phase 50 Hz, 230 V, 84 W cascaded 9-level inverter fed by a single 12 V dc source was designed. Wave-stepping was used to generate the 9-level voltage waveform using only two H-bridge cells. Two transformers were designed in a way such that their secondary switches of the two inverters could be directly driven by the 4.8 V controller output. However, to drive the high side switches, a gate drive voltage of approximately 15 V was required. The concept of open drain mode of MOSFETs was used to drive the high side switches. This gate drive technique was simple, fast and accurate. However, four auxiliary switches were required to drive the primary high side switches, which added to the cost of the system. The waveforms at various points were recorded in an oscilloscope and are presented in this paper. The waveform has a frequency

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(a)

(f) Fig. 8. (a) Gate drive signals for Q2 and Q3. (b) Gate drive signals for Q6 and Q7. (c) Gate drive signals for Q3 and Qg(I). (d) Gate drive signals for Q7 and Qg(II). (e) Boosted gate drive signal for Q1 and gate drive signal for Q3. (f) Boosted gate drive signal for Q5 and gate drive signal for Q7.

(b)

(a)

(c)

(b) Fig. 9. (a) Waveform of the output taken across the H-bridge of inverter I. (b) Waveform of the output taken across the H-bridge of inverter II.

(d)

(e)

Fig. 10.

Output waveform of the cascaded inverter.

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Fig. 11.

FFT of the output waveform of the cascaded inverter.

of 50 Hz which is the standard power line frequency in India. Due to a minor mismatch in the turns ratio of the two transformers, the 9-level in the output voltage waveform was difficult to identify. Realising soft switching of the power devices can further improve the THD of the multilevel waveform. The FFT of the output voltage waveform and experimental THD are presented to validate the feasibility of the approach.

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[7]

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