HCC-based interleaved boost converter with optimal switching frequency control of wind energy conversion system for DC microgrid application V. Karthikeyan1, S. Rajasekar2, B. Chitti Babu3, Praveen Yadav1, P. Karuppanan4, Haider A.F. Almurib3, S. Tamilselvi5 1

Department of Electrical Engineering, M.N. National Institute of Technology, Allahabad, India Smart Energy Division NEC Laboratories Singapore, NEC Asia Paciﬁc Pte Ltd., Singapore, Singapore 3 Faculty of Engineering, The University of Nottingham Malaysia Campus, Semenyih 43500, Malaysia 4 Department of Electronics & Communication Engineering, M.N. National Institute of Technology, Allahabad, India 5 Department of Electrical Engineering, SSN College of Engineering, Chennai, India E-mail: [email protected] 2

Published in The Journal of Engineering; Received on 9th June 2017; Accepted on 28th June 2017

Abstract: This study exploited the hysteresis current control (HCC) with optimal switching frequency for interleaved boost converter to improve the power factor of wind energy conversion system (WECS) exclusively for DC microgrid applications. By fact that output power from WECS is variable due to unpredictable wind speed, where the HCC suffers with range of switching frequency, high switching loss, large input current ripple and poor power factor. To overcome the aforementioned problem, an automatic tuning procedure has been developed for proportional–integral–derivative (PID) voltage regulator to achieve optimal feedback gain of ﬁlter inductor current and thereby optimal switching frequency is maintained with good power factor, low harmonic distortion and improved efﬁciency. Additionally, the robust PID voltage regulator guarantees the stability and investigated through bode plots. Hardware prototype model is implemented in the laboratory standards with Spartan 3AN ﬁeld programmable gate array control board. The experimental results obtained are conﬁrming the theoretical background aspects of the operating regimes.

1

Introduction

Predominant requirement in any AC/DC power conversion stages requires good power factor correction (PFC) both in light/heavy and or dynamically varying loads with high quality, high efﬁciency and operable reliability [1]. In particular, for clean energy generation systems, wind energy conversion system (WECS) plays vital role, where permanent magnet synchronous generator is used as prime mover in application, i.e. the diode bridge rectiﬁer is connected across wind turbine to convert generated AC power into unidirectional DC power [2]. Method results in low cost, simple structure, robustness and absence of complex controls but the complete system suffers with poor input power factor by the injected lower-order harmonics to AC system. Results of the line voltage with harmonic components, equipment overheating, malfunction and deteriorate the total quality of system [3]. Many works articulate to improve the input power factor and to reduce current harmonics includes passive or active PFC techniques [4]. Renowned being PFC techniques by employing classical topologies such as boost, buck–boost- and buck-converters [5]. However, among these topologies, interleaved boost converter (IBC) is preferred for high-power application. In particular WECS, it offers high efﬁciency, improved power factor, lower harmonic distortion and reduced voltage stress across the switches [6, 7]. Higher switching frequency operated IBC provides PFC and exhibits the following merits: † Cascaded of multiple smaller units shares equally the demanded power, which reduces the size of the inductor, rating of the switch and diodes. Moreover, the reliability and cost aspects of the system get improved thereby. † Interleaved PFC converter operates at u = 360◦ /N and uN − uN−1 = 360/N ∀N [ [2N ], where N denotes the number of cells connected in parallel/series depends on current/voltage demands. Consequently, the current/voltage rating of the switches gets minimised. J Eng 2017 doi: 10.1049/joe.2017.0241

† IBC operates at higher switching frequency with ﬂexible in control and dynamically stable. † Higher operating frequency results in reduced ripple factor which in effect eliminate the needs of auxiliary ﬁlter circuitry, and thereby reduced overall cost. Such features make high switching frequency-controlled IBC topology extensively popular for high-power applications [8–13]. The DC–DC converters are operated normally in three modes, namely (a) continuous conduction mode (CCM), (b) discontinuous CM (DCM) and (c) critical conduction mode or transition mode control. Usually, converter will operate either in CCM or DCM and CCM is suitable for high-power applications, whereas DCM and critical conduction mode are suitable for low-/medium-power applications [14]. By literatures, different strategies to limit switching losses such as: appropriate design of inductor and capacitor, effect of interleaved boost stage, replacement of semiconductor switches, average current mode control and the hysteresis control [15–17]. Hysteresis comparators are the most popular control techniques, ensured by robustness and simple control strategy for easy implementation [18]. However, its switching frequency varies greatly during dynamic operating conditions [19] and several attempts are carried out to attain constant switching frequency while adopting hysteresis current control (HCC) [20, 21]. However, no inclusive articles focused on HCC application to IBC. Hence, this research work exploits the adoption of HCC to rectiﬁed DC current in IBC with ﬁxed hysteresis band which when used with an optimal linear proportional–integral–derivative (PID) controller leads to the following advantages: † Unity power factor. † Lower total harmonic distortion (THD). † Lesser ripple current. † Better stability in under dynamic load changes reinforced with simplicity and robustness.

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This paper proposed an automatic tuning algorithm and to demonstrate the optimal value of the feedback gain of ﬁlter inductor current is achieved, thereby optimal switching frequency and hence ensured minimal trade-off between switching power losses and current ripple. Furthermore, the design of robust PID voltage regulator which explicitly guarantees the dynamic stability is proposed in this investigation for set power system. Set of experimental results are provided in this paper to verify the theoretical background of the proposed control scheme. This paper is organised as follows: Section 2 deals with architecture of the complete power system conﬁguration. The proposed control algorithm ‘HCC to rectiﬁed DC in IBC-based PFC in WECS’ with its systematic structure has been given a lucid and elaborated in Section 2.1. Section 3 deals brieﬂy with small signal modelling of IBC and its use in switching frequency estimation for the optimal boundary region operation of IBC. Furthermore, in the same Section 3 robust PID voltage regulator is designed for the guaranteed dynamic stability of proposed scheme. Section 4 explicitly deals with overall stability analysis. Performance evaluation of the proposed control algorithm is validated with Spartan 3AN ﬁeld programmable gate array (FPGA) implementation in Section 5. Finally, the concluding remark is given in Section 6. 2

Detailed architecture system conﬁguration

The proposed control architecture of HCC technique for DC microgrid application is described in detail in Fig. 1, being constituted by: (a) micro wind turbine, (b) IBC unit reinforced with PFC, (c) PF measurement unit and (d) Spartan 3AN FPGA processor featured with reference current generation and voltage control loop. In detail, three-phase IBC operates in CCM and to maintain unity power factor with boost converter operates 120° phase difference [22]. The sensors are employed to measure the output voltage and current of WECS, and its current signal corresponding in voltage values is utilised for phase angle generation required to achieve unity power factor using zero crossing detector (ZCD)

[23, 24]. Power factor measurement unit is operated as follows: transistor is driven by square wave signal obtained through ZCD and produces 5 V signal either with respect to voltage or current signal. In general, for 50 Hz frequency, the transistor output signal period would be 20 ms and the transistor output pulse time period is similar to that of current waveform. If there occurs to be any phase difference between input voltage and current, exclusive or (X-OR) gate generates a pulse according to the phase delay of voltage and current. For the modulation of IBC, switching pulses shifted in phase by 120° with each other are generated by control logic consisting of voltage and current control loop implemented on FPGA. 2.1 Novel PFC approach: HCC technique to rectiﬁer DC current Fig. 2 shows schematic representation of the proposed PFC algorithm consisting of ZCD, phase locked loop (PLL) and angle to delay generator, i.e. HCC technique to rectiﬁed DC current for maintaining good PF. Furthermore, PLL is essential for combination of transistor drivers and X-OR logic gates. If there happens to be any phase angle mismatch between voltage and current, the PLL will generate a signal corresponding to the phase angle. Voltage and current sensing units are used to estimate the power generated (Pin) by wind energy system. Furthermore, frequency estimation through ZCD leads to calculation of respective time period which is required to generate reference rectiﬁed DC current. Use of enable/disable facilitated trigger control mechanism buffer logic allows the reference rectiﬁed DC current to rise at the instant when the voltage starts rising, to ensure unity PF. In case if PF is not unity, then the power generated from WECS is not delivered completely to DC bus. This demands the generation of reference rectiﬁed DC current according to voltage errors. The combined reference rectiﬁed DC current is compared with actual DC current. Moreover, the measurement of actual DC current does not involve any dedicated sensor, rather is obtained by the rectiﬁcation of AC input current.

Fig. 1 Detailed control structure of the proposed HCC method applied to IBC This is an open access article published by the IET under the Creative Commons Attribution-NonCommercial-NoDerivs License (http://creativecommons.org/ licenses/by-nc-nd/3.0/)

J Eng 2017 doi: 10.1049/joe.2017.0241

Fig. 2 Proposed HCC block diagram

Finally, the actual rectiﬁed DC current is controlled by optimally tuned hysteresis loop current controller to achieve the desired reference current with unity PF. When wind energy output power changes due to wind velocity, the generated reference current signal inevitably becomes variable and not just poses requirement of variable duty cycle but variable switching control structure as well. Therefore, variable K1, the feedback coefﬁcient of ﬁlter inductor current, is investigated as potential solution to achieve the variable frequency control structure with ﬁxed hysteresis band 2h. An excellent automatic tuning procedure has been developed to achieve optimal solution of K1 with switching loss and inductor current ripple as two optimisation variable. Procedure, design goals and solution of optimisation task has been extensively elaborated later in Section 3. Furthermore, a robust PID controller is designed for excellent regulation of DC-link voltage as per the reference voltage for suggested solution set K1 and hence fsw . The design procedure will be elaborated later in the text. 3 Switching frequency formulation and small signal modelling This section deals with formulation of analytical expression for maximum, minimum and average switching frequency applies to IBC. The following sets of assumption are made:

where ˆiLi is the inductor current variation, vˆ o (t) is the output voltage variation, Di is the nominal duty cycle, dˆ i is the duty cycle variation, RLi is the parasitic resistance of the inductor and Vin is the input voltage in nominal state. Inductor current dynamics for the IBC constituted by three parallel boost converter cells can be written as LDiL = Vin − ˆiLi (t)RLi − (1 − Di )ˆvo (t) + Vo dˆ i (t) D − 1/3 T

(2)

Simplifying (2) and replacing Vin = Vo (1 − D) leads to the following relation: DiL =

Vin − ˆiLi (t)RLi − (1 − Di )ˆvo (t) + Vo dˆ i (t) D − 1/3 T L (3)

The typical expression for instantaneous switching frequency, in IBC can be written as (4), without loss of generality and presumption that D denotes nominal duty cycle fsw

ˆ Vin − ˆiL (t)RL − (1 − D)ˆvo (t) + Vo d(t) (3D − 1) = 3LDiL

(4)

† All the switches, inductors, capacitors and diodes are ideal. † The output voltage (Vo) is larger than input voltage (Vin). † Three-stage boost converter inductors are equal (i.e. L1 = L2 = L3 = L).

The average value of the inductor is absolutely governed by reference current and average current can be constructed as

The linearised state-space differential equations for the IBC circuit as shown in Fig. 1 can be formulated as

where K1 is the servo coefﬁcient of ﬁlter inductor current, as the magnitude of inductor current ripple is strongly related to hysteresis band, so DiL = 2h/K1 [25] instantaneous switching frequency can now be parameterised as

⎫ ⎪ ⎪ = Vin − ˆiLi (t)RLi − (1 − Di )ˆvo (t) + Vo dˆ i (t) ⎪ ⎬ dt ∀i dˆv (t) ⎪ ˆ − ˆi (t) ⎪ ⎪ (1 − Di )ˆiLi (t) − ILi d(t) C C = ⎭ Load dt i i

Li

dˆiLi (t)

= [1, 3] J Eng 2017 doi: 10.1049/joe.2017.0241

iL =

fsw (1)

iref K1

ˆ (3D − 1) Vin − ˆiL (t)RL − (1 − D)ˆvo (t) + vo d(t) = 6Lh′

(5)

where h′ = h/K1 .

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The general trade-off between the inductor current ripple and switching loss demands the constraints on switching frequency bounds for efﬁcient modulation of switching converter. In HCC, the variable hysteresis band leads to variable switching frequency system and resulting higher switching loss or current ripple. The present work deals with a new approach toward optimal modulation of IBC under variable frequency control structure. Instead to vary hysteresis band, the variable servo (feedback) coefﬁcient of ﬁlter inductor current (K1) can provide an alternate solution to the variable frequency control under constant hysteresis band (2h). The procedural details are described in what follows.

switching frequency went beyond bound region, it will induce high switching loss, poor efﬁciency, high ripple and cause ageing effect to the system. Hence, an auto-tuning procedure needs to be developed such that the operating frequency lies within the neighbourhood of the optimal fsw. The optimal tuning of K1 helps to ﬁnd neighbourhood of the optimal switching frequency fsw and also satisﬁes the constraint on the current ripple h′ =

0.25 × Po Vo

(6)

3.2 Parameterisation of voltage regulator (PID) for given phase margin

3.1 Optimal switching frequency formulation Owing to the variable and stochastic nature of the wind speeds, output frequency ﬂuctuates with respect to the desired nominal frequency of 50 Hz. This will cause the duration over a cycle of rectiﬁed DC current in WECS to vary and as the consequence of which the reference current in this duration is in synchronism with input voltage to achieve unity power factor in the proposed control scheme. To ensure that the system operates at/around optimal switching frequency (with a tolerance limit of ±15%), it is necessary that optimal value of the parameter K1 should be considered so as to ensure proper trade-off between switching power losses and current ripple. When an optimisation task is carried out in search of optimal determination of K1, the search algorithm furnishes a distinct value of K1 at the end of search as shown in Fig. 3. The different values of K1 and its corresponding switching loss and inductor current ripple is shown in Fig. 4a. In the presented work with the assumption that inductor current ripple comes up DiL [ [0.5 − 0.7]A, the optimisation search algorithm

with solution set: K1 [ [0.71 − 0.99] and K1 Di = &f L optimal

The interleaved switching DC–DC boost converter exhibits nonminimum phase behaviour due to the inherent existence of an zero-right half plane zero (RHP) zero when it is operated under CCM and voltage control mode. To control output transfer function of the interleaved pulse-width modulation (PWM) DC–DC switching converter, the RHP zero is present as: 1 − ts, where t = Leq /R(1 − D)2 . The inherent time delay due to RHP zero of the boost converter can be expanded using Pade’s approximation (ﬁrst order) [26] e−ts =

(7)

Using general notation, the uncompensated system can be represented as follows: Guncomp =

sw optimal

0.81 as an optimal solution for K1. The switching frequency range investigated by optimisation task, shown in Fig. 4b, is fsw [ [19.2 − 26.4] kHz with an optimal switching frequency fsw = 21.6 kHz. As per theoretical calculation using (5), the maximum and minimum switching frequencies of the converter considered to be bound in the region of fsw [ [13.33 − 40.132] kHz for efﬁcient operation. If HCC operates in the

H(s) I(s)

P˜ (s) −ts P˜ (s) H (s) P(s) = †e = † ˜ (s) ˜ (s) I (s) Q(s) Q Q

(8)

Moreover, the time delay element can be taken in feedback loop (sensor delay) or in feed-forward loop (actuator delay), the frequency response and hence the conclusion for the stability ˜ (s) remains still true. Here in the presented study, the term Q included the time delay element arising due to the digital

Fig. 3 Flowchart description of optimal search algorithm This is an open access article published by the IET under the Creative Commons Attribution-NonCommercial-NoDerivs License (http://creativecommons.org/ licenses/by-nc-nd/3.0/)

J Eng 2017 doi: 10.1049/joe.2017.0241

The PID regulator is designed as per the procedure outlined in [27]. The complex form of the open-loop transfer function of the compensated system is Gcomp = C(jv)Guncomp (jv) Gcomp =

v2 Po Kp − Ki Pe + v2 Kd Pe (vKp Pe + vPo Ki − v3 Kd P) −j 2 v Qo − jvQe v2 Qo − jvQe (12)

As mentioned in [28], the discernment/determination of the margin of stability and in turn assurance of a robust controller design, through the desired phase margin, certain conditions can be inferenced a ReGcomp jvc = − cos (sm ) b ImGcomp jvc = − sin sm d Re Gcomp jvc =0 c dvc Fig. 4 Optimal switching frequency location trade-off analysis and recommended region of operation

implementation of controller (delay introduced in transmitting the controller’s output). The Taylor series expansion was used for approximating the timed delay term e−td s , as shown in Fig. 5, and ˜ (s) in denominator of (8). thus resulting in equivalent Q The PID controller in parallel form can be represented by C = Kp +

Ki + Kd †s s

where sm is the preset phase stability, vc is the crossover frequency obtained using optimisation, ReGcomp is the real part of compensated system, ImGcomp is the imaginary part of compensated system and dRe Gcomp jvc /dvc = 0 is the derivative of real part taken with respect to frequency. Substituting (12) into the above system of conditions, a set of explicitly deﬁned algebraic equations are formulated with the objective of achieving the desired PID controller gains

(9) Kp x11 + Ki x12 + Kd x13 = y1 Kp x21 + Ki x22 + Kd x23 = y2

where symbols used in (9) have usual meaning. On substituting s = jv the frequency-domain representation of uncompensated system and PID controller is given as [27] Guncomp (s) =

P(s) P (v ) + jv Po (v ) = e Q(s) Qe (v) + jvQo (v)

K C = Kp + i + Kd †jv jv

(13)

(10)

(14)

Kp x31 + Ki x32 + Kd x33 = 0

Solving (14), the equivalent coefﬁcients can be expressed as

(11)

x11 = v4 Po Qo + v2 Po Qe x12 = v2 Po De + v2 Ne Do

where Pe and Po are even and odd parts of P(s) [the numerator in (8)]. Similar deﬁnition holds for denominator Q(s) of (10).

(15)

x13 = v4 Pe Qo + v4 Po Qe

Fig. 5 Controller structure for stability analysis in parlance of linear system theory J Eng 2017 doi: 10.1049/joe.2017.0241

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x21 = v3 Po Qe + v3 Pe Qo x22 = −vPe Qe + v3 Po Do

(16)

x23 = v3 Pe Qe + v5 Po Qo

x31

⎛ ′ ′ Po Q2e Qo + Po Q2e Qo ′ ⎜ ′ ′ ′ 2 2 = v8 Po Q3o − Po Qo Q2o + v6 ⎜ ⎝ +Pe Qe Qo + Pe Qe Qo ′

⎞

′

⎟ ⎟ ⎠

−2Po Qe Qe Qo − 2Pe Qe Qo Qo

x32

x33

+ v5 2Po Q2e Qo − 2Pe Qe Q2o ′ ′ + v4 Pe Q3e − Pe Qe Q2e ′ ′ ′ ′ ′ = v6 Po Qe Q2o − Pe Q3o + Pe Qo Q2o + Po Qe Q2o − 2Po Qe Qo Qo (17) + v5 2Pe Q3o − 2Po Qe Q2o ′ ′ Po Q3e − Pe Q2e Qo − + v4 ′ ′ ′ Pe Q2e Qo + 2Pe Qe Qe Qo − Po Qe Q2e ′ ′ ′ ′ = v8 Pe Q3o − Pe Qo Q2o − Po Qe Q2o + 2Po Qe Qo Qo ′ ′ 2 2 ′ 3 6 Pe Qe Qo + Pe Qe Qo − Po Qe +v ′ ′ +Po Qe Q2e − 2Pe Qe Qe Qo + v5 2Pe Q2e Qo − 2Po Q3e y1 = − cos s v2 Q2e + v4 Q2o y2 = − sin s v2 Q2e + v4 Q2o

(18)

Po (s), Qo (s) are derivatives with respect to the frequency. Using the obtained equivalent coefﬁcients from the aforementioned set of well-deﬁned equations, Kp , Ki and Kd in terms of frequency ω

x x y + x22 x33 y1 − x12 x33 y2 − x23 x32 y1 Kp vc = 13 32 2 ∂ x11 x33 y2 − x13 x31 y2 − x21 x32 y1 − x22 x31 y1 Ki vc = ∂ x12 x31 y2 − x11 x32 y2 + x21 x32 y1 − x22 x31 y1 Kd vc = ∂

(19)

(20)

The parameterisation of PID is mono-variable system in v. Estimation of crossover frequency leads to explicit formulation of PID controller with desired phase margin. To achieve the PID controller gains, the crossover frequency has to be speciﬁed. As mentioned in [28], with higher gain crossover frequency system tends to exhibit more oscillatory nature as the transient time decreases, thereby reducing the transient nature of the process response. Using the integral of time-weighted absolute error (ITAE) minimisation, the optimal crossover frequency can be obtained 1

te(t )dt

77 , 7.96×103

(21)

0

So, from (19) it can be seen that each parameterisation of controller depends on phase margin and gain crossover frequency. Fig. 5

(22) . So,

optimisation is just one way to ﬁnd optimum crossover frequency and/or phase margin. However, can be calculated manually too. 4

Dynamic stability of the proposed controller

A phase margin of more than or close to 76° is required for guaranteed absence of overshoot in output voltage [29]. The small signal model of IBC is derived as follows using the state-space averaging techniques analytically derived for ILBC, in the Appendix: vˆ o = 1.135 dˆ × 103

(1 + 8.116 × 10−6 s)(1 − 1.316 × 10−4 s) 1.212 × 10−6 s2 + 2.203 × 10−4 s

(23)

Fig. 5 shows the block diagram of closed-loop compensator structure and their frequency-domain stability response is depicted in Fig. 6. From Table 1, it can be inferenced that system remains stable with minimal or no overshoot if it is operated under solution set: K1 [ [0.71 − 0.99] which corresponds to switching frequency mapped to set fsw [ [19.2 − 26.4] kHz. In this recommended region of operation K1 [ [0.71 − 0.99], the servo and regulatory dynamics of the closed-loop system remains stable. From Figs.

4a and b, it can be concluded that operating in vicinity of = 0.81 results in minimal trade-off between K1 Di &f sw optimal

switching loss and DiL . Furthermore, let it be noted that very highphase margin may lead to undesirable impact on overshoot, so any phase difference with ±10% deviation from optimal phase difference (77°) is acceptable [28]. 5

∂ = x11 x22 x33 − x11 x23 x32 − x12 x21 x33 + x12 x23 x31

ITAE =

3.44 3.72 × 10−05 s + s 0.000111 s + 1

Equation (22) presents parameters Kp , Ki , Kd ◦ C = 0.0412 +

L optimal

where

+ x13 x21 x32 − x13 x22 x31

presents inﬂuence of crossover frequency to step response of the control system. When an optimisation is used, a phase margin 77° is determinate and solved an optimisation task to ﬁnd optimum crossover frequency in (21) ITAE (vc ) must be minimum solution of this task as vc = 7.96 × 103 rad/s. Using crossover frequency obtained using optimisation task, the controller can be parameterised as

Experimental results

The experimental prototype of HCC IBC for PFC is implemented in laboratory environment as shown in Fig. 7. The experimental veriﬁcation deals with the analysis of theoretical aspects of the proposed optimal switching frequency applied to IBC. Parameters used to fabricate converter is given in Table 2. The Spartan 3AN FPGA processor is used to provide switching pulses to IBC, which offers ﬂexible implementation of HCC. This FPGA has a 12 bit analogue-to-digital converter which converts various analogue signals to digital signal. It also has enabled PWM driver channels, which can generate required PWM control signals to IBC. These channels can realise highresolution control signals in the range of 50 MHz switching frequency. To show the performance of the proposed optimal switching frequency HCC approach with conventional HCC, two approaches are implemented. Fig. 8a shows the experimental waveforms of input current (Iin) and input voltage (Vin) of IBC without HCC, the corresponding ZCD pulse generation with respect to phase angle of voltage and current is shown in lower trace. The experimental waveform of DC-link voltage, AC input voltage, phase a inductor current and AC input current is shown in Fig. 8b. Practically, in the aforementioned theory, the power can be generated in WECS with variable AC voltage and frequency. To show the performance of the

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J Eng 2017 doi: 10.1049/joe.2017.0241

Fig. 6 Frequency-domain analysis to investigate dynamic stability proposed scheme with K1 [ [0.71 − 0.99]

Table 1 Phase margin ranges for stable operation Value of K1 through optimisation 0.72 0.81 (optimal) 0.99

Phase margin, deg 55.35 77 97.07

Fig. 7 Photograph of laboratory experimental setup

Table 2 Experimental setup parameters Parameter input voltage output voltage rated power frequency inductance (L1 = L2 = L3) parasitic resistance of inductor capacitance (boost converter) parasitic resistance of capacitor operating switching frequency

Value 50 V 80 V 250 W 50 Hz 0.5 mH 0.23 Ω 100 µF 0.2 Ω 21.6 kHz

proposed HCC with optimal switching frequency for IBC to improve the power factor of WECS, the experimental results have been presented under steady-state operations. J Eng 2017 doi: 10.1049/joe.2017.0241

Fig. 8 Experimental results of IBC a Input current (Iin), input voltage (Vin) and corresponding ZCD of converter without HCC b DC-link voltage, input voltage, inductor current and input current with conventional HCC approach

The experimental waveforms for input current and each phase of IBC inductor currents operating in CCM and shifted in phase by 120° with just the previous phase are shown in Fig. 9a. Owing to optimal switching frequency approach in HCC, it clearly shows that the input ripple current is appreciably small. The magnitude of inductor current for every phase IBC is almost similar and summation of it produces ripple free input current. Fig. 9b depicts the waveforms of DC-link voltage, AC input voltage, phase a inductor current and AC input current waveforms. As it can be seen, the total currents of three-phase inductor currents are equal to the rectiﬁed DC current but with fewer ripples in the proposed optimal

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Fig. 9 Experimental results of IBC with the proposed approach a Three-phase inductor currents of IBC and input current b DC-link voltage, input voltage, inductor current and input current c Input voltage and current variation at dynamic load condition

switching frequency approach of HCC. From Fig. 8b, it can be seen that the magnitude of rectiﬁed DC current has more ripple and consequential rectiﬁcation losses in the conventional approach of HCC. This makes high switching loss, large input current ripple and poor power factor. Fig. 9c shows the experimental results of input voltage and the input current under dynamic behaviour, i.e. load resistance changes from 60 to 15 Ω. During the load variation in DC side, the load power approximately changes from 45 to 100 W. Under this condition, the phase angles between the input voltage and input current, as illustrated from Fig. 9c, are absolutely in phase and hence maintaining near unity power factor.

Power quality analyser is utilised to capture THD. To do this, light load condition is taken into consideration. The efﬁciency of the proposed system can be estimated after analysing the results of total losses appeared in power converter. To estimate the losses experimentally, loss breakdown analysis of the converter has been considered PL total = Psw + Pcond + PL + Pc

(24)

where Psw is the switching losses of the IBC. Pcond is the conduction losses of the power electric components. PL is the inductor

Fig. 10 Performance comparison of conventional and proposed controller a Measured power factor b Measured efﬁciency This is an open access article published by the IET under the Creative Commons Attribution-NonCommercial-NoDerivs License (http://creativecommons.org/ licenses/by-nc-nd/3.0/)

J Eng 2017 doi: 10.1049/joe.2017.0241

loss and Pc is the capacitor losses. Using (24), the total losses (PL total ) can be estimated. Fig. 10a shows the measured power factor of the conventional control technique and the proposed HCC technique in interleaved PFC boost converter. This shows the power factor of the proposed controller is signiﬁcantly higher than that of the conventional interleaved PFC boost rectiﬁer over the entire load range. Fig. 10b shows the measured power factor of the proposed approach. The power factor is 0.93 in light load condition and 0.99 during full load condition. Similarly, the measured efﬁciency is 91.3% in light load condition, whereas 98.8% is obtained during full load condition; this would certainly improve the efﬁciency of IBC. 6

Conclusion

This research articulates the optimal switching frequency of HCC for IBC with experimental prototype implementation and theoretical background veriﬁcation of the proposed robust self-tuning algorithm. The obtained experimental results conﬁrm power factor improvement of WECS is guaranteed with low switching loss, limited input current ripples and good efﬁciency. Furthermore, the system operates stable dynamically with wider range of switching frequency and optimality at 21.6 kHz is conﬁrmed. Experimental task in light load conditions, the power factor is maintained with 0.93 and efﬁciency leads to 91.3%, whereas in full load condition power factor is maintained at 0.99 and efﬁciency leads to 98.8%. Finally it is concluded with experimental investigation that IBC with adapting the proposed robust control approach HCC suits for DC microgrid applications. The ongoing work, to be communicated, is an attempt how to deal with online tuning of parameter K1, which will elaborate the related algorithm, challenges and practical value of such suggested methods. 7

Acknowledgment

This work was supported by the Board of Research in Nuclear Sciences (BRNS), Department of Atomic Energy Government of India under the grant no: 34/14/53/2014-BRNS. 8

References

[1] Kanaan H.Y., Sauriol G., Al-Haddad K.: ‘Small-signal modelling and linear control of a high efﬁciency dual boost single-phase power factor correction circuit’, IET Power Electron., 2009, 2, (6), pp. 665–674 [2] Wang Q., Chang L.: ‘An intelligent maximum power extraction algorithm for inverter-based variable speed wind turbine systems’, IEEE Trans. Power Electron., 2004, 19, (5), pp. 1242–1249 [3] Jovanovic M.M, Jang Y.: ‘State-of-the-art, single phase, active power-factor-correction techniques for high power applications – an overview’, IEEE Trans. Ind. Electron., 2005, 52, pp. 701–708 [4] Wang C.M., Lin C.H., Lu C.M., ET AL.: ‘Design and realization of a zero-voltage transition pulse-width modulation interleaved boost power factor correction converter’, IET Power Electron., 2015, 8, (8), pp. 1542–1551 [5] Meng T., Ben H., Zhu L., ET AL.: ‘Improved passive snubbers suitable for single-phase isolated full-bridge boost power factor correction converter’, IET Power Electron., 2014, 7, (2), pp. 279–288 [6] Narimani M., Moschopoulos G.: ‘A new interleaved three-phase single stage PFC AC–DC converter’, IEEE Trans. Ind. Electron., 2014, 61, (2), pp. 648–654 [7] Tamyurek B., Torrey D.A.: ‘A three-phase unity power factor single-stage ac–dc converter based on an interleaved ﬂyback topology’, IEEE Trans. Power Electron., 2011, 26, (1), pp. 308–318 [8] Garcia O., Zumel P., de Castro A., ET AL.: ‘Automotive DC–DC bidirectional converter made with many interleaved buck stages’, IEEE Trans. Power Electron., 2006, 21, (3), pp. 578–586 [9] Rocabert J., Luna A., Blaabjerg F., ET AL.: ‘Control of power converters in AC microgrid’, IEEE Trans. Power Electron., 2012, 27, (11), pp. 4734–4749 J Eng 2017 doi: 10.1049/joe.2017.0241

[10] Loh P.C., Li D., Chai Y.K, ET AL.: ‘Autonomous operation of hybrid micro-grid with AC and DC subgrids’, IEEE Trans. Power Electron., 2013, 28, (5), pp. 2214–2223 [11] Ahmed M.E.S., Orabi M., Abdelrahim O.M.: ‘Two-stage micro-grid inverter with high-voltage gain for photovoltaic applications’, IET Power Electron., 2013, 6, (9), pp. 1812–1821 [12] Xu X., Liu W., Huang A.Q.: ‘Two-phase interleaved critical mode PFC boost converter with closed loop interleaving strategy’, IEEE Trans. Power Electron., 2009, 24, (12), pp. 3003–3113 [13] Tsai J.R., Wu T.F., Wu C.Y., ET AL.: ‘Interleaving phase shifters for critical-mode boost PFC’, IEEE Trans. Power Electron., 2008, 23, (3), pp. 1348–1357 [14] Ku C.P., Chen D., Huang C.S., ET AL.: ‘A novel SFVM-M3 control scheme for interleaved CCM/DCM boundary-mode boost converter in PFC applications’, IEEE Trans. Power Electron., 2011, 26, (8), pp. 2295–2303 [15] Angjelichinoski M., Stefanovic C., Popovski P., ET AL.: ‘Power talk: how to modulate data over a DC micro grid bus using power electronics’. 2015 IEEE Global Communications Conf., San Diego, CA, 2015, pp. 1–7 [16] Selvamuthukumaran R., Gupta R.: ‘Rapid prototyping of power electronics converters for photovoltaic system application using Xilinx system generator’, IET Power Electron., 2014, 7, (9), pp. 2269–2278 [17] Kazimierczuk M.K.: ‘Pulse-width modulated DC–DC power converters’ (Wiley, Chichester, UK, 2008) [18] Suresh Y., Panda A.K., Suresh M.: ‘Real-time implementation of adaptive fuzzy hysteresis-band current control technique for shunt active power ﬁlters’, IET Power Electron., 2012, 5, (7), pp. 1188–1195 [19] Fangrui L., Maswood A.I.: ‘A novel variable hysteresis band current control of three-phase three-level unity PF rectiﬁer with constant switching frequency’, IEEE Trans. Power Electron., 2006, 21, (6), pp. 1727–1734 [20] Peña-Alzola R., Liserre M., Blaabjerg F., ET AL.: ‘A selfcommissioning notch ﬁlter for active damping in a three-phase LCL-ﬁlter-based grid-tie converter’, IEEE Trans. Power Electron., 2014, 29, (12), pp. 6754–6761 [21] Biricik S., Komurcugil H.: ‘Three-level hysteresis current control strategy for three-phase four-switch shunt active ﬁlters’, IET Power Electron., 2016, 9, (8), pp. 1732–1740 [22] Tamyurek B., Torrey D.A.: ‘A three-phase unity power factor single stage ac–dc converter based on an interleaved ﬂyback topology’, IEEE Trans. Power Electron., 2011, 26, (1), pp. 308–318 [23] Sun J., Mitchell D.M., Greuel M.F., ET AL.: ‘Averaged modeling of PWM converters operating in discontinuous conduction mode’, IEEE Trans. Power Electron., 2001, 16, (4), pp. 482–492 [24] Suntio T.: ‘Average and small-signal modeling of self-oscillating ﬂyback converter with applied switching delay’, IEEE Trans. Power Electron., 2006, 21, (2), pp. 479–486 [25] Wang L., Lam C.S., Wong M.C., ET AL.: ‘Non-linear adaptive hysteresis band pulse-width modulation control for hybrid active power ﬁlters to reduce switching loss’, IET Power Electron., 2015, 8, (11), pp. 2156–2167 [26] Ostos J.C., Lu D.D.C.: ‘Modeling and analysis of CCM non-isolated high step-up interleaved buck–boost dc/dc converters’. Int. Conf. Proc. IEEE Power and Energy Conf., IEEE-PECon’12, Kota Kinabalu, 2–5 December 2012, pp. 28–31 [27] Kondrath N., Kazimierczuk M.K.: ‘Uniﬁed model to derive control-to-output transfer function of peak current-mode-controlled pulse-width modulated dc–dc converters in continuous conduction mode’, IET Power Electron., 2012, 5, (9), pp. 1706–1713 [28] Andrikopoulos G., Nikolakopoulos G., Manesis S.: ‘Advanced nonlinear PID-based antagonistic control for pneumatic muscle actuators’, IEEE Trans. Ind. Electron., 2014, 61, (12), pp. 6926–6937 [29] Erickson R.W., Maksimovic D.: ‘Fundamentals of power electronics’ (Norwell Kluwer, MA, 2001, 2nd edn.)

9 Appendix. Analytical derivation of small signal model of interleaved non-ideal DC–DC boost converter The small signal state-space representation of IBC is derived in what follows. The linearised differential equations, using switched statespace technique through state-space averaged models of the

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conventional boost converter, for non-ideal ILBC, are deﬁned as follows [29]: ⎫ ⎪ ⎪ ˆ = Vin − ˆiLi (t)RLi − (1 − Di )ˆvo (t) + Vo d i (t) ⎪ Li ⎬ dt ∀i = [1, 3] dˆv (t) ⎪ ˆ − ˆi (t) ⎪ (1 − Di )ˆiLi (t) − ILi d(t) C C = ⎪ Load ⎭ dt dˆiLi (t)

i

i

state-space averaged model neglecting the second-order non-linear term in linearised AC model can be formulated as follows: ˆ xˆ˙ (t) = Aˆx(t) + Bˆu(t) + Bd d(t) i=6 where A = i=6 i=1, 3, 5 Ai X − i=1 Ai Di , B = i=1 Bi Di and Bd = j=2, 4, 6 Bi U and ⎡

⎡1⎤ ⎢ L1 ⎥ iL1 ⎢ ⎥ ⎢1⎥ ⎢i ⎥ ⎢ ⎥ ⎢ L2 ⎥ ⎥ xˆ (t) = ⎢ ⎥; Bi = ⎢ ⎢ L2 ⎥∀i = [16] ⎣ iL ⎦ ⎢1⎥ 3 ⎢ ⎥ ⎣L ⎦ Vo

⎤

⎡

˙iL ⎢˙ 1 ⎥ ⎢ iL2 ⎥ ⎥ xˆ˙ (t) = ⎢ ⎢ ˙i ⎥; ⎣ L3 ⎦ V˙ o

⎤

3

0 D1 = D3 = D5 = D; D1 + D3 + D5 + D2 + D4 + D6 = 1 Similarly, the matrices in states 2–6 can be of similar form in what follows: ⎡

−

RL L1

⎢ ⎢ ⎢ ⎢ ⎢ 0 ⎢ ⎢ A1 = ⎢ ⎢ ⎢ ⎢ 0 ⎢ ⎢ ⎢ ⎣ 0 ⎡

−

−

0

RL L2

0

−

0

0

R(Rc + RL ) + RL Rc L3 (R + Rc ) R C(R + Rc ) 0

⎥ ⎥ ⎥ ⎥ ⎥ 0 ⎥ ⎥ ⎥ ⎥ R ⎥ ⎥ − L3 (R + Rc ) ⎥ ⎥ ⎥ ⎦ 1 − C(R + Rc ) 0

R(Rc + RL ) + RL Rc L2 (R + Rc )

−

R(Rc + RL ) + RL Rc L2 (R + Rc )

−

R(Rc − RL ) − RL Rc L3 (R + Rc )

−

R(Rc − RL ) − RL Rc L3 (R + Rc )

R C(R + Rc ) 0 −

R(Rc + RL ) + RL Rc L2 (R + Rc ) 0 R C(R + Rc )

R C(R + Rc ) 0 0 −

RL L3

0

⎤ 0

−

RL L1

⎢ ⎢ ⎢ ⎢ ⎢ 0 ⎢ ⎢ A3 = ⎢ ⎢ ⎢ ⎢ 0 ⎢ ⎢ ⎢ ⎣ 0

−

0

RL L1

⎢ ⎢ ⎢ ⎢ ⎢ 0 ⎢ ⎢ A2 = ⎢ ⎢ ⎢ ⎢ 0 ⎢ ⎢ ⎢ ⎣ 0 ⎡

⎤ 0

⎤

⎥ ⎥ ⎥ ⎥ R ⎥ − L2 (R + Rc ) ⎥ ⎥ ⎥ ⎥ R ⎥ ⎥ − L3 (R + Rc ) ⎥ ⎥ ⎥ ⎦ 1 − C(R + Rc )

0

⎥ ⎥ ⎥ ⎥ R ⎥ − L2 (R + Rc ) ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ 0 ⎥ ⎥ ⎥ ⎦ 1 − C(R + Rc )

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J Eng 2017 doi: 10.1049/joe.2017.0241

⎡

R(Rc + RL ) + RL Rc ⎢− L1 (R + Rc ) ⎢ ⎢ ⎢ R(R + R ) + R R c L L c ⎢− ⎢ L2 (R + Rc ) ⎢ A4 = ⎢ ⎢ ⎢ 0 ⎢ ⎢ ⎢ ⎢ ⎣ R C(R + Rc ) ⎡ R(R + R ) + R R c L L c − ⎢ L1 (R + Rc ) ⎢ ⎢ ⎢ ⎢ 0 ⎢ ⎢ A5 = ⎢ ⎢ ⎢ 0 ⎢ ⎢ ⎢ ⎣ R ⎡

C(R + Rc )

R(Rc + RL ) + RL Rc ⎢− L1 (R + Rc ) ⎢ ⎢ ⎢ ⎢ 0 ⎢ ⎢ A6 = ⎢ ⎢ R(R + R ) + R R ⎢ c L L c ⎢− ⎢ L3 (R + Rc ) ⎢ ⎢ ⎣ R C(R + Rc )

−

R(Rc + RL ) + RL Rc L1 (R + Rc )

0

−

R(Rc + RL ) + RL Rc L2 (R + Rc )

0 −

0 R C(R + Rc )

⎤ R L1 (R + Rc ) ⎥ ⎥ ⎥ ⎥ R ⎥ − ⎥ L2 (R + Rc ) ⎥ ⎥ ⎥ ⎥ 0 ⎥ ⎥ ⎥ ⎥ ⎦ 1 − C(R + Rc ) −

RL L3

0 ⎤

0

0

0

RL L2

0

0

RL L3

0

−

0 0 0 −

−

−

0

R(Rc + RL ) + RL Rc − L1 (R + Rc )

RL L2

0 0

1 C(R + Rc )

⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦

0 −

R(Rc + RL ) + RL Rc L3 (R + Rc ) R C(R + Rc )

⎤ R − L1 (R + Rc ) ⎥ ⎥ ⎥ ⎥ ⎥ 0 ⎥ ⎥ ⎥ ⎥ R ⎥ − ⎥ L3 (R + Rc ) ⎥ ⎥ ⎥ ⎦ 1 − C(R + Rc )

The control to output transfer function of the IBC is designed and derived as

vˆ o (t) = (sIn − A)−1 Bd n=4 ˆd

J Eng 2017 doi: 10.1049/joe.2017.0241

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Department of Electrical Engineering, M.N. National Institute of Technology, Allahabad, India Smart Energy Division NEC Laboratories Singapore, NEC Asia Paciﬁc Pte Ltd., Singapore, Singapore 3 Faculty of Engineering, The University of Nottingham Malaysia Campus, Semenyih 43500, Malaysia 4 Department of Electronics & Communication Engineering, M.N. National Institute of Technology, Allahabad, India 5 Department of Electrical Engineering, SSN College of Engineering, Chennai, India E-mail: [email protected] 2

Published in The Journal of Engineering; Received on 9th June 2017; Accepted on 28th June 2017

Abstract: This study exploited the hysteresis current control (HCC) with optimal switching frequency for interleaved boost converter to improve the power factor of wind energy conversion system (WECS) exclusively for DC microgrid applications. By fact that output power from WECS is variable due to unpredictable wind speed, where the HCC suffers with range of switching frequency, high switching loss, large input current ripple and poor power factor. To overcome the aforementioned problem, an automatic tuning procedure has been developed for proportional–integral–derivative (PID) voltage regulator to achieve optimal feedback gain of ﬁlter inductor current and thereby optimal switching frequency is maintained with good power factor, low harmonic distortion and improved efﬁciency. Additionally, the robust PID voltage regulator guarantees the stability and investigated through bode plots. Hardware prototype model is implemented in the laboratory standards with Spartan 3AN ﬁeld programmable gate array control board. The experimental results obtained are conﬁrming the theoretical background aspects of the operating regimes.

1

Introduction

Predominant requirement in any AC/DC power conversion stages requires good power factor correction (PFC) both in light/heavy and or dynamically varying loads with high quality, high efﬁciency and operable reliability [1]. In particular, for clean energy generation systems, wind energy conversion system (WECS) plays vital role, where permanent magnet synchronous generator is used as prime mover in application, i.e. the diode bridge rectiﬁer is connected across wind turbine to convert generated AC power into unidirectional DC power [2]. Method results in low cost, simple structure, robustness and absence of complex controls but the complete system suffers with poor input power factor by the injected lower-order harmonics to AC system. Results of the line voltage with harmonic components, equipment overheating, malfunction and deteriorate the total quality of system [3]. Many works articulate to improve the input power factor and to reduce current harmonics includes passive or active PFC techniques [4]. Renowned being PFC techniques by employing classical topologies such as boost, buck–boost- and buck-converters [5]. However, among these topologies, interleaved boost converter (IBC) is preferred for high-power application. In particular WECS, it offers high efﬁciency, improved power factor, lower harmonic distortion and reduced voltage stress across the switches [6, 7]. Higher switching frequency operated IBC provides PFC and exhibits the following merits: † Cascaded of multiple smaller units shares equally the demanded power, which reduces the size of the inductor, rating of the switch and diodes. Moreover, the reliability and cost aspects of the system get improved thereby. † Interleaved PFC converter operates at u = 360◦ /N and uN − uN−1 = 360/N ∀N [ [2N ], where N denotes the number of cells connected in parallel/series depends on current/voltage demands. Consequently, the current/voltage rating of the switches gets minimised. J Eng 2017 doi: 10.1049/joe.2017.0241

† IBC operates at higher switching frequency with ﬂexible in control and dynamically stable. † Higher operating frequency results in reduced ripple factor which in effect eliminate the needs of auxiliary ﬁlter circuitry, and thereby reduced overall cost. Such features make high switching frequency-controlled IBC topology extensively popular for high-power applications [8–13]. The DC–DC converters are operated normally in three modes, namely (a) continuous conduction mode (CCM), (b) discontinuous CM (DCM) and (c) critical conduction mode or transition mode control. Usually, converter will operate either in CCM or DCM and CCM is suitable for high-power applications, whereas DCM and critical conduction mode are suitable for low-/medium-power applications [14]. By literatures, different strategies to limit switching losses such as: appropriate design of inductor and capacitor, effect of interleaved boost stage, replacement of semiconductor switches, average current mode control and the hysteresis control [15–17]. Hysteresis comparators are the most popular control techniques, ensured by robustness and simple control strategy for easy implementation [18]. However, its switching frequency varies greatly during dynamic operating conditions [19] and several attempts are carried out to attain constant switching frequency while adopting hysteresis current control (HCC) [20, 21]. However, no inclusive articles focused on HCC application to IBC. Hence, this research work exploits the adoption of HCC to rectiﬁed DC current in IBC with ﬁxed hysteresis band which when used with an optimal linear proportional–integral–derivative (PID) controller leads to the following advantages: † Unity power factor. † Lower total harmonic distortion (THD). † Lesser ripple current. † Better stability in under dynamic load changes reinforced with simplicity and robustness.

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This paper proposed an automatic tuning algorithm and to demonstrate the optimal value of the feedback gain of ﬁlter inductor current is achieved, thereby optimal switching frequency and hence ensured minimal trade-off between switching power losses and current ripple. Furthermore, the design of robust PID voltage regulator which explicitly guarantees the dynamic stability is proposed in this investigation for set power system. Set of experimental results are provided in this paper to verify the theoretical background of the proposed control scheme. This paper is organised as follows: Section 2 deals with architecture of the complete power system conﬁguration. The proposed control algorithm ‘HCC to rectiﬁed DC in IBC-based PFC in WECS’ with its systematic structure has been given a lucid and elaborated in Section 2.1. Section 3 deals brieﬂy with small signal modelling of IBC and its use in switching frequency estimation for the optimal boundary region operation of IBC. Furthermore, in the same Section 3 robust PID voltage regulator is designed for the guaranteed dynamic stability of proposed scheme. Section 4 explicitly deals with overall stability analysis. Performance evaluation of the proposed control algorithm is validated with Spartan 3AN ﬁeld programmable gate array (FPGA) implementation in Section 5. Finally, the concluding remark is given in Section 6. 2

Detailed architecture system conﬁguration

The proposed control architecture of HCC technique for DC microgrid application is described in detail in Fig. 1, being constituted by: (a) micro wind turbine, (b) IBC unit reinforced with PFC, (c) PF measurement unit and (d) Spartan 3AN FPGA processor featured with reference current generation and voltage control loop. In detail, three-phase IBC operates in CCM and to maintain unity power factor with boost converter operates 120° phase difference [22]. The sensors are employed to measure the output voltage and current of WECS, and its current signal corresponding in voltage values is utilised for phase angle generation required to achieve unity power factor using zero crossing detector (ZCD)

[23, 24]. Power factor measurement unit is operated as follows: transistor is driven by square wave signal obtained through ZCD and produces 5 V signal either with respect to voltage or current signal. In general, for 50 Hz frequency, the transistor output signal period would be 20 ms and the transistor output pulse time period is similar to that of current waveform. If there occurs to be any phase difference between input voltage and current, exclusive or (X-OR) gate generates a pulse according to the phase delay of voltage and current. For the modulation of IBC, switching pulses shifted in phase by 120° with each other are generated by control logic consisting of voltage and current control loop implemented on FPGA. 2.1 Novel PFC approach: HCC technique to rectiﬁer DC current Fig. 2 shows schematic representation of the proposed PFC algorithm consisting of ZCD, phase locked loop (PLL) and angle to delay generator, i.e. HCC technique to rectiﬁed DC current for maintaining good PF. Furthermore, PLL is essential for combination of transistor drivers and X-OR logic gates. If there happens to be any phase angle mismatch between voltage and current, the PLL will generate a signal corresponding to the phase angle. Voltage and current sensing units are used to estimate the power generated (Pin) by wind energy system. Furthermore, frequency estimation through ZCD leads to calculation of respective time period which is required to generate reference rectiﬁed DC current. Use of enable/disable facilitated trigger control mechanism buffer logic allows the reference rectiﬁed DC current to rise at the instant when the voltage starts rising, to ensure unity PF. In case if PF is not unity, then the power generated from WECS is not delivered completely to DC bus. This demands the generation of reference rectiﬁed DC current according to voltage errors. The combined reference rectiﬁed DC current is compared with actual DC current. Moreover, the measurement of actual DC current does not involve any dedicated sensor, rather is obtained by the rectiﬁcation of AC input current.

Fig. 1 Detailed control structure of the proposed HCC method applied to IBC This is an open access article published by the IET under the Creative Commons Attribution-NonCommercial-NoDerivs License (http://creativecommons.org/ licenses/by-nc-nd/3.0/)

J Eng 2017 doi: 10.1049/joe.2017.0241

Fig. 2 Proposed HCC block diagram

Finally, the actual rectiﬁed DC current is controlled by optimally tuned hysteresis loop current controller to achieve the desired reference current with unity PF. When wind energy output power changes due to wind velocity, the generated reference current signal inevitably becomes variable and not just poses requirement of variable duty cycle but variable switching control structure as well. Therefore, variable K1, the feedback coefﬁcient of ﬁlter inductor current, is investigated as potential solution to achieve the variable frequency control structure with ﬁxed hysteresis band 2h. An excellent automatic tuning procedure has been developed to achieve optimal solution of K1 with switching loss and inductor current ripple as two optimisation variable. Procedure, design goals and solution of optimisation task has been extensively elaborated later in Section 3. Furthermore, a robust PID controller is designed for excellent regulation of DC-link voltage as per the reference voltage for suggested solution set K1 and hence fsw . The design procedure will be elaborated later in the text. 3 Switching frequency formulation and small signal modelling This section deals with formulation of analytical expression for maximum, minimum and average switching frequency applies to IBC. The following sets of assumption are made:

where ˆiLi is the inductor current variation, vˆ o (t) is the output voltage variation, Di is the nominal duty cycle, dˆ i is the duty cycle variation, RLi is the parasitic resistance of the inductor and Vin is the input voltage in nominal state. Inductor current dynamics for the IBC constituted by three parallel boost converter cells can be written as LDiL = Vin − ˆiLi (t)RLi − (1 − Di )ˆvo (t) + Vo dˆ i (t) D − 1/3 T

(2)

Simplifying (2) and replacing Vin = Vo (1 − D) leads to the following relation: DiL =

Vin − ˆiLi (t)RLi − (1 − Di )ˆvo (t) + Vo dˆ i (t) D − 1/3 T L (3)

The typical expression for instantaneous switching frequency, in IBC can be written as (4), without loss of generality and presumption that D denotes nominal duty cycle fsw

ˆ Vin − ˆiL (t)RL − (1 − D)ˆvo (t) + Vo d(t) (3D − 1) = 3LDiL

(4)

† All the switches, inductors, capacitors and diodes are ideal. † The output voltage (Vo) is larger than input voltage (Vin). † Three-stage boost converter inductors are equal (i.e. L1 = L2 = L3 = L).

The average value of the inductor is absolutely governed by reference current and average current can be constructed as

The linearised state-space differential equations for the IBC circuit as shown in Fig. 1 can be formulated as

where K1 is the servo coefﬁcient of ﬁlter inductor current, as the magnitude of inductor current ripple is strongly related to hysteresis band, so DiL = 2h/K1 [25] instantaneous switching frequency can now be parameterised as

⎫ ⎪ ⎪ = Vin − ˆiLi (t)RLi − (1 − Di )ˆvo (t) + Vo dˆ i (t) ⎪ ⎬ dt ∀i dˆv (t) ⎪ ˆ − ˆi (t) ⎪ ⎪ (1 − Di )ˆiLi (t) − ILi d(t) C C = ⎭ Load dt i i

Li

dˆiLi (t)

= [1, 3] J Eng 2017 doi: 10.1049/joe.2017.0241

iL =

fsw (1)

iref K1

ˆ (3D − 1) Vin − ˆiL (t)RL − (1 − D)ˆvo (t) + vo d(t) = 6Lh′

(5)

where h′ = h/K1 .

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The general trade-off between the inductor current ripple and switching loss demands the constraints on switching frequency bounds for efﬁcient modulation of switching converter. In HCC, the variable hysteresis band leads to variable switching frequency system and resulting higher switching loss or current ripple. The present work deals with a new approach toward optimal modulation of IBC under variable frequency control structure. Instead to vary hysteresis band, the variable servo (feedback) coefﬁcient of ﬁlter inductor current (K1) can provide an alternate solution to the variable frequency control under constant hysteresis band (2h). The procedural details are described in what follows.

switching frequency went beyond bound region, it will induce high switching loss, poor efﬁciency, high ripple and cause ageing effect to the system. Hence, an auto-tuning procedure needs to be developed such that the operating frequency lies within the neighbourhood of the optimal fsw. The optimal tuning of K1 helps to ﬁnd neighbourhood of the optimal switching frequency fsw and also satisﬁes the constraint on the current ripple h′ =

0.25 × Po Vo

(6)

3.2 Parameterisation of voltage regulator (PID) for given phase margin

3.1 Optimal switching frequency formulation Owing to the variable and stochastic nature of the wind speeds, output frequency ﬂuctuates with respect to the desired nominal frequency of 50 Hz. This will cause the duration over a cycle of rectiﬁed DC current in WECS to vary and as the consequence of which the reference current in this duration is in synchronism with input voltage to achieve unity power factor in the proposed control scheme. To ensure that the system operates at/around optimal switching frequency (with a tolerance limit of ±15%), it is necessary that optimal value of the parameter K1 should be considered so as to ensure proper trade-off between switching power losses and current ripple. When an optimisation task is carried out in search of optimal determination of K1, the search algorithm furnishes a distinct value of K1 at the end of search as shown in Fig. 3. The different values of K1 and its corresponding switching loss and inductor current ripple is shown in Fig. 4a. In the presented work with the assumption that inductor current ripple comes up DiL [ [0.5 − 0.7]A, the optimisation search algorithm

with solution set: K1 [ [0.71 − 0.99] and K1 Di = &f L optimal

The interleaved switching DC–DC boost converter exhibits nonminimum phase behaviour due to the inherent existence of an zero-right half plane zero (RHP) zero when it is operated under CCM and voltage control mode. To control output transfer function of the interleaved pulse-width modulation (PWM) DC–DC switching converter, the RHP zero is present as: 1 − ts, where t = Leq /R(1 − D)2 . The inherent time delay due to RHP zero of the boost converter can be expanded using Pade’s approximation (ﬁrst order) [26] e−ts =

(7)

Using general notation, the uncompensated system can be represented as follows: Guncomp =

sw optimal

0.81 as an optimal solution for K1. The switching frequency range investigated by optimisation task, shown in Fig. 4b, is fsw [ [19.2 − 26.4] kHz with an optimal switching frequency fsw = 21.6 kHz. As per theoretical calculation using (5), the maximum and minimum switching frequencies of the converter considered to be bound in the region of fsw [ [13.33 − 40.132] kHz for efﬁcient operation. If HCC operates in the

H(s) I(s)

P˜ (s) −ts P˜ (s) H (s) P(s) = †e = † ˜ (s) ˜ (s) I (s) Q(s) Q Q

(8)

Moreover, the time delay element can be taken in feedback loop (sensor delay) or in feed-forward loop (actuator delay), the frequency response and hence the conclusion for the stability ˜ (s) remains still true. Here in the presented study, the term Q included the time delay element arising due to the digital

Fig. 3 Flowchart description of optimal search algorithm This is an open access article published by the IET under the Creative Commons Attribution-NonCommercial-NoDerivs License (http://creativecommons.org/ licenses/by-nc-nd/3.0/)

J Eng 2017 doi: 10.1049/joe.2017.0241

The PID regulator is designed as per the procedure outlined in [27]. The complex form of the open-loop transfer function of the compensated system is Gcomp = C(jv)Guncomp (jv) Gcomp =

v2 Po Kp − Ki Pe + v2 Kd Pe (vKp Pe + vPo Ki − v3 Kd P) −j 2 v Qo − jvQe v2 Qo − jvQe (12)

As mentioned in [28], the discernment/determination of the margin of stability and in turn assurance of a robust controller design, through the desired phase margin, certain conditions can be inferenced a ReGcomp jvc = − cos (sm ) b ImGcomp jvc = − sin sm d Re Gcomp jvc =0 c dvc Fig. 4 Optimal switching frequency location trade-off analysis and recommended region of operation

implementation of controller (delay introduced in transmitting the controller’s output). The Taylor series expansion was used for approximating the timed delay term e−td s , as shown in Fig. 5, and ˜ (s) in denominator of (8). thus resulting in equivalent Q The PID controller in parallel form can be represented by C = Kp +

Ki + Kd †s s

where sm is the preset phase stability, vc is the crossover frequency obtained using optimisation, ReGcomp is the real part of compensated system, ImGcomp is the imaginary part of compensated system and dRe Gcomp jvc /dvc = 0 is the derivative of real part taken with respect to frequency. Substituting (12) into the above system of conditions, a set of explicitly deﬁned algebraic equations are formulated with the objective of achieving the desired PID controller gains

(9) Kp x11 + Ki x12 + Kd x13 = y1 Kp x21 + Ki x22 + Kd x23 = y2

where symbols used in (9) have usual meaning. On substituting s = jv the frequency-domain representation of uncompensated system and PID controller is given as [27] Guncomp (s) =

P(s) P (v ) + jv Po (v ) = e Q(s) Qe (v) + jvQo (v)

K C = Kp + i + Kd †jv jv

(13)

(10)

(14)

Kp x31 + Ki x32 + Kd x33 = 0

Solving (14), the equivalent coefﬁcients can be expressed as

(11)

x11 = v4 Po Qo + v2 Po Qe x12 = v2 Po De + v2 Ne Do

where Pe and Po are even and odd parts of P(s) [the numerator in (8)]. Similar deﬁnition holds for denominator Q(s) of (10).

(15)

x13 = v4 Pe Qo + v4 Po Qe

Fig. 5 Controller structure for stability analysis in parlance of linear system theory J Eng 2017 doi: 10.1049/joe.2017.0241

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x21 = v3 Po Qe + v3 Pe Qo x22 = −vPe Qe + v3 Po Do

(16)

x23 = v3 Pe Qe + v5 Po Qo

x31

⎛ ′ ′ Po Q2e Qo + Po Q2e Qo ′ ⎜ ′ ′ ′ 2 2 = v8 Po Q3o − Po Qo Q2o + v6 ⎜ ⎝ +Pe Qe Qo + Pe Qe Qo ′

⎞

′

⎟ ⎟ ⎠

−2Po Qe Qe Qo − 2Pe Qe Qo Qo

x32

x33

+ v5 2Po Q2e Qo − 2Pe Qe Q2o ′ ′ + v4 Pe Q3e − Pe Qe Q2e ′ ′ ′ ′ ′ = v6 Po Qe Q2o − Pe Q3o + Pe Qo Q2o + Po Qe Q2o − 2Po Qe Qo Qo (17) + v5 2Pe Q3o − 2Po Qe Q2o ′ ′ Po Q3e − Pe Q2e Qo − + v4 ′ ′ ′ Pe Q2e Qo + 2Pe Qe Qe Qo − Po Qe Q2e ′ ′ ′ ′ = v8 Pe Q3o − Pe Qo Q2o − Po Qe Q2o + 2Po Qe Qo Qo ′ ′ 2 2 ′ 3 6 Pe Qe Qo + Pe Qe Qo − Po Qe +v ′ ′ +Po Qe Q2e − 2Pe Qe Qe Qo + v5 2Pe Q2e Qo − 2Po Q3e y1 = − cos s v2 Q2e + v4 Q2o y2 = − sin s v2 Q2e + v4 Q2o

(18)

Po (s), Qo (s) are derivatives with respect to the frequency. Using the obtained equivalent coefﬁcients from the aforementioned set of well-deﬁned equations, Kp , Ki and Kd in terms of frequency ω

x x y + x22 x33 y1 − x12 x33 y2 − x23 x32 y1 Kp vc = 13 32 2 ∂ x11 x33 y2 − x13 x31 y2 − x21 x32 y1 − x22 x31 y1 Ki vc = ∂ x12 x31 y2 − x11 x32 y2 + x21 x32 y1 − x22 x31 y1 Kd vc = ∂

(19)

(20)

The parameterisation of PID is mono-variable system in v. Estimation of crossover frequency leads to explicit formulation of PID controller with desired phase margin. To achieve the PID controller gains, the crossover frequency has to be speciﬁed. As mentioned in [28], with higher gain crossover frequency system tends to exhibit more oscillatory nature as the transient time decreases, thereby reducing the transient nature of the process response. Using the integral of time-weighted absolute error (ITAE) minimisation, the optimal crossover frequency can be obtained 1

te(t )dt

77 , 7.96×103

(21)

0

So, from (19) it can be seen that each parameterisation of controller depends on phase margin and gain crossover frequency. Fig. 5

(22) . So,

optimisation is just one way to ﬁnd optimum crossover frequency and/or phase margin. However, can be calculated manually too. 4

Dynamic stability of the proposed controller

A phase margin of more than or close to 76° is required for guaranteed absence of overshoot in output voltage [29]. The small signal model of IBC is derived as follows using the state-space averaging techniques analytically derived for ILBC, in the Appendix: vˆ o = 1.135 dˆ × 103

(1 + 8.116 × 10−6 s)(1 − 1.316 × 10−4 s) 1.212 × 10−6 s2 + 2.203 × 10−4 s

(23)

Fig. 5 shows the block diagram of closed-loop compensator structure and their frequency-domain stability response is depicted in Fig. 6. From Table 1, it can be inferenced that system remains stable with minimal or no overshoot if it is operated under solution set: K1 [ [0.71 − 0.99] which corresponds to switching frequency mapped to set fsw [ [19.2 − 26.4] kHz. In this recommended region of operation K1 [ [0.71 − 0.99], the servo and regulatory dynamics of the closed-loop system remains stable. From Figs.

4a and b, it can be concluded that operating in vicinity of = 0.81 results in minimal trade-off between K1 Di &f sw optimal

switching loss and DiL . Furthermore, let it be noted that very highphase margin may lead to undesirable impact on overshoot, so any phase difference with ±10% deviation from optimal phase difference (77°) is acceptable [28]. 5

∂ = x11 x22 x33 − x11 x23 x32 − x12 x21 x33 + x12 x23 x31

ITAE =

3.44 3.72 × 10−05 s + s 0.000111 s + 1

Equation (22) presents parameters Kp , Ki , Kd ◦ C = 0.0412 +

L optimal

where

+ x13 x21 x32 − x13 x22 x31

presents inﬂuence of crossover frequency to step response of the control system. When an optimisation is used, a phase margin 77° is determinate and solved an optimisation task to ﬁnd optimum crossover frequency in (21) ITAE (vc ) must be minimum solution of this task as vc = 7.96 × 103 rad/s. Using crossover frequency obtained using optimisation task, the controller can be parameterised as

Experimental results

The experimental prototype of HCC IBC for PFC is implemented in laboratory environment as shown in Fig. 7. The experimental veriﬁcation deals with the analysis of theoretical aspects of the proposed optimal switching frequency applied to IBC. Parameters used to fabricate converter is given in Table 2. The Spartan 3AN FPGA processor is used to provide switching pulses to IBC, which offers ﬂexible implementation of HCC. This FPGA has a 12 bit analogue-to-digital converter which converts various analogue signals to digital signal. It also has enabled PWM driver channels, which can generate required PWM control signals to IBC. These channels can realise highresolution control signals in the range of 50 MHz switching frequency. To show the performance of the proposed optimal switching frequency HCC approach with conventional HCC, two approaches are implemented. Fig. 8a shows the experimental waveforms of input current (Iin) and input voltage (Vin) of IBC without HCC, the corresponding ZCD pulse generation with respect to phase angle of voltage and current is shown in lower trace. The experimental waveform of DC-link voltage, AC input voltage, phase a inductor current and AC input current is shown in Fig. 8b. Practically, in the aforementioned theory, the power can be generated in WECS with variable AC voltage and frequency. To show the performance of the

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Fig. 6 Frequency-domain analysis to investigate dynamic stability proposed scheme with K1 [ [0.71 − 0.99]

Table 1 Phase margin ranges for stable operation Value of K1 through optimisation 0.72 0.81 (optimal) 0.99

Phase margin, deg 55.35 77 97.07

Fig. 7 Photograph of laboratory experimental setup

Table 2 Experimental setup parameters Parameter input voltage output voltage rated power frequency inductance (L1 = L2 = L3) parasitic resistance of inductor capacitance (boost converter) parasitic resistance of capacitor operating switching frequency

Value 50 V 80 V 250 W 50 Hz 0.5 mH 0.23 Ω 100 µF 0.2 Ω 21.6 kHz

proposed HCC with optimal switching frequency for IBC to improve the power factor of WECS, the experimental results have been presented under steady-state operations. J Eng 2017 doi: 10.1049/joe.2017.0241

Fig. 8 Experimental results of IBC a Input current (Iin), input voltage (Vin) and corresponding ZCD of converter without HCC b DC-link voltage, input voltage, inductor current and input current with conventional HCC approach

The experimental waveforms for input current and each phase of IBC inductor currents operating in CCM and shifted in phase by 120° with just the previous phase are shown in Fig. 9a. Owing to optimal switching frequency approach in HCC, it clearly shows that the input ripple current is appreciably small. The magnitude of inductor current for every phase IBC is almost similar and summation of it produces ripple free input current. Fig. 9b depicts the waveforms of DC-link voltage, AC input voltage, phase a inductor current and AC input current waveforms. As it can be seen, the total currents of three-phase inductor currents are equal to the rectiﬁed DC current but with fewer ripples in the proposed optimal

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Fig. 9 Experimental results of IBC with the proposed approach a Three-phase inductor currents of IBC and input current b DC-link voltage, input voltage, inductor current and input current c Input voltage and current variation at dynamic load condition

switching frequency approach of HCC. From Fig. 8b, it can be seen that the magnitude of rectiﬁed DC current has more ripple and consequential rectiﬁcation losses in the conventional approach of HCC. This makes high switching loss, large input current ripple and poor power factor. Fig. 9c shows the experimental results of input voltage and the input current under dynamic behaviour, i.e. load resistance changes from 60 to 15 Ω. During the load variation in DC side, the load power approximately changes from 45 to 100 W. Under this condition, the phase angles between the input voltage and input current, as illustrated from Fig. 9c, are absolutely in phase and hence maintaining near unity power factor.

Power quality analyser is utilised to capture THD. To do this, light load condition is taken into consideration. The efﬁciency of the proposed system can be estimated after analysing the results of total losses appeared in power converter. To estimate the losses experimentally, loss breakdown analysis of the converter has been considered PL total = Psw + Pcond + PL + Pc

(24)

where Psw is the switching losses of the IBC. Pcond is the conduction losses of the power electric components. PL is the inductor

Fig. 10 Performance comparison of conventional and proposed controller a Measured power factor b Measured efﬁciency This is an open access article published by the IET under the Creative Commons Attribution-NonCommercial-NoDerivs License (http://creativecommons.org/ licenses/by-nc-nd/3.0/)

J Eng 2017 doi: 10.1049/joe.2017.0241

loss and Pc is the capacitor losses. Using (24), the total losses (PL total ) can be estimated. Fig. 10a shows the measured power factor of the conventional control technique and the proposed HCC technique in interleaved PFC boost converter. This shows the power factor of the proposed controller is signiﬁcantly higher than that of the conventional interleaved PFC boost rectiﬁer over the entire load range. Fig. 10b shows the measured power factor of the proposed approach. The power factor is 0.93 in light load condition and 0.99 during full load condition. Similarly, the measured efﬁciency is 91.3% in light load condition, whereas 98.8% is obtained during full load condition; this would certainly improve the efﬁciency of IBC. 6

Conclusion

This research articulates the optimal switching frequency of HCC for IBC with experimental prototype implementation and theoretical background veriﬁcation of the proposed robust self-tuning algorithm. The obtained experimental results conﬁrm power factor improvement of WECS is guaranteed with low switching loss, limited input current ripples and good efﬁciency. Furthermore, the system operates stable dynamically with wider range of switching frequency and optimality at 21.6 kHz is conﬁrmed. Experimental task in light load conditions, the power factor is maintained with 0.93 and efﬁciency leads to 91.3%, whereas in full load condition power factor is maintained at 0.99 and efﬁciency leads to 98.8%. Finally it is concluded with experimental investigation that IBC with adapting the proposed robust control approach HCC suits for DC microgrid applications. The ongoing work, to be communicated, is an attempt how to deal with online tuning of parameter K1, which will elaborate the related algorithm, challenges and practical value of such suggested methods. 7

Acknowledgment

This work was supported by the Board of Research in Nuclear Sciences (BRNS), Department of Atomic Energy Government of India under the grant no: 34/14/53/2014-BRNS. 8

References

[1] Kanaan H.Y., Sauriol G., Al-Haddad K.: ‘Small-signal modelling and linear control of a high efﬁciency dual boost single-phase power factor correction circuit’, IET Power Electron., 2009, 2, (6), pp. 665–674 [2] Wang Q., Chang L.: ‘An intelligent maximum power extraction algorithm for inverter-based variable speed wind turbine systems’, IEEE Trans. Power Electron., 2004, 19, (5), pp. 1242–1249 [3] Jovanovic M.M, Jang Y.: ‘State-of-the-art, single phase, active power-factor-correction techniques for high power applications – an overview’, IEEE Trans. Ind. Electron., 2005, 52, pp. 701–708 [4] Wang C.M., Lin C.H., Lu C.M., ET AL.: ‘Design and realization of a zero-voltage transition pulse-width modulation interleaved boost power factor correction converter’, IET Power Electron., 2015, 8, (8), pp. 1542–1551 [5] Meng T., Ben H., Zhu L., ET AL.: ‘Improved passive snubbers suitable for single-phase isolated full-bridge boost power factor correction converter’, IET Power Electron., 2014, 7, (2), pp. 279–288 [6] Narimani M., Moschopoulos G.: ‘A new interleaved three-phase single stage PFC AC–DC converter’, IEEE Trans. Ind. Electron., 2014, 61, (2), pp. 648–654 [7] Tamyurek B., Torrey D.A.: ‘A three-phase unity power factor single-stage ac–dc converter based on an interleaved ﬂyback topology’, IEEE Trans. Power Electron., 2011, 26, (1), pp. 308–318 [8] Garcia O., Zumel P., de Castro A., ET AL.: ‘Automotive DC–DC bidirectional converter made with many interleaved buck stages’, IEEE Trans. Power Electron., 2006, 21, (3), pp. 578–586 [9] Rocabert J., Luna A., Blaabjerg F., ET AL.: ‘Control of power converters in AC microgrid’, IEEE Trans. Power Electron., 2012, 27, (11), pp. 4734–4749 J Eng 2017 doi: 10.1049/joe.2017.0241

[10] Loh P.C., Li D., Chai Y.K, ET AL.: ‘Autonomous operation of hybrid micro-grid with AC and DC subgrids’, IEEE Trans. Power Electron., 2013, 28, (5), pp. 2214–2223 [11] Ahmed M.E.S., Orabi M., Abdelrahim O.M.: ‘Two-stage micro-grid inverter with high-voltage gain for photovoltaic applications’, IET Power Electron., 2013, 6, (9), pp. 1812–1821 [12] Xu X., Liu W., Huang A.Q.: ‘Two-phase interleaved critical mode PFC boost converter with closed loop interleaving strategy’, IEEE Trans. Power Electron., 2009, 24, (12), pp. 3003–3113 [13] Tsai J.R., Wu T.F., Wu C.Y., ET AL.: ‘Interleaving phase shifters for critical-mode boost PFC’, IEEE Trans. Power Electron., 2008, 23, (3), pp. 1348–1357 [14] Ku C.P., Chen D., Huang C.S., ET AL.: ‘A novel SFVM-M3 control scheme for interleaved CCM/DCM boundary-mode boost converter in PFC applications’, IEEE Trans. Power Electron., 2011, 26, (8), pp. 2295–2303 [15] Angjelichinoski M., Stefanovic C., Popovski P., ET AL.: ‘Power talk: how to modulate data over a DC micro grid bus using power electronics’. 2015 IEEE Global Communications Conf., San Diego, CA, 2015, pp. 1–7 [16] Selvamuthukumaran R., Gupta R.: ‘Rapid prototyping of power electronics converters for photovoltaic system application using Xilinx system generator’, IET Power Electron., 2014, 7, (9), pp. 2269–2278 [17] Kazimierczuk M.K.: ‘Pulse-width modulated DC–DC power converters’ (Wiley, Chichester, UK, 2008) [18] Suresh Y., Panda A.K., Suresh M.: ‘Real-time implementation of adaptive fuzzy hysteresis-band current control technique for shunt active power ﬁlters’, IET Power Electron., 2012, 5, (7), pp. 1188–1195 [19] Fangrui L., Maswood A.I.: ‘A novel variable hysteresis band current control of three-phase three-level unity PF rectiﬁer with constant switching frequency’, IEEE Trans. Power Electron., 2006, 21, (6), pp. 1727–1734 [20] Peña-Alzola R., Liserre M., Blaabjerg F., ET AL.: ‘A selfcommissioning notch ﬁlter for active damping in a three-phase LCL-ﬁlter-based grid-tie converter’, IEEE Trans. Power Electron., 2014, 29, (12), pp. 6754–6761 [21] Biricik S., Komurcugil H.: ‘Three-level hysteresis current control strategy for three-phase four-switch shunt active ﬁlters’, IET Power Electron., 2016, 9, (8), pp. 1732–1740 [22] Tamyurek B., Torrey D.A.: ‘A three-phase unity power factor single stage ac–dc converter based on an interleaved ﬂyback topology’, IEEE Trans. Power Electron., 2011, 26, (1), pp. 308–318 [23] Sun J., Mitchell D.M., Greuel M.F., ET AL.: ‘Averaged modeling of PWM converters operating in discontinuous conduction mode’, IEEE Trans. Power Electron., 2001, 16, (4), pp. 482–492 [24] Suntio T.: ‘Average and small-signal modeling of self-oscillating ﬂyback converter with applied switching delay’, IEEE Trans. Power Electron., 2006, 21, (2), pp. 479–486 [25] Wang L., Lam C.S., Wong M.C., ET AL.: ‘Non-linear adaptive hysteresis band pulse-width modulation control for hybrid active power ﬁlters to reduce switching loss’, IET Power Electron., 2015, 8, (11), pp. 2156–2167 [26] Ostos J.C., Lu D.D.C.: ‘Modeling and analysis of CCM non-isolated high step-up interleaved buck–boost dc/dc converters’. Int. Conf. Proc. IEEE Power and Energy Conf., IEEE-PECon’12, Kota Kinabalu, 2–5 December 2012, pp. 28–31 [27] Kondrath N., Kazimierczuk M.K.: ‘Uniﬁed model to derive control-to-output transfer function of peak current-mode-controlled pulse-width modulated dc–dc converters in continuous conduction mode’, IET Power Electron., 2012, 5, (9), pp. 1706–1713 [28] Andrikopoulos G., Nikolakopoulos G., Manesis S.: ‘Advanced nonlinear PID-based antagonistic control for pneumatic muscle actuators’, IEEE Trans. Ind. Electron., 2014, 61, (12), pp. 6926–6937 [29] Erickson R.W., Maksimovic D.: ‘Fundamentals of power electronics’ (Norwell Kluwer, MA, 2001, 2nd edn.)

9 Appendix. Analytical derivation of small signal model of interleaved non-ideal DC–DC boost converter The small signal state-space representation of IBC is derived in what follows. The linearised differential equations, using switched statespace technique through state-space averaged models of the

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conventional boost converter, for non-ideal ILBC, are deﬁned as follows [29]: ⎫ ⎪ ⎪ ˆ = Vin − ˆiLi (t)RLi − (1 − Di )ˆvo (t) + Vo d i (t) ⎪ Li ⎬ dt ∀i = [1, 3] dˆv (t) ⎪ ˆ − ˆi (t) ⎪ (1 − Di )ˆiLi (t) − ILi d(t) C C = ⎪ Load ⎭ dt dˆiLi (t)

i

i

state-space averaged model neglecting the second-order non-linear term in linearised AC model can be formulated as follows: ˆ xˆ˙ (t) = Aˆx(t) + Bˆu(t) + Bd d(t) i=6 where A = i=6 i=1, 3, 5 Ai X − i=1 Ai Di , B = i=1 Bi Di and Bd = j=2, 4, 6 Bi U and ⎡

⎡1⎤ ⎢ L1 ⎥ iL1 ⎢ ⎥ ⎢1⎥ ⎢i ⎥ ⎢ ⎥ ⎢ L2 ⎥ ⎥ xˆ (t) = ⎢ ⎥; Bi = ⎢ ⎢ L2 ⎥∀i = [16] ⎣ iL ⎦ ⎢1⎥ 3 ⎢ ⎥ ⎣L ⎦ Vo

⎤

⎡

˙iL ⎢˙ 1 ⎥ ⎢ iL2 ⎥ ⎥ xˆ˙ (t) = ⎢ ⎢ ˙i ⎥; ⎣ L3 ⎦ V˙ o

⎤

3

0 D1 = D3 = D5 = D; D1 + D3 + D5 + D2 + D4 + D6 = 1 Similarly, the matrices in states 2–6 can be of similar form in what follows: ⎡

−

RL L1

⎢ ⎢ ⎢ ⎢ ⎢ 0 ⎢ ⎢ A1 = ⎢ ⎢ ⎢ ⎢ 0 ⎢ ⎢ ⎢ ⎣ 0 ⎡

−

−

0

RL L2

0

−

0

0

R(Rc + RL ) + RL Rc L3 (R + Rc ) R C(R + Rc ) 0

⎥ ⎥ ⎥ ⎥ ⎥ 0 ⎥ ⎥ ⎥ ⎥ R ⎥ ⎥ − L3 (R + Rc ) ⎥ ⎥ ⎥ ⎦ 1 − C(R + Rc ) 0

R(Rc + RL ) + RL Rc L2 (R + Rc )

−

R(Rc + RL ) + RL Rc L2 (R + Rc )

−

R(Rc − RL ) − RL Rc L3 (R + Rc )

−

R(Rc − RL ) − RL Rc L3 (R + Rc )

R C(R + Rc ) 0 −

R(Rc + RL ) + RL Rc L2 (R + Rc ) 0 R C(R + Rc )

R C(R + Rc ) 0 0 −

RL L3

0

⎤ 0

−

RL L1

⎢ ⎢ ⎢ ⎢ ⎢ 0 ⎢ ⎢ A3 = ⎢ ⎢ ⎢ ⎢ 0 ⎢ ⎢ ⎢ ⎣ 0

−

0

RL L1

⎢ ⎢ ⎢ ⎢ ⎢ 0 ⎢ ⎢ A2 = ⎢ ⎢ ⎢ ⎢ 0 ⎢ ⎢ ⎢ ⎣ 0 ⎡

⎤ 0

⎤

⎥ ⎥ ⎥ ⎥ R ⎥ − L2 (R + Rc ) ⎥ ⎥ ⎥ ⎥ R ⎥ ⎥ − L3 (R + Rc ) ⎥ ⎥ ⎥ ⎦ 1 − C(R + Rc )

0

⎥ ⎥ ⎥ ⎥ R ⎥ − L2 (R + Rc ) ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ 0 ⎥ ⎥ ⎥ ⎦ 1 − C(R + Rc )

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⎡

R(Rc + RL ) + RL Rc ⎢− L1 (R + Rc ) ⎢ ⎢ ⎢ R(R + R ) + R R c L L c ⎢− ⎢ L2 (R + Rc ) ⎢ A4 = ⎢ ⎢ ⎢ 0 ⎢ ⎢ ⎢ ⎢ ⎣ R C(R + Rc ) ⎡ R(R + R ) + R R c L L c − ⎢ L1 (R + Rc ) ⎢ ⎢ ⎢ ⎢ 0 ⎢ ⎢ A5 = ⎢ ⎢ ⎢ 0 ⎢ ⎢ ⎢ ⎣ R ⎡

C(R + Rc )

R(Rc + RL ) + RL Rc ⎢− L1 (R + Rc ) ⎢ ⎢ ⎢ ⎢ 0 ⎢ ⎢ A6 = ⎢ ⎢ R(R + R ) + R R ⎢ c L L c ⎢− ⎢ L3 (R + Rc ) ⎢ ⎢ ⎣ R C(R + Rc )

−

R(Rc + RL ) + RL Rc L1 (R + Rc )

0

−

R(Rc + RL ) + RL Rc L2 (R + Rc )

0 −

0 R C(R + Rc )

⎤ R L1 (R + Rc ) ⎥ ⎥ ⎥ ⎥ R ⎥ − ⎥ L2 (R + Rc ) ⎥ ⎥ ⎥ ⎥ 0 ⎥ ⎥ ⎥ ⎥ ⎦ 1 − C(R + Rc ) −

RL L3

0 ⎤

0

0

0

RL L2

0

0

RL L3

0

−

0 0 0 −

−

−

0

R(Rc + RL ) + RL Rc − L1 (R + Rc )

RL L2

0 0

1 C(R + Rc )

⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎥ ⎦

0 −

R(Rc + RL ) + RL Rc L3 (R + Rc ) R C(R + Rc )

⎤ R − L1 (R + Rc ) ⎥ ⎥ ⎥ ⎥ ⎥ 0 ⎥ ⎥ ⎥ ⎥ R ⎥ − ⎥ L3 (R + Rc ) ⎥ ⎥ ⎥ ⎦ 1 − C(R + Rc )

The control to output transfer function of the IBC is designed and derived as

vˆ o (t) = (sIn − A)−1 Bd n=4 ˆd

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