HfO2-based Ferroelectric Field-Effect Transistors with 260 nm channel length and long data retention Ekaterina Yurchuk1, Johannes Müller2, Raik Hoffmann2, Jan Paul2, Dominik Martin1, Roman Boschke3, Till Schlösser3, Stefan Müller1, Stefan Slesazeck1, Ralf van Bentum3 , Martin Trentzsch3, Uwe Schröder1 and Thomas Mikolajick1 1
NaMLab gGmbH, Noethnitzer Strasse 64, 01187 Dresden, Germany Fraunhofer Center Nanoelectronic Technologies, Koenigsbruecker Strasse 180, 01099 Dresden, Germany 3 GLOBALFOUNDRIES Dresden Module One LLC & Co. KG, Wilschdorfer Landstrasse 101, 01109 Dresden, Germany mail to:
[email protected] 2
Abstract—We report the fabrication of highly scaled sub-0.3 μm ferroelectric field-effect transistors on the basis of ferroelectric HfO2. The electrical properties of 9 nm thick Si-doped HfO2 films depending on the silicon content and the annealing temperature were investigated. The most suitable fabrication conditions for the emergence of ferroelectricity were identified. The ferroelectric properties were verified up to temperatures of 170 oC. N-channel MFIS-FETs (MetalFerroelectric-Insulator-Semiconductor Field-Effect Transistors) with poly-Si/TiN/Si:HfO2/SiO2/Si gate stack and channel lengths down to 260 nm were successfully fabricated. The switching characteristics, endurance and retention properties were analysed. Switching times of 10 ns were demonstrated. A memory window of 1.2 V was obtained with program/erase voltages of -6.5 V and +4 V and pulses as short as 50 ns. Endurance performance of up to 104 cycles was verified. Retention characteristics were measured at 25 oC and 150 oC. 10 years data retention was indicated for both temperatures by the extrapolation of the experimental data. Keywords- FeFET; ferroelectric; hafnium oxide
I.
INTRODUCTION
Ferroelectric field effect transistors (FeFETs) have been discussed as promising candidates for future non-volatile memory applications for many years [1–3]. The FeFETs utilize the polarization of the ferroelectric material incorporated into the transistor gate-stack to control the channel conductivity. In comparison to the conventional floating-gate based technology the FeFETs provide several advantages: very short write/erase times (in the nanosecond range), low voltage operation (5–6 V) and excellent endurance characteristics [4]. However, their industrial implementation has not been successful up to now. The main challenges of the FeFET approach are integration of the conventional ferroelectric materials (e.g. PZT, SBT) into CMOS technology and the down-scaling of the gate stack beyond the 50 nm node [4, 5]. The recently introduced HfO2-based ferroelectrics [6–8] have the potential to solve these issues. The scaling of the MFIS-FETs using PZT and SBT materials is limited by the necessity of growing thick films (200–500 nm) to obtain good ferroelectric properties and to ensure the predominant voltage drop over the ferroelectric layer. This scaling rule will
not be an issue for HfO2-based FeFETs. The significantly lower dielectric constant of HfO2 (~20 in contrast to PZT or SBT ~200–300) eliminates the need for thick films. HfO2 is fully compatible to the conventional CMOS technology and is already established as reliable gate dielectric in high-k metal gate technology. The atomic layer deposition (ALD) ensures a high quality of the thin HfO2 layers (10–30 nm) with excellent ferroelectric properties. Moreover, promising retention characteristics revealing 10 years data retention have been already demonstrated in long channel devices [9]. In this work we report the successful fabrication of MFIS-FETs utilizing Si-doped HfO2. The devices were scaled down to 260 nm channel length, which is comparable to the most advanced FeFET cells with conventional ferroelectric SBT material [10]. A detailed characterization of the device performance was carried out including memory window, switching characteristics, endurance and retention properties. Within our study we report retention characteristics at both room temperature and elevated temperatures. Several material aspects of HfO2 thin films are discussed in order to give better insight into their ferroelectric properties and guidelines for transistor fabrication. II.
EXPERIMENTAL DETAILS
The metal-insulator-metal (MIM) capacitors were formed by deposition of a Pt/TiN/Si:HfO2/TiN film stack on silicon substrates. ALD process is utilized for the deposition of 9 nm thick Si:HfO2 layers with a dopant concentration between 0 and 6.6 mol% of SiO2. The accurate determination of the Si content was performed by means of XPS measurements. 10 nm thick TiN top and bottom electrodes were grown in a batch furnace using a pulsed CVD process at 450 oC. The annealing was performed following the formation of TiN top electrodes. N-channel MFIS-FETs with a poly-Si/TiN/Si:HfO2/SiO2/Si gate stack were fabricated using state-of-the-art high-k metal-gate technology on a 300 mm manufacturing equipment. In contrast to the fabrication of MIM structures the 10 nm thick TiN layer was grown using PVD technique to avoid the undesirable early crystallization of HfO2, that was partially detected for CVD-TiN. The chemically grown SiO2 interface layer between the substrate and HfO2 had
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a thickness of 1.2 nm. The transistor structures were successfully scaled down to a channel length of 260 nm. III.
RESULTS AND DISCUSSION
A. Ferroelectric Si-doped HfO2 It has already been reported in [6-8] that thin HfO2 films doped with a certain amount of trivalent or tetravalent cations and crystallized under encapsulation exhibit either ferroelectric or antiferroelectric properties. HfO2 layers with ferroelectric characteristics are used for manufacturing of ferroelectric FETs to ensure their non-volatility. Therefore, the effect of SiO2 content and annealing temperature was examined in order to find the most suitable fabrication conditions for the emergence of ferroelectricity in the HfO2 films. Pt/TiN/Si:HfO2/TiN capacitors with 9 nm thick HfO2 layers containing different fractions of SiO2 from 0 (pure HfO2) to 6.6 mol% were electrically characterized. The results of polarization- and capacitance-voltage measurements performed on samples annealed at 850 oC are shown in Fig. 1. Pure HfO2 shows a linear dielectric response, being paraelectric as expected. The admixture of SiO2 induces non-linearity of both P-V and C-V characteristics. For layers with 4.4 mol% SiO2 polarization hysteresis loops were detected evidencing the presence of a ferroelectric phase. An increased SiO2 concentration of 6.6 mol% induced the stabilization of a higher-symmetry phase indicated by the appearance of antiferroelectric properties [6], i.e. a double-loop hysteresis. Additionally ferro- and antiferroelectricity was proven by means of capacitance-voltage measurements shown in Fig. 1b. Accordingly, HfO2 films with 4.4 mol% SiO2 are most suitable for the implementation in ferroelectric FETs.
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Polarization (μC/cm )
60 40
2
6.6 mol %
20 0 -20 -40 -60 4.5
Capacitance (μF/cm )
4.4 mol %
SiO2 0 mol %
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(a) 3 0 3 SiO2 0 mol%
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0 3 4.4 mol %
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0 3 6.6 mol %
3.5 3.0 2.5 2.0 1.5 1.0
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-3 0 0 3 -3 0 3 Electric field strength (MV/cm)
(b) 3
Figure 1. (a) Polarization- and (b) capacitance-voltage measurements performed on TiN/Si:HfO2/TiN capacitors with different SiO2 contents annealed at 850 oC. A transition from paraelectric over ferroelectric to antiferroelectric behavior is visible with increasing SiO2 concentration.
For ferroelectric samples (4.4 mol% SiO2) the effect of annealing temperature on the remanent polarization and the coercive field strength was studied (Fig. 2). Since all samples were exposed to 450 oC during the deposition of the TiN top electrodes by CVD the as-deposited samples were defined as annealed at 450 oC. Post deposition annealing was carried out at 650, 800 and 1000 oC for 20 s, 20 s and 1 s, respectively. The highest temperature treatment simulates a spike anneal typically used in the CMOS technology for implant activation. The increasing crystallinity of the HfO2 films with annealing temperature (confirmed by X-ray diffraction measurements not shown here) induces a higher fraction of a ferroelectric phase and therefore a higher remanent polarization. The change of the coercive field strength with the annealing temperature remains negligible. Thus spike anneals at temperatures around 1000 oC are suitable for the formation of Si:HfO2 with sufficient ferroelectric properties. As a result no additional annealing step is needed for the fabrication of ferroelectric transistors in a fully integrated state-of-the-art CMOS process. Furthermore, the thermal stability of the ferroelectric properties was investigated in the temperature range between 25 oC and 170 oC. It could be shown that the material retains its ferroelectric behavior up to 170 oC, as the polarization hysteresis loop remains almost immutable for all examined temperatures (Fig. 3). Thus the ferroelectric HfO2 is stable at elevated temperatures. A slight decrease of the remanent polarization above 100 oC can be attributed to the reduced ability of dipoles to maintain their orientation. The kinetic energy of the lattice ions increases with temperature, which makes it easier for them to change their position in the double well potential resulting in a decreased stability of the dipoles. B. HfO2-based MFIS Field Effect Transistors The performance of n-channel MFIS-FETs with poly-Si/TiN/Si:HfO2/SiO2/Si stack scaled down to a channel length of 260 nm was investigated in detail. The drain current versus gate voltage characteristics after 100 ns program/erase pulses of -6 V/+4 V are shown in Fig. 4. A shift in the threshold voltage oppositely to the polarity of the applied voltage evidences the ferroelectric switching. These operation voltages induce a memory window of 1.2 V. The measured program and erase characteristics are shown in Fig. 5 as a function of pulse width at different amplitudes. The ferroelectric switching was detected at pulses as short as 10 ns. The maximum memory window of 1.2 V was obtained at voltages of +4 V/-6.5 V applied for 50 ns each. At very high and long pulses a reduction of the memory window was observed. For these operation conditions charge trapping superimposes the ferroelectric switching, causing a threshold voltage shift in the direction oppositely to the shift induced by ferroelectric switching. This ultimately results in a reduction of the memory window. Endurance performance was tested by applying alternating pulses of -6 V/ +4 V for 100 ns each. The results shown in Fig. 6 indicate a write/erase potential of up to 104 cycles.
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5 0 0.0 400 500 600 700 800 900 1000
30 2
Polarization (μC/cm )
Annealing temperature ( C) Figure 2. The remanent polarization and the coercive field strength of the ferroelectric TiN/Si:HfO2/TiN capacitors (4.4 mol% SiO2) depending on annealing temperature. The increase of annealing temperature induces a higher remanent polarization and a negligible change in the coercive field strength.
Memory window (V)
30 MW ~1,2 V
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-2 0 2 Electric field strength (MV/cm)
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-4.5 V -5 V -6 V -6.5 V
0 1 Vgate (V)
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1.0 +2 +3 V +3.5 V 0.5 +4 V +4.5 V +5 V
0.5
Figure 5. Memory window of MFIS-FETs with a channel length of 260 nm detected for (a) program and (b) erase pulses of varying amplitude and width. Ferroelectric switching was registered for a pulse width as short as 10 ns.
1.0 programmed -6 V 100 ns 0.5 0.0 -0.5 erased +4 V 100 ns 0
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1E-8 1E-7 1E-6 1E-5 1E-4 1E-8 1E-7 1E-6 1E-5 1E-4 Pulse width (s) Pulse width (s)
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Figure 4. Drain current versus gate voltage after applying erase/program pulses of +4 V 100 ns and -6 V 100 ns for MFIS-FETs with a channel length of 260 nm. A memory window of approximately 1.2 V was detected.
10
4
(b)
0.0
0 -1
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-20
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Cycles Figure 6. Endurance characteristics of MFIS-FETs with a channel length of 260 nm. Alternating +4 V and -6 V pulses of 100 ns were applied.
1.0 programmed -6.5 V 100 ns 0.5 0.0
o
Experimental data 25 C o Experimental data 150 C Extrapolation
erased +4.5 V 100 ns
10 years
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-2 V -3 V -4 V
Threshold voltage (V)
Idrain (μA)
40
o
25 C o 45 C o 90 C o 130 C o 170 C
0
Figure 3. Temperature dependent polarization measurements on the ferroelectric TiN/Si:HfO2/TiN capacitors (4.4 mol% SiO2). The polarization hysteresis loop remains stable up to temperature of 170 oC.
1.5 (a)
50 +4 V 100 ns -6 V 100 ns
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o
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-0.5 0 1 2 3 4 5 6 7 8 10 10 10 10 10 10 10 10 10 time (s)
Figure 7. The retention characteristics of MFIS-FETs measured at 25 oC and 150 oC. Extrapolation of experimental data reveals 10 years data retention at both temperatures.
Data retention characteristics for ON (erased with +4.5 V 100 ns pulse) and OFF (programmed with -6.5 V 100ns pulse) states were measured at 25 oC and 150 oC for up to 10 days retention time. A residual memory window of 0.9 V at 25 oC and 0.5 V at 150 oC was detected (see Fig. 7). The extrapolation of the experimental data reveals the non-volatility of information storage over 10 years at both temperatures. Therefore, these results outperform the data shown in [10] for comparably scaled FeFETs utilizing SBT ferroelectric. IV.
CONCLUSIONS
In summary, we have shown that ferroelectric behavior in 9 nm thick HfO2 films can be induced by doping with 4.4 mol% SiO2. Spike anneals at 1000 oC can be used to obtain crystalline layers with sufficient remanent polarization to induce a significant threshold voltage shift. The temperature stability of the ferroelectric phase was proven up to 170 oC. This novel ferroelectric material was implemented in highly scaled FeFETs with a channel length of 260 nm. This matches the contemporary scaling node of FeFETs based on conventional SBT ferroelectrics [10]. Switching times of 10 ns could be demonstrated. A memory window of 1.2 V was detected for program/erase voltages of -6.5 V and +4 V and a pulse width of 50 ns. Endurance performance up to 104 cycles was verified. 10 years data retention at 25 oC and 150 oC was evaluated by the extrapolation of the experimental data measured at these temperatures. ACKNOWLEDGMENT The work for this paper was partially supported within the scope of technology development by the EFRE fund of the European Community and by funding of the Free State of Saxony (Project HEIKO Nr. 100064807).
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