AbstractâDesign and measurement results are presented for a 0.18 µm CMOS full-wave rectifier architecture with 85.8% measured power efficiency at 40.68 ...
High-Efficiency CMOS Rectifier for Fully Integrated mW Wireless Power Transfer Meysam Zargham, P. Glenn Gulak School of Electrical and Computer Engineering University of Toronto Email: {zarghamm,gulak}@eecg.toronto.edu Immersed in blood
ɳ= 70%
1cm EM Field ɳ= -21dB
CMOS
PCB substrate
4mm2 die
ɳ= 86%
Rectifier
1mW
Regulator
ɳ= 80%
Fig. 1. Block diagram of a fully integrated wireless power delivery system. The system integrates the receiver coil on-chip and provides 1mW of power to a CMOS wireless sensor immersed in blood, 10mm away from the transmitter.
media between the TX and RX coils, the coupling efficiency (ηcoupling ) suffers from low efficiency [1]. Therefore it is critical for the rectifier to provide high efficiency. It has been shown that the optimum frequency for near-field inductively coupled wireless on-chip WPT receivers is around 100MHz, with 40.68MHz as the closest ISM band [1]. In addition to this, due to low coupling efficiency, the range of delivered power in these systems is between hundreds of µW to a few mW [1]. A great deal of attention in the literature has been devoted to high efficiency rectifiers. However none of the existing designs are suitable for on-chip WPT receivers. Rectifiers used in RFID tags are designed for delivering 10’s of µW at 950MHz. At the other extreme, there is a large body of published literature on CMOS rectifiers optimized for power delivery in the 10’s of mW range (and greater), working at the low MHz range. Between these two extremes, none of the wireless power literature surveyed is designed for high efficiency at 40.68MHz required for any WPT receivers integrated on a CMOS substrate. This section presents a power-efficient, lowcomplexity rectifier that provide a measured efficiency of 85.8% at 40.68 MHz while delivering 1mW of power to a biosensor immersed in blood as shown in Fig. 1. The remainder of the paper is organized as follows. In section II, the high efficiency rectifier is introduced. In section III, we present the simulation and measurement results and compare the rectifier with other state-of-the-art published rectifiers. Finally, in the last section we conclude the paper.
(1)
However, due to the limited size of an on-chip receiver coil, the electrical properties of the Si substrate and the conductive 978-1-4673-0219-7/12/$31.00 ©2012 IEEE
Pin=270mW
Pin 1.5mW
Sensor
ηtotal = ηPA × ηcoupling × ηrectifier × ηregulator
PA
Transmitter Coil
RF Limiter
I. I NTRODUCTION Wireless power delivery is becoming increasingly important for implantable microelectronics devices (IMD) and lab-onchip (LoC) applications that require measurement or sensing of biological phenomenon. In these scenarios the use of batteries is restricted due to their size, cost, lifetime and packaging issues. Within this domain, near-field inductive coupling is one of the most practical ways of transmitting data and energy to implantable devices. Examples of such sensors are bacteria identification circuits or neural implants. In such systems the circuits contained in the IMD or the LoC are remotely powered by means of two coupled inductors and a power amplifier operating at a fixed carrier frequency. It is highly desirable to fully integrate the power receiver coil on the CMOS substrate. Aside from the obvious reduction in size compared to typical implants that are already in use today a wireless power transfer (WPT) receiver integrated on a single CMOS substrate is protected from the outside environment through a passivation layer, while access to sensor electrodes would be granted through selected passivation openings across the die. The later property is especially beneficial in accommodating applications that involve liquid samples. As a result the die would be readily mass producible. The elimination of the package and the external coil reduces the form factor and cost, as well as elimination (or at least reduction) in post-processing package+die encapsulation steps ultimately makes the single die design proposed extremely attractive. Figure 1 shows the block diagram of the system. Utilizing energy collected at the receiver coil requires a rectifier, regulator and a bandgap voltage reference to deliver a stable, load-independent voltage to the circuit. The power efficiency of the link is given below:
f=40.68MHz
Matching Networks
Abstract—Design and measurement results are presented for a 0.18 µm CMOS full-wave rectifier architecture with 85.8% measured power efficiency at 40.68 MHz. The rectifier targets fully integrated power harvesting biomedical implant and labon-chip applications that use on-chip or mm-sized near-field inductively coupled wireless power transfer receivers. The rectifier uses feedback from the output to lower the voltage drop and increase the power efficiency. The rectifier achieves the highest measured efficiency in its class.
II. R ECTIFIER Conventionally, rectifiers are built using diode bridges. Diodes commonly have large voltage drops and hence are
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VREC + M5
M6
R1
RF+
M3
M1
C1
RF-
R2
CL
RL
M4
C2
M2
VREC -
Fig. 2. Proposed rectifier circuit. The coil shown in the figure between RF+ and RF- represents the WPT receiver coil implemented in top layer metal on the CMOS substrate.
Fig. 3. Die micrograph of the proposed rectifier in 0.18µm. The dimensions are 426×108 (µm)2 .
the transistors is to cross-couple the gate of all transistors to the input RF voltage terminals. However a cross-coupled
590 VBias 580
Voltage(mV)
not suitable for low voltage circuits. One common way of dealing with this issue is to use low Vt (threshold voltage) transistors, which would translate to higher fabrication costs. A less expensive solution to this problem is provided by active diodes, various threshold cancellation techniques and comparator-based rectifiers. The published rectifiers based on threshold cancelling techniques suffer from low power efficiency [2]–[4]. The comparator-based [5]–[7] rectifiers show promising performance at low frequencies where the traditional power harvesting systems operate. However timing of the comparators plays an important role in the power efficiency of these comparators and consequently the design of high frequency comparators is challenging. As a result they tend to suffer from poor power efficiency at higher frequencies [6] preventing them from fulfilling an essential requirement when the receiver coil is fully integrated in a single-chip WPT receiver. [1], [8]. In this section we propose a rectifier based on partial threshold cancellation. The schematic of the proposed fully integrated rectifier is shown in Fig. 2 and its die photo is shown in Fig. 3. The circuit was implemented in 0.18µm CMOS technology using 3.3V transistors with high threshold voltages (nMOS: 800mV, pMOS: 660mV). The choice of high voltage and hence higher threshold voltage transistors was required by the 3.3V supply needed by the sensor circuit. One solution to overcome the high threshold voltage of
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14.735
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Fig. 4. Dynamic bias voltage for partial threshold cancellation. The input voltage in the simulation is 4.5V, Load = 10kΩ and VREC+ = 4.04V.
transistor would experience periods when both transistors are conducting as well as reverse currents due to Gate-InducedDrain-Leakage (GIDL) currents [9]. As the result they would lower the efficiency. Another solution is to cancel the threshold using threshold cancellation techniques [2], [4], [10]. However this would result in excessive subthreshold leakage due to the large size of these transistors and hence a lower power conversion efficiency. In the proposed design, the threshold voltage cancellation is partial and adaptive. The gate of the bottom nMOS transistors M3 , M4 are biased using crosscoupled resistors and diode connected transistors. The average value of this bias voltage tracks the threshold voltage of M1 and M2 through process and temperature variations. This average value is smaller than the threshold voltage of M3 and M4 and can be adjusted by proper sizing of M1 , M2 and the value of the resistors R1 , R2 . Ideally, when one of the transistors M3 or M4 is on, the other transistor has to be off. The higher we choose the bias voltage the less on resistance is experienced during the conduction phase. Conversely, a value too close to the threshold would increase the leakage currents through the off transistor especially at high input voltages. Hence completely cancelling the threshold voltage would result in low efficiency. In this design, the average stored voltage at the gate is 70% of the threshold voltage of M3 and M4 and by cross-coupling the resistive connection, this voltage adaptively increases to 75% and falls to 65% during the conducting and non-conduction phases. The exact variation depends on the magnitude of the input RF signal. Figure 4 show the variation of the bias voltage for a 4.5V sinusoidal input. The transistors M3 and M4 only conduct when the negative RF voltage goes below VREC- by more than 150mV. During the non-conducting phase, the gate source over-drive of these transistors is kept at -280mV. Hence both the GIDL and subthreshold currents are minimized. Figure 5 shows post-layout simulations (PLS) of the rectifier when delivering 1.6mW of power to a 10kΩ resistor. The amplitude of the input RF signal in this simulation is 4.5V and the rectifier output voltage converges to 4.04V. The motivation
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Simulated waveform of the currents through transistor M4 .
Fig. 6.
Fig. 5. PLS waveforms for the proposed rectifier. In these simulations the CL = 1nF.
Vector Network Analyzer HP 8753C
100nF
The design also ensures that the substrate diode of all transistors are off during steady-state operation. The bulk terminal of the pMOS transistors is connected to VREC+ and the bulk of the nMOS transistors is connected to VRECnode. The absolute value of the source-bulk voltage of any of the transistors never exceeds 350mV. Hence the substrate diodes are never forward-biased during the steady-state operation of the rectifier. Using this technique we achieve a measured efficiency of 85.8%, at 40.69MHz, which is the highest reported efficiency at this frequency. However, due to the partial cancellation of threshold the average voltage drop is 360mV which is 150mV higher than the case for fullthreshold cancellation. The optimal frequency for the proposed WPT receiver on CMOS substrate is 120MHz for maximum power tranfer efficiency, with 40.68MHz being the closest ISM band. Simulations of the rectifier shows an efficiency of 86% at 120MHz. The proposed design is capable of working at higher frequencies without a large penalty in power conversion efficiency. The next section provides the measurement and
Load
behind cross-coupling the pMOS transistors was to reduce the voltage drop. In the conventional rectifiers with cross-coupled transistors, when the RF signal is lower than VREC+ but higher than VREC- volts, the transistors would sink unwanted reverse currents from the load capacitor. However in the proposed rectifier, the bottom nMOS transistors would only turn on when the RF signal is smaller than VREC- and hence during the time that the RF signal travels between VREC+ and VREC- , the nMOS transistors block the current path. Therefore, the reverse leakage is effectively reduced. Figure 6 shows the current through one of the transistors. As evident in Fig. 6 the peak reverse current is only 4% of the peak forward current. As a result the circuit forces the floating RF source to position its voltage such that the voltage drop across the conducting pMOS transistor would be less than 100mV. Hence effectively shutting down the pMOS transistor during the transition. Figure 5 shows the simulated waveforms. Also when one of the pMOS switches is fully on, the leakage through the other pMOS is orders of magnitude smaller.
Balun
Rectifier ZFDC-20-4-S+
Coupler
Fig. 7.
Power Meter E4418B7B
Measurement setup for calculating the efficiency of the rectifier.
simulation results for the proposed rectifier. III.
MEASUREMENT AND SIMULATION RESULTS
In this section we present the simulation and measurement results for the proposed rectifier. Figure 7 shows the hardware setup for measuring the efficiency of the rectifier. The conventional method of using a series resistor for calculating the input power resulted in large uncertainty in measuring the efficiency at this frequency. Therefore, we used the following method to measure the power efficiency. The rectifier was tested using a vector network analyzer, and a balun at 40.68MHz. In order to measure the efficiency we first measured the two-port scattering parameters Sij of the measurement setup from the VNA to the chip. We then calculate the Γin (setup) using the VNA. During this measurement, the input power from the VNA was adjusted so that the rectifier was delivering 3.15V to the load resistor. Using the twoport scattering parameters of the test setup and the measured Γin (setup), we were able to calculate reflection of the rectifier, Γin (rec) and hence measure the loss of efficiency through the measurement setup: |S21 |2 1-|Γin (rec)|2 ηsetup = (2) (1-|Γin (setup)|2 ) |1-S22 Γin (rec)|2 Pin (rec) = Psource × 1-|Γin (setup)|2 × ηsetup . (3) The power delivered to the load was then calculated by measuring the output DC voltage of the rectifier using a Keithley 6514 electro-meter. Figure 9 shows the measured efficiency versus simulation results. The drop of efficiency at higher
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Measured Efficiency
TABLE I R ECTIFIER P ERFORMANCE S UMMARY AND C OMPARISON
PLS Efficiency
90
Efficiency (%)
80
[4] [2] [3] [11]
70 60
This Work [12] [13] [6] [7] [5]
50 40
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9
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12
Load Resistance (kΩ)
Pout (W)
Frequency(Hz)
Power Efficiency(%)
Vdrop (V)
28µ 56µ 90µ 190µ
950M 953M 953M 915M
11 67.5 36.6 65
n/a n/a n/a 150m
1m 6m 19m 19.5m 25m 40m
40.68M 13.56M 2M 13.56M 10M 1.5M
85.8 89 84.8 80.2 76 87
360m 280m 640m 680m 960m 320m
Fig. 8. Measured and simulated efficiency for the proposed rectifier. The output DC voltage during measurement was 3.15V. Measured Voltage Drop
power to an 8kΩ resistor.
Simulated Voltage Drop
500
ACKNOWLEDGMENT
Volttage drop(mV)
The authors thank NSERC and CMC for thier support. R EFERENCES
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200 7
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Load Resistance (kΩ)
Fig. 9. Measured and simulated voltage drop for the proposed rectifier. The output DC voltage during measurement was 3.15V.
load resistance values could be associated with the accuracy of the measurement setup at low power levels. The voltage drop was measured by calculating the difference between the output DC voltage of the rectifier and the amplitude of the input sinusoidal voltage. The former quantity was measured using a high frequency differential probe. The signal during this measurement was applied directly to the rectifier. Table I provides the performance summary and comparison results for the implemented rectifier sorted by Pout . The achieved efficiency is very similar to the efficiencies reported by comparator-based rectifiers. However the frequency of operation is higher, the sensitivity to change in frequency and process variations is low and the design is simple. IV. C ONCLUSION This paper presents an integrated, power-efficient CMOS rectifier designed for inductively power circuits. The rectifier targets the 40.68MHz ISM band which is the optimum ISM frequency for near-field WPT receivers integrated on a 4mm2 CMOS substrate. The proposed circuit uses an adaptive biasing technique with partial threshold cancellation and achieves a measured efficiency of 85.8% while delivering 1.2mW of
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