High-Frequency Application of MOS Compact Models and their Development for Scalable RF' Model Libraries. D. R. Pehlke, M. Schroter*, A. Burstein, ...
High-Frequency Application of MOS Compact Models and their Development for Scalable RF'Model Libraries D. R. Pehlke, M. Schroter*, A. Burstein, M. Matloubian", M.F. Chang Rockwell Science Center, 1049 Camino Dos Rios, P.O. Box 1085, Thousand Oaks, CA 91358-0085 *Rockwell Semiconductor Systems, 43 11 Jamboree Rd., Newport Beach, CA 92660-3095
Abstract The evaluation of MOS compact models, focusing on BSIM3v3, is performed with specific development described toward scalable RF libraries suitable for high-frequency mixed-signal circuit design. Additional parasitic elements are added to the compact model to better describe its operation at higher frequency. This extrinsic subcircuit includes the gate resistance and complex substrate admittance which are scalable and physically based, and a detailed parameter extraction procedure for each is described. Small-signal yparameters and noise behavior of the extended model are used to verify the match to high-frequency onwafer measurements.
Introduction The RF transceiver in wireless communications traditionally has been dominated by GaAs and Siliconbipolar based technologies. Emerging commercial mass-market applications, however, require costefficient solutions, that tend towards higher levels of integration and silicon-based implementations. For the lower performance end of these, e.g. 900MHz cordless phones, mainstream CMOS digital processes are being considered as a potential cost-efficient solution [ 1-31 that allows integration of RF front-end circuits, such as low-noise amplifier (LNA) and mixer, with the mixedsignal and digital data processing components on the same chip. Despite using the same base-line process, analog high-frequency (including RF) circuit design requires very different expertise and approaches compared to digital circuit design. The same is true about compact transistor models that have to be very accurate over bias and frequency in order to facilitate a design cycle time comparable to that in the digital area. This paper describes the results of a general evaluation of MOS compact models based on the latest version 3 of
BSIM3 [4]with respect to its suitability for highfrequency circuit design using a 0.5pm CMOS process*
MOS Compact Modeling Issues for RF Application BSIM3v3 is presently being considered by many companies as a public domain standard model and embodies significant development toward lower frequency digital applications. Along with all other presently available compact MOS models, it's extrinsic elements are defined to minimize node count, maximize digital simulation efficiency for large scale integrated circuits, and address the specific requirements of the digital community. Highfrequency analog and mixed signal applications; however, require additional accuracy that can only be achieved with on-wafer high-frequency measurement and a more detailed extrinsic network. This extrinsic network requires additional nodes to accommodate it. This work details the development of such an extrinsic network which includes the gate resistance and complex substrate admittance to represent highfrequency resistive losses at the gate, source, and drain terminals. The parameter extraction of each is described along with the extraction of capacitances from on-wafer measurement at RF, de-embedding and physical modeling of the RF pad structure. Previous works have investigated RF application of MOS compact models [5,6], but this work focuses on a detailed model evaluation with respect to highfrequency specific improvements and scalability toward generation of a complete RF library.
MOS Model and Extrinsic Network Determination As the first step, the model parameters were
extracted from DC characteristics, low-frequency transconductance gm and output conductance gds, by
10.6.1 0-7803-4292-5/97/$10.00 0 1998 IEEE
219 IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE
using devices with different geometry and conventional binning schemes. Figures l a and lb show a typical characteristic for a high-frequency transistor.
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The high-frequency parameter determinations were made entirely from de-embedded on-wafer Sparameter measurements. Several key issues were addressed in this development. 0 The determination of capacitances of the model based on large area CV test structure measurements at 1 MHz proved to be inaccurate in the bias and frequency range of interest for RF design, which requires that the bias range include moderate inversion for low-power design, while the frequency range has to extend to the range of higher harmonics to facilitate accurate distortion analysis. The intrinsic gate to source and gate to drain capacitances are dominated by the same parameters that affect the threshold voltage, channel charge, and DC correspondence within the compact model. These parasitic overlap capacitances were determined from the high-frequency Y-parameters from a combination of direct extraction and optimization. Addition of gate, source, and drain series resistances to correctly represent the input admittance, RC time delays, and high-frequency noise behavior. The inclusion of gate resistance is critical both for the model accuracy of high-speed switching delay, as well as for the accurate noise behavior of the model. The gate resistance (see Figure 2) is assumed here as a bias-independent loss due to the finite sheet resistance of the silicided poly gate stripe. It is determined from the input impedance under strong inversion conditions with zero drain-to-source 6ias according to :
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figure l a : ID and gmvs VGSfor vDS=1,2, and 3 V for a transistor geometry of Lc = 0.5 p,finger width = 20 p,and number of fingers = 20
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Addition of a bias-independent RC network for proper modeling of the lossy substrate effect, which couples between draidsource and the substrate contact (see Figure 2). The augmentation to the bias dependent purely capacitive representation of the junction diode, C,svs, with a fixed value (determined by geometry) parallel R-C network to describe the resistive loss of the bulk parasitic is critical to the correspondence of complex output admittance at higher frequency. The calculation of
10.6.2
the substrate resistance, RPs, , and substrate capacitance term, Cps, , are according to :
be discussed. From this evaluation, it can be concluded that FW circuit design demands an expanded compact model than is presently available commercially, but that the required extrinsic network is readily implementable for scaled FW CMOS model libraries. Acknowledgments: The authors would like to thank G. Sridhaaran for performing the high-frequency noise measurements, B. Bhattacharyya for library implementation, and A. Salem for helpful discussions and supporting device simulations.
[I] A. Abidi, A. Rofougaran, G. Chang, J. Rael, J. Chang, M. Rofougaran,
where gDs is taken as the low frequency value of Relyz2-&,I, G,, = l / R p S u B , and is found from the quadratic solution to equation (4) above. Subsequent optimization on the direct extraction results for these substrate components is performed to improve the fitting with only slight changes to their value.
and P.Chang, ISSCC Digest, pp. 118, 1997. [2] J.C. Rudell, J.-J.Ou, T.B. Cho, G., Chien, F. Brianti, J.A.Weldon, and P.R. Gray ISSCC Digest, pp. 304, 1997. [3] A.R. Shahani, D. Schaeffer, and T.H.Lee, ISSCC Digest, pp. 368, 1997. [4] Y. Cheng, C. Hu, “Berkeley Short-Channel Insulated Gate Model”, Memorandum UCBERL M97/2,1997. [5] M.C. Ho, K. Green, R. Culbertson, J.Y. Yang, D. Ladwig, and P. Ehnis, IEEE MTT-S, p. 391-394, 1997. [6] W. Liu, R. Gharpurey, M.C. Chang, U. Erdogan, R. Aggarwal, and J. Mattia, IEDM (to be presented) 1997.
Correct representation of the geometry of the interdigitated high-frequency multi-finger layout with shared source and drain regions between gate fingers. Figure 2 shows the implementation used here with the “end” FBTs difference being unshared source regions. Figures 3-5 show comparisons of the model to measured transit frequency fT as a function of bias, as well as to the transconductance y21 and output conductance y22 as a function of frequency. Figure 6 contains a comparison of the frequency dependence of important noise parameters, using BSWL3 in the HPMDS circuit simulator. Results shown are from a scalable library and are intended to demonstrate the capability of standard compact MOS models once proper high-frequency measurement, parameter extraction and the complete extrinsic network are included. Additional results to be presented compare the model to measured data for various transistor sizes, along with a specific technique for de-embedding the RF pad parasitics from on-wafer measurement results. The resultant pad model and correspondence to the physical pad structure will also
10.6.3
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Figure 4 : y2l vs frequency for IDS= 4mA. 8 d . 2 o d , 4omA Vas= 0.83V, 0.94V, 1.03V, 1.18V vDs=lv. v s S d V . Same transistor as in Figure 1.
BSIM3v3 Microwave Noise Performance
Microwave Noise Performanceof BSIM3v3
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(a) Minimum Noise Agure vs frequency Vos=0.88 v, vDS=2 v, I D S = ~ImA. Same transistor as in Figure 1.
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10.6.4
