High-Frequency High-Efficiency CLL Resonant ... - Semantic Scholar

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 58, NO. 8, AUGUST 2011

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High-Frequency High-Efficiency CLL Resonant Converters With Synchronous Rectifiers Daocheng Huang, Dianbo Fu, Member, IEEE, Fred C. Lee, Fellow, IEEE, and Pengju Kong, Member, IEEE

Abstract—This paper proposes a CLL resonant dc–dc converter as an option for offline applications. This topology can achieve zero-voltage switching from zero load to a full load and zero-current switching for output rectifiers and makes the implementation of a secondary rectifier easy. This paper also presents a novel methodology for designing CLL resonant converters based on efficiency and holdup time requirements. An optimal transformer structure is proposed, which uses a current-type synchronous rectifier (SR) drive scheme. An 800-kHz 250-W CLL resonant converter prototype is built to verify the proposed circuit, design method, transformer structure, and SR drive scheme. Index Terms—Design methodology, driving scheme, high efficiency, high frequency, high power density, resonant converter, synchronous rectifier, transformer.

I. I NTRODUCTION

D

ISTRIBUTED POWER SYSTEMS (DPSs) are widely used in offline applications, such as servers and telecom applications. In a DPS, power is processed in two stages: front-end converters and load converters. Efficiency and power density are the two main driving forces of front-end converters [1]. Front-end converters normally consist of three parts: an electromagnetic interference (EMI) filter, a power-factorcorrection circuit, and a dc–dc converter. For computing applications, holdup time operation is required. Bulky capacitors must be used to provide energy during the holdup time. A wide operation range in the dc–dc stage is necessary to reduce the holdup time capacitance. Pulsewidth modulation (PWM) converters are widely employed as front-end dc–dc converters. Two-switch forward converters [2] have received a lot of interest for their robustness and their easy transformer reset mechanism. However, their high switching loss and large filter inductance are major concerns. Phase-shift full-bridge (PSFB) converters [3] can achieve zerovoltage switching (ZVS) to enhance the efficiency of the converter. However, when a holdup time is needed, the duty cycle of PSFB converters is small at nominal conditions. A small duty cycle leads to large circulating energy and high turnoff switching loss, which significantly sacrifices the efficiency.

Manuscript received January 2, 2010; revised May 3, 2010 and August 9, 2010; accepted September 9, 2010. Date of publication November 18, 2010; date of current version July 13, 2011. D. Huang, F. C. Lee, and P. Kong are with the Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg, VA 24061 USA (e-mail: [email protected]; [email protected]; [email protected]). D. Fu is with Huawei Technologies, Plano, TX 75075 USA (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2010.2093474

The aforementioned problems can be solved by using an LLC resonant dc–dc converter [4]–[6]. Low switching loss and low circulating energy are achievable at nominal conditions. Thus, high-efficiency operation is accomplished. A wide input voltage range is obtained in the low-frequency range, where the voltage gain is very high. Thus, the LLC resonant converter is suitable for offline applications with holdup time requirements. Nevertheless, for LLC resonant converters, there are still issues, such as how to drive synchronous rectifiers (SRs) and how to achieve low loss for a gapped transformer at high switching frequencies. Commercially, the drain–source voltage of SRs is sensed to drive SRs. However, the package inductance of an SR would cause a phase shift of the sensed voltage, which introduces high body-diode conduction loss. A compensation driving scheme has been proposed to correct the deviation [7]; however, this compensation scheme requires extra circuits, which are complicated. A secondary-side current-sensing method is also used to drive SRs [8]. However, the large size of the currentsensing transformer makes it awkward to use. For high-current applications, the extra resistance of the current transformer (CT) winding becomes lossy. On the other hand, the primaryside current is much lower, which means that the CT can be small and more efficient. However, the magnetizing inductance of the transformer for an LLC converter is used as resonant inductance and thus is relatively small. Due to the magnetizing current, the sensed primary-side current and the SR current are out of phase. Hence, the SR cannot be driven by sensing the primary-side current. To solve these issues, Wu et al. [9] propose an improved current-sensing method with an additional inductor and compensation circuits. However, the complexity and cost are major drawbacks. Consequentially, determining how to effectively drive an SR remains an issue for LLC resonant converters. In the transformer design, an air gap is used to control the magnetizing inductance. However, high eddy-current losses are induced due to the fringing effect of the air gap. The higher the switching frequency, the stronger the fringing effect. The CLL resonant converter is a potential alternative solution for front-end dc–dc converters. The CLL resonant converter is studied with a full-bridge configuration in [10]. The design methodology is limited to zero-current switching (ZCS) applications where insulated-gate bipolar transistors are employed, and it is not suitable for high-frequency applications where MOSFETs are used. In addition, the impact of the holdup time operation is not considered. An asymmetrical PWM ZVS CLL converter is proposed in [11] and [12]. The asymmetrical operation introduces high rms currents and high turnoff

0278-0046/$26.00 © 2010 IEEE

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currents, which cause high conduction loss and turnoff loss. An extra snubber capacitor is needed to reduce the high turnoff loss, which increases the cost and complexity of the whole system. This paper proposes a symmetrical-duty-cycle frequencycontrolled CLL resonant converter. Using this control mode, lower rms current and turnoff currents can be achieved. This leads to much lower conduction loss and switching loss than that in an asymmetrical PWM-controlled converter. In addition, snubber capacitors and complicated design are not required. Based on the symmetrical operation mode, it is possible to achieve ZVS for the entire load range. Meanwhile, the air gap in the transformer is omitted to eliminate the fringing effect. Moreover, because of very high magnetizing inductance, the transformer’s primary-side current is in phase with the secondary-side current. Thus, the SR can be easily driven. Hence, higher efficiency and higher power density can be achieved. This paper is organized as follows. The basic characteristics of the proposed CLL resonant converters are discussed in Section II. A novel optimization design methodology of CLL resonant converters is presented in Section III. Section IV presents the optimal transformer structure for CLL resonant converters. A current-type SR drive scheme is proposed in Section V. Finally, the experimental results are discussed in Section VI. An 800-kHz 250-W prototype is built to verify the proposed optimal design method, the transformer structure, and the proposed SR driving scheme. Using this prototype, up to a 96.7% efficiency is achieved.

Fig. 1. CLL resonant converter.

Fig. 2. Basic characteristics of the CLL resonant converter. (a) Equivalent circuit of CLL resonant converter. (b) CLL resonant converter’s gain curves.

7) Parallel resonant frequency f02 = 1/(2π · L1 · C1 ).

(7)

8) Quality factor Q = Z0 /(n2 · Ro ).

(8)

II. C HARACTERISTICS OF CLL R ESONANT C ONVERTER The topology of the CLL resonant converter is shown in Fig. 1. The main relationships in the CLL resonant converter are given in (1)–(9), where ωs is the switching angular frequency, Ro is the load resistor, and Ts is the switching period. 1) Normalized voltage gain M = 2Vo · n/Vin .

(1)

9) Normalized characteristic angular frequency ωn = ωs /ωo = fs /fo .

Fundamental mode approximation is used for resonant tank analysis. Based on the equivalent circuit shown in Fig. 2(a), the voltage gain expression of the CLL resonant converter is deduced as follows:

2) Resonant inductor ratio Ln = L1 /L2 .

(2)

3) Equivalent resonant inductor Leq = L1 · L2 /(L1 + L2 ).

(3)

5) Characteristic impedance Z0 = Leq /C1 .

(4)

(5)

6) Characteristic angular frequency ωo = 2πfo = 2π/T0 = 1/ Leq C1 .

M=

nVo Vin 2

= (1+L )2 n · Ln

. 2 π 2 2 8 Q (1 − ωn ) · jωn + 1 − (1 + Ln ) · ωn −(1 + Ln ) · ωn2

(10)

4) Equivalent characteristic inductor LP = L21 /(L1 + L2 ) = Leq · Ln .

(9)

(6)

The gain curves of the CLL resonant converter are plotted in Fig. 2(b). There are two resonant frequencies for CLL resonant converters. One is the series resonant frequency, whose value is equal to the characteristic frequency. The other resonant frequency is the parallel resonant frequency. The parallel resonant frequency is introduced by L1 and C1 and is defined as f02 . The operation regions of CLL resonant converters could be divided into three parts, as shown in Fig. 2. These operation regions are the ZCS region, the ZVS1 region, and the ZVS2 region.

HUANG et al.: HIGH-FREQUENCY HIGH-EFFICIENCY CLL RESONANT CONVERTERS WITH SRs

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contributes to the ZVS operation. When S1 is turned off, Vs2 drops sharply. However, due to the conduction of the SR, Vm is clamped to nVo . During the MOSFET’s transition dead time, VC1 changes very little. As a consequence, the voltage across L2 becomes very high. iL2 drops quickly until it reaches zero. It can be observed that high di/dt will be generated if the L2 value is small. Therefore, this region is not preferred with the design of a small L2 . The point at which the switching frequency equals the resonant frequency is very important. This point is the optimal point of the frequency range for minimal switching loss and circulating energy. Thus, at the nominal condition, the CLL resonant converter should be designed to operate close to the resonant frequency. At the resonant frequency [shown by a black dot in Fig. 2(b)], according to (10), the voltage gain is derived as M = 1 + 1/Ln .

Fig. 3. Waveforms of CLL resonant converter at each operation region. (a) ZCS region. (b) ZVS1 region. (c) ZVS2 region. (d) At resonant frequency with full load. (e) At resonant frequency with no load.

As shown in Fig. 3(a), in the ZCS region, the primary-side switches (S1 , S2 ) can achieve ZCS. During [0, tr ], L1 , L2 , and C1 resonate with each other. During [tr , Ts /2], L1 resonates with C1 , and iC1 turns negative before S1 is turned off. As a result, iC1 goes through D1 , which is the body diode of S1 . At Ts /2, S2 is turned on, and D1 will be turned off. The hard turnoff of the MOSFET body diodes generates severe reverserecovery loss and high-voltage stress. Thus, this operation region should be avoided for MOSFETs. As shown in Fig. 3(b), in the ZVS1 region, the primaryside switches (S1 , S2 ) can achieve ZVS. During [0, Ts /2], Vs2 and Vo1 are positive. During [0, tr ], L1 , L2 , and C1 resonate. During [tr , Ts /2], L1 resonates with C1 . At Ts /2, iC1 remains positive. When S1 is turned off, iC1 charges and discharges the junction capacitors of S1 and S2 , respectively. Hence, ZVS is achieved. In this region, an output rectifier can achieve ZCS. This suggests that low di/dt is beneficial for rectifiers. The waveforms of the CLL resonant converter in the ZVS2 region are plotted in Fig. 3(c). The primary-side switches (S1 , S2 ) can also achieve ZVS. During [0, Ts /2], Vs2 and Vo1 are positive. During [0, Ts /2], L1 , L2 , and C1 resonate. At Ts /2, iC1 is still positive. When S1 is turned off, iC1

(11)

The voltage gain value at the resonant frequency is independent of the load. The waveforms of the heavy-load and noload conditions at this point are shown in Fig. 3(d) and (e), respectively. Equation (12) is derived from the circuit drawn in Fig. 1. From Fig. 3(d) and (e), the boundary conditions are represented in (13). C1 · d(Vindt−Vm ) = iC1 , L1 · didtL1 = Vm (12) L2 d(iC1dt−iL1 ) = Vm − Vo1 iL1 (0) = −iL1 T2s , iC1 (0) = iL1 (0) Ts (13) Vo 2 2 [iC1 (t) − iL1 (t)] dt = n·R . Ts · 0 o Thus, the current expressions at the series resonant frequency are deduced in

⎧ (L1 +L2 )ωs πL2 Vin ⎪ i (t) = · sin(ω t) − cos(ω t) 2 s s ⎪ L1 n2 Ro 4ωs L1 ⎪ ⎪ ⎨ Vin Ts t − + 2L 4 1 (L1 +L2 )ωs ⎪ πL2 ωs C1 Vin ⎪ (t) = · sin(ω t) − cos(ω t) i ⎪ 2R C1 s s 4L n ⎪ 1 o ⎩ iC1 (t) = iL1 (t) + iL2 (t). (14) At the MOSFETs’ transition dead time, t = 0, t = Ts /2, and iL1 = 0. Thus, iC1 = iL1 and is derived in (15). This current charges and discharges the junction capacitors of the primaryside MOSFETs. During the dead time, since iC1 and iL1 are independent of the load, ZVS can be achieved for the entire load range with the proper design. Ts Ts = iL1 |iC1 (0)| = |iL1 (0)| = iC1 2 2 =

Vin To L1 + L2 . 2 4 L21

(15)

Physically speaking, all three resonant elements resonate during power delivery. When the output rectifiers are off, only two elements (L1 and C1 ) resonate. In contrast, for existing LLC resonant converters, two series-resonant elements

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resonate during power delivery. When the output rectifiers are off, all three resonant elements resonate. Due to the very different operation scenario for the proposed CLL resonant converter, the voltage gain at the resonant frequency is 1 + 1/Ln . The voltage boost capability at the resonant frequency may be very useful for high-voltage applications. The benefits of the topology difference in the transformer design and of being SR driven are discussed in Sections IV and V. III. D ESIGN M ETHODOLOGY FOR CLL R ESONANT C ONVERTERS There are many papers that present different design methods for the LLC resonant converter. In [13], LLC resonant converters are designed with a numeric processing scheme. In this scheme, resonant tank parameters are chosen based on a numerically determined minimum input power with a given output power. Nevertheless, this method relies purely on numeric analysis and is hence very complicated. It requires tremendous programming work. Furthermore, even with dedicated iterations, only the primary rms current is taken into account; the switching loss and secondary-side rms current are not considered. Thus, it is desirable to further improve the process of optimization. Reference [14] gives a design method based on start-up current, efficiency, and holdup time requirements. The combination of Ln and Q impacts the efficiency, and this paper uses these variables to present a trend of achieving high efficiency. However, the suitable range that is given for Ln and Q is based on observation. Thus, the precise optimal efficiency point cannot be obtained, and trial and error iterations are still necessary for this design strategy. Lu et al. [15] provide a design method based on efficiency and holdup time requirements. However, the effects of dead time and device characteristics on the system efficiency are ignored in both [14] and [15]. Thus, the Ln and Q curves plotted in these papers are actually not very accurate at high switching frequencies. The optimal design methodology for CLL resonant converters presented in this paper is based on the requirement of high efficiency and the need to accommodate holdup time operation. This design achieves high efficiency over a wide load range.

In accordance with (14) and (15), assuming there is zero dead time, the primary-side and secondary-side rms currents are derived in ⎧ 4 2 2 ⎪ Ro Ts 2Vo Vin Vo ⎪ ⎨ IRMS_P = 4√1 2 R + 4π 2 V 2V L2P o in o (16) 4 2 2 ⎪ Ro Ts ⎪ Vin ⎩ IRMS_S = π Vo 5π2 −48 + 1. 4 Ro 12π 2 2Vo π 2 L2 P

In (16), IRMS_P and IRMS_S are the primary-side rms current and the secondary-side rms current, respectively. Vin and Vo represent the input voltage and the output voltage, respectively, and Ro represents the full load resistance. LP should be designed to be large to reduce device rms currents. B. RMS Current With Consideration of Dead-Time Period For high-frequency operation, the dead time tdead is so critical that it affects the design considerably. During tdead , no energy is transferred to the load. Thus, a large dead time causes less of an energy transfer interval at the same switching frequency than does a smaller dead time. This leads to higher rms current for the same energy transfer. This dead-time effect should not be ignored. Hence, (16) provides only approximate results for low frequencies or systems with very small tdead . With the consideration of tdead , the expressions of the primaryside and secondary-side rms currents can be deduced using (17) shown at the bottom of the page. C. Dead-Time Influence on RMS Current and Turnoff Current During tdead , the junction capacitor of the primary-side devices will be charged and discharged to achieve ZVS. Ceq equals the junction capacitance of one primary-side MOSFET. During a short tdead , the current of L1 , i.e., iL1_ max , remains almost the same and is equal to the primary-side turnoff current Iturnoff . Ts Vin Ts L1 + L2 = Iturnoff = |iL1 (0)| = iL1 2 2 4 L21 =

A. RMS Current Without Consideration of Dead-Time Period If the switching frequency is low, the dead time (tdead ) is much shorter than the switching period (Ts ). For the sake of simplicity, we treat the switching period Ts as approximately the resonant period To at the resonant point.

⎧ ⎪ ⎪ ⎨ IRMS_P =

Vo2 2 2 Vin Ro

⎪ ⎪ ⎩ IRMS_S =

√ 3 Vo 12 Ro

1 √

·

·

Vin 2Vo

Vin 2Vo

4

4

Ro2 To2 L2P

To Vin . 8 Lp

(18)

Iturnoff helps to achieve ZVS and should be large enough to charge and discharge the junction capacitors during tdead . Iturnoff × tdead ≥ 2Ceq Vin .

+ 4π 2 +

(5π 2 −48)Ro2 To3 L2P (To +2tdead )

+

16π 2 (To tdead +t2dead ) To2

12π 4 To To +2tdead

+

48π 4 (To tdead +t2dead ) To (To +2tdead )

(19)

(17)


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Substituting (18) into (19), we get Lp ≤

To · tdead . 16Ceq

(20)

To achieve ZVS, LP should satisfy (20). Meanwhile, a large LP is preferred for low conduction loss. Hence, LP should be chosen as To · tdead /16Ceq . Applying LP = To · tdead /16Ceq to (17), we get (21) shown at the bottom of the page. Td_norm and ZC _norm are defined as follows: Td_norm = tdead /Ts 2 Vin 1 Ro · . ZC _norm = Ceq ωs 2Vo

Fig. 4. RMS current calculation results. (a) Primary-side rms current with and without consideration of dead-time period. (b) Normalized primary-side and secondary-side rms currents considering dead-time period.

(22)

less circulating current is achieved. On the other hand, a larger Td_norm causes a smaller power delivery duty cycle. To provide the same energy to the load, higher power is required during the shorter power delivery period, which leads to higher current. Taking the aforementioned two aspects into consideration, the relationship between Td_norm and the primary-side rms current exhibits a U shape. There is an optimal dead time at which the lowest rms current can be achieved. This optimal dead time is identified in the following paragraph. With simple algebra, the normalized dead time for the minimal primary-side rms current and secondary-side rms current can be calculated using ⎧ 2 ⎪ 4 + 3 π 4 ZC ⎨ Td_norm_ min _prim = 2 _norm (26) 2 π 2 3 12·ZC _norm ⎪ ⎩ Td_norm_ min _ sec = 1 2+ 4 . 2 5π −48

(23)

ZC _norm indicates the impedance relationship of the junction capacitor of the device and the load. By substituting (22) and (23) into (21) and normalizing (21) by the factors Po /0.5Vin and Po /Vo , (24) shown at the bottom of the page can be derived. Po equals Vo2 /Ro . Hence, it is expedient to apply normalized current to evaluate the performance. By applying (22), (23), and LP = To · tdead /16Ceq to (18) and normalizing by the factor Po /0.5Vin , (15) can be deduced. ITurnoff _norm =

1 1 2 . π Td_norm ZC _norm

(25)

Fig. 4(a) shows the difference in the primary rms current with and without the consideration of tdead . The dashed line is obtained from (16), and the dotted line is based on (17). As we can see, tdead plays a significant role in a high Td_norm range or a high-frequency range. Fig. 4(b) shows the normalized primary-side rms current IRMS_P_norm and secondary-side rms current IRMS_S_norm . Td_norm influences the primary-side rms current in two ways. On the one hand, based on (22) and (18), a large Td_norm means a large Lp , and less Iturnoff is required to achieve ZVS. Hence,

⎧ ⎪ ⎪ ⎪ ⎪ ⎨ IRMS_P =

Vo2 2 2 Vin Ro

⎪ ⎪ ⎪ ⎪ ⎩ IRMS_S =

√ 6 Vo 24π Ro

1 √

⎧ ⎪ ⎪ ⎨ IRMS_P_norm = ⎪ ⎪ ⎩ IRMS_S_norm =

1 √

6 24π

Vin 2Vo

4 2 √

·

Vin 2Vo

4

4

2

2

16Ceq

1 Td_norm

8 π 8 π

2

2

2

(To +2tdead )

1 2 ZC _norm 1 2 ZC _norm

16π 2 (To tdead +t2dead ) To2

(21)

(5π 2 −48)Ro2 To3

To ·t

Td_norm

The design method is based on the requirements of high efficiency and holdup time. The device losses are a major part of the system losses. Based on (24) and (25), we know that the conduction loss and switching loss of the devices are related to the output power, the characteristics of the devices, the

ToR·to To 2 + 4π 2 + dead

dead 16Ceq

1

D. Design Methodology

+

+

12π 4 To To +2tdead

+

48π 4 (To tdead +t2dead ) To (To +2tdead )

4π 2 (1−2Td_norm )2

(5π 2 − 48)(1 − 2Td_norm ) +

(24) 12π 4 1−2Td_norm

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Fig. 5. Design relationship. (a) Ratio of device loss and power versus dead time under different loads. (b) Q and Ln relationship for ZVS requirement.

switching frequency, and the dead time. In particular, (24) indicates that the conduction losses of the primary- and secondaryside devices are not influenced by the resonant tank design. According to (25), the turnoff loss of the primary-side device is determined by the dead-time design, but it is not affected by the resonant tank parameters. Therefore, the device losses are independent of the resonant tank design. For given output power, devices, and switching frequency, the device losses can be obtained using the dead-time design. The conduction losses of the devices can be easily calculated by (24). The losses can be normalized by the output power. Pcond_loss_P and Pcond_loss_S indicate the primary-side and secondary-side conduction losses, respectively. Rdson_p and Rdson_s indicate the turn-on resistances of the primary-side and secondary-side devices. Pcond_P_norm and Pcond_S_norm indicate the normalized primary-side and secondary-side conduction losses ⎧ P ⎪ Pcond_P_norm = condP_oloss_P ⎪ ⎪ ⎪ ⎪ ⎨ = Rdson_p 2Vo 2 I 2 RMS_P_norm Ro Vin (27) Pcond_loss_S ⎪ ⎪ P = cond _ S _ norm ⎪ Po ⎪ ⎪ ⎩ = Rdson_s I 2 . RMS _ S _ norm Ro Equation (25) shows the relationship between the dead time and turnoff current. The turnoff loss can be attained either by precise device simulation or by a circuit test. In this paper, the device turnoff loss is obtained by experimental measurement. A design example is given to show the proposed optimal design procedure. The design specifications are Vin = 400 V, Vo = 12 V, and Po = 250 W. The switching frequency is 800 kHz for the sake of high power density. STB12NM50FD (Ceq = 142 pF) and BSC014N03MSG are chosen as the primary- and secondary-side devices. Based on (25), (27), and the device test results, Fig. 5(a) shows the device loss percentage curves with variations in dead time. According to the 80 Plus requirement [1], high efficiency should be achieved at 20%, 50%, and 100% load conditions. A suitable value for the dead time should be chosen to satisfy the high efficiency requirement. Hence, a dead time that falls within the shaded area is recommended for better efficiency over a wide load range. Based on Fig. 5(a), a dead time of 170 ns is chosen. Once the optimal dead time is selected, (20) can be used to determine that LP = 67.6 μH. Because the switching fre-

Fig. 6. Peak gain curves of different combinations of Q and Ln . (a) Peak gain for fixed Ln . (b) Peak gain for different Ln ’s.

Fig. 7.

Three-dimensional plots of the proposed design method.

quency is 800 kHz, the series resonant frequency fo is 1.1 MHz with the consideration of the dead time. For a given LP , the relationship between Q and Ln can be expressed as 2 2Vo 2πfo (1 + Ln )2 = LP · . (28) Q· Ln Vin Ro In this case, Q · (1 + Ln )2 /Ln = 2.918 is obtained because LP = 67.6 μH. The relationship between Q and Ln is plotted in Fig. 5(b). To complete the resonant tank design, Q and Ln should be determined. The holdup time operation requirement is another resonant tank design constraint. In general, for each Q, the maximum gain is achieved at the resonant ridge, as shown in Fig. 6(a). The peak gain curves of different Ln ’s are drawn in Fig. 6(b). The peak gain decreases as Q increases when Ln is fixed. Meanwhile, the peak gain increases as Ln decreases for the same Q. Fig. 7 shows the peak gain surface for different values of Q and Ln , as well as the gain plane of the holdup time operation constraint. In this design, the holdup time gain is adopted as 1.8. Thus, a peak gain surface higher than 1.8 can be considered. Equation (28) and Fig. 7 are determined by the high efficiency constraint, which should be recalled to finalize the resonant tank design. Fig. 7 shows the holdup time gain constraint and the high-efficiency operation constraint. The final optimal design point is located at the intersection of the three surfaces, which is where all requirements can be satisfied. If this design point moves up along the boundary line of the peak gain surface and the high-efficiency constraint surface, the voltage conversion range is enlarged and the efficiency of the converter


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Fig. 10. LLC resonant converter with integrated Lm . Fig. 8. Circuit stresses at different values of Ln . (a) Primary-side peak current. (b) Peak voltage of resonant capacitor.

Fig. 11. LLC resonant converter transformer. (a) Transformer structure. (b) FEA simulation result.

IV. T RANSFORMER D ESIGN I NVESTIGATION Fig. 9.

Design procedure of the CLL resonant converters.

is kept the same. If this occurs, the impacts of design point selection should be studied further. During the holdup time operation, the primary-side peak current is normalized by the factor Po /0.5Vin ; this current is plotted in Fig. 8(a). The maximum voltage gain is achieved close to the parallel resonant frequency f02 . The primary-side peak current at f02 increases as Ln increases. If Ln 1, based on √ (3) and (7), it can be derived that Leq ≈ L2 and f02 ≈ f0 / Ln . The frequency operation range during the holdup time also increases. In one switching cycle, the energy transfer period is close to T0 due to the nature of resonance. If the switching frequency moves farther from the series resonant frequency, the effective energy transfer duty cycle is reduced, which results in a higher current. Roughly, the peak √ current is inversely proportional to f02 or proportional to Ln . Normalized by the factor 0.5Vin , Fig. 8(b) shows how the peak voltage of the resonant capacitor changes during the holdup time operation. The peak voltage decreases as Ln increases. to Ln . Based on (4)–(7), we know that C1 is proportional √ Since the peak current is roughly proportional to Ln during the holdup time, the increase in the capacitance is greater than the increase in the current going through the capacitor. Thus, the voltage stress decreases. Normally, a narrow frequency operation range and low current stress are preferred. Thus, the black dot in Fig. 7, where Ln equals 17 and Q equals 0.153, is chosen as the optimal design point. According to (2)–(8), the resonant tank parameters can be calculated as L1 = 74.06 μH, L2 = 4.35 μH, and C1 = 5.09 nF. Based on (11), the transformer turn ratio is 18 : 1. The optimal design procedure is summarized in Fig. 9.

For the CLL resonant converter transformer design, two factors need to be taken into consideration. First, the magnetizing inductance of the transformer should be designed to be as high as possible. Second, the leakage inductance of the transformer could be utilized as Lr . The basic configuration of the transformer is as follows: Litz wires are utilized as the primary-side winding for their ability to reduce the skin effect caused by high-frequency current. Printed circuit board (PCB) winding is utilized on the secondary side for the easy connection of high-current devices. As shown in Fig. 10, for a conventional LLC resonant converter, Lm is usually integrated into the transformer with the insertion of an air gap. A discrete inductor is required for Lr . However, the air gap will cause a high eddy current in the PCB windings and, hence, high winding loss [16]. The LLC resonant converter transformer structure is shown in Fig. 11(a), where the rounded winding is the primary-side litz wire and the center two plates are the secondary-side PCB winding. The primary-side and secondary-side windings are interleaved for lower ac winding loss. The thickness of the core is 2 mm (from the inner side to the outer side), and the window area of the core is 50 mm2 . The width of the PCB copper is 7 mm, and it has a weight of 4 oz. The diameter of the litz wire is 0.5 mm (AWG 24). We chose Maxwell 2-D-based finite element analysis (FEA) to investigate the winding loss. The secondary PCB winding loss is 2.89 W (23.1% of the system loss) for a 250-W LLC transformer with an air gap. Fig. 11(b) shows a large eddy current that occurs at the edges of the copper plates near the air gaps. For the CLL resonant converter transformer design, there is no need to utilize magnetizing inductance (as shown in Fig. 1). Thus, air gaps and the associated fringing effect can be eliminated. The optimal design of the separate L1 for small size and high efficiency can be achieved easily. The next issue

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Fig. 12. CLL resonant converter transformer without interleaving windings. (a) Transformer structure. (b) FEA simulation result.

Fig. 14. CLL resonant converter transformer with interleaving windings and magnetic shunt. (a) Transformer structure. (b) FEA simulation result.

Based on the aforementioned analysis and comparison, the proposed transformer structure is very suitable for the CLL resonant converter. For the planar transformer, it may not be favorable to integrate the magnetizing inductance due to the severe fringing effect. However, the leakage inductance can be easily integrated without an apparent sacrifice in performance. The proposed CLL resonant converter can fully utilize the optimal integration solution of the magnetic components, which is an inherent merit of this topology. Fig. 13. CLL resonant converter transformer with interleaving windings. (a) Transformer structure. (b) FEA simulation result.

is determining how to integrate L2 into the transformer without suffering too much loss. Fig. 12(a) shows the transformer structure without interleaving, and Fig. 12(b) shows the FEA simulation results. Without an interleaving structure, the secondary PCB conduction loss is 2.82 W (22.6% of the system loss), and the leakage inductance is 4.14 μH. The transformer structure with interleaving is shown in Fig. 13(a), and the FEA simulation results are shown in Fig. 13(b). The conduction loss is 1.59 W (12.7% of the whole system loss), and the leakage inductance is 1.94 μH. The interleaving structure of the transformer makes the magnetomotive force (MMF) more evenly distributed but with a significant reduction of the leakage inductance. The leakage inductance is mainly generated by the magnetic energy stored in the space between the primary-side and secondary-side windings. In an interleaving structure, the energy is small due to low MMF. To increase the leakage inductance, a magnetic shunt with higher permeability is adopted. A ferrite polymer composite (FPC) film with μr = 9 is used as a magnetic shunt. Fig. 14(a) shows the transformer with an interleaving structure and a magnetic shunt. The FEA simulation results are shown in Fig. 14(b). The two gray bars between the primaryside and secondary-side windings represent the magnetic shunt layers. The conduction loss of the secondary PCB winding is 1.74 W (13.9% of the system loss), and the leakage inductance is 3.89 μH. The leakage inductance of the transformer with magnetic shunts is double that of the transformer without magnetic shunts. The magnetic shunt layers attract more leakage flux. However, due to limited permeability, the induced leakage flux bends slightly. The leakage flux induces an eddy current at the edge of the copper plates. Fortunately, the leakage flux is very low. Thus, only a 0.15-W loss is added, which is acceptable for a 250-W converter.

V. S YNCHRONOUS R ECTIFICATION D RIVING S CHEME For conventional LLC resonant converters, it is not easy to apply a current-drive SR. Otherwise, discrete magnetic components should be applied. Unlike existing LLC resonant converters, the magnetizing inductance of the proposed CLL resonant converter is very large. The impact of the phase mismatch between the primary-side and secondary-side currents of the transformer can be ignored. Thus, the transformer’s primaryside current can be utilized directly to drive the SR. Fig. 15(a) shows a diagram of the SR driving scheme, and Fig. 15(b) shows the schematic of the SR driving circuit. A CT is used to sense the primary-side current, and comparators and simple peripheral circuits are utilized as Schmitt triggers. Unlike the conventional LLC resonant converter, there is no conflict between the current-driven SR and the integration of magnetic components. This is another inherent benefit of the proposed CLL resonant converter. VI. E XPERIMENTAL R ESULTS A 250-W 800-kHz 400-V/12-V CLL resonant converter prototype is built to verify the theoretical analysis and the proposed design strategies. The resonant parameters are designed as follows: L1 = 73 μH, L2 = 4.4 μH, and C1 = 5 nF. The transformer turn ratio is 18 : 1 : 1. The core material is 3F45. L2 is integrated with the transformer. The relative permeability of the FPC is nine. For L1 [17], an RM8/ILP with 3F45 is chosen, and 24-turn AWG-26 litz wires are used. The power density of the prototype is 94.6 W/in3 . The part number of the primary-side and secondary-side devices are STB12NM50FD and BSC014N03MSG, respectively. Fig. 16(a) shows the experimental results of the CLL resonant converter at a no-load condition. ZVS is achieved during the dead time between the marked lines. Vds_s1 and Vds_s2 are the drain–source voltages of S1 and S2 , respectively. Vgs_s1 and Vgs_s2 are the gate–source voltages of S1 and S2 , respectively.


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Fig. 15. CLL resonant converter with SR driving scheme. (a) CLL resonant converter. (b) Schematic of SR driving scheme.

Fig. 16. Experimental waveforms of prototype. (a) 400 V/12 V, no load. (b) 400 V/12 V, 250-W full load.

When the drain–source voltage drops to zero, the gate signal starts to drive. The dead time is 160 ns, and the turnoff current is around 0.68 A. Fig. 16(b) shows the experimental results of the CLL resonant converter at the full-load condition. VQ2 is the driving signal of Q2 . VdsQ2 represents the drain–source voltage of Q2 . The primary-side current iL2 has the same shape as the secondary-side current, but it has a different amplitude due to the turn ratio. iL2 is in a sinusoidal shape. As the dotted line indicates, VdsQ2 begins to rise just at the zero-cross point of the sinusoidal current. Hence, ZCS is achieved. It can also be observed that the SR body-diode conduction time is almost eliminated. The experimental efficiency curve of the prototype is shown in Fig. 17. The efficiency at a half load is 96.7%, and at a full load, it is 96.1%. The holdup time capacitor is 56 μF for a 250-W converter, and the input voltage range is 415–220 V. The voltage ripple is around ±15 V. Based on this voltage ripple, the switching frequency range is 725–900 kHz. Based on calculation, the efficiency at 725, 800, and 900 kHz (fixed frequency) is 95.9%, 96.3%, and 95.7%, respectively. As the frequency variation is not significant, the efficiency of the converter will change little. The proposed optimal design procedure is valid. A detailed loss breakdown under full-load conditions is shown in Table I. VII. C ONCLUSION This paper has proposed a high-frequency high-efficiency CLL resonant converter. The characteristics of the CLL resonant converter are analyzed, and the operation regions of

Fig. 17. Measured efficiency curve for the constructed CLL resonant converter. TABLE I LOSS BREAKDOWN OF THE HARDWARE UNDER FULL LOAD

the CLL resonant converter are discussed. Recognizing that dead time is a critical factor that influences the entire system design and using thorough investigation, an optimal design methodology is proposed to achieve high efficiency over a wide load range. An optimal transformer structure for the CLL resonant converter is proposed to achieve low winding loss and to have the capability of magnetic integration, and an easily implemented current-type SR driving scheme is proposed to achieve low SR losses. An 800-kHz 250-W CLL resonant converter prototype is built to verify the benefits of the proposed CLL resonant converters, and over a 96% efficiency is achieved for the wide load conditions of interest. The proposed CLL resonant converter is a good candidate for next-generation highfrequency high-efficiency high-power-density power supplies.

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R EFERENCES [1] Efficient Power Supplies for Data Center and Enterprise Servers. [Online]. Available: http://www.80plus.org [2] L. D. Salazar and P. D. Ziogas, “A high-frequency two-switch forward converter with optimized performance,” IEEE Trans. Ind. Electron., vol. 37, no. 6, pp. 496–505, Dec. 1990. [3] X. Ruan and Y. Yan, “Soft-switching techniques for PWM full bridge converters,” in Proc. IEEE PESC, 2000, vol. 2, pp. 634–639. [4] M. K. Kazimierczuk, “Class D voltage-switching MOSFET power amplifier,” Proc. Inst. Elect. Eng.—B, vol. 138, no. 6, pp. 285–296, Nov. 1991. [5] B. Yang, F. C. Lee, A. J. Zhang, and G. Huang, “ LLC resonant converter for front end dc/dc conversion,” in Proc. IEEE APEC, 2002, pp. 1108–1112. [6] Y. Gu, Z. Lu, L. Hang, Z. Qian, and G. Huang, “Three-level LLC series resonant dc/dc converter,” IEEE Trans. Power Electron., vol. 20, no. 4, pp. 781–789, Jul. 2005. [7] D. Fu, Y. Liu, F. C. Lee, and M. Xu, “A novel driving scheme for synchronous rectifiers in LLC resonant converters,” IEEE Trans. Power Electron., vol. 24, no. 5, pp. 1321–1329, May 2009. [8] X. Xie, J. C. P. Liu, F. N. K. Poon, and M. H. Pong, “A novel high frequency current-driven synchronous rectifier applicable to most switching topologies,” IEEE Trans. Power Electron., vol. 16, no. 5, pp. 635–648, Sep. 2001. [9] X. Wu, B. Li, Z. Qian, and R. Zhao, “Current driven synchronous rectifier with primary current sensing for LLC converter,” in Proc. IEEE ECCE, 2009, pp. 738–743. [10] C. Chakraborty, M. Ishida, and T. Hori, “Performance, design and pulse width control of a CLL resonant dc/dc converter operating at constant frequency in the lagging power factor mode,” in Proc. IEEE Int. Conf. Power Electron. Drive Syst., 1999, pp. 767–772. [11] D. J. Tschirhart and P. K. Jain, “A CLL resonant asymmetrical pulsewidth-modulated converter with improved efficiency,” IEEE Trans. Ind. Electron., vol. 55, no. 1, pp. 114–122, Jan. 2008. [12] D. J. Tschirhart and P. K. Jain, “A cost-effective synchronous rectifier gating signal scheme for constant frequency resonant converters,” in Proc. IEEE Ind. Electron. Conf. Symp., Jul. 2006, pp. 1235–1240. [13] H. de Groot, E. Janssen, R. Pagano, and K. Schetters, “Design of a 1-MHz LLC resonant converter based on a DSP-driven SOI half-bridge power MOS module,” IEEE Trans. Power Electron., vol. 22, no. 6, pp. 2307– 2320, Nov. 2007. [14] T. Liu, Z. Zhou, A. Xiong, J. Zeng, and J. Ying, “A novel precise design method for LLC series resonant converter,” in Proc. IEEE INTELEC, 2006, pp. 1–6. [15] B. Lu, W. Liu, Y. Liang, F. C. Lee, and J. D. van Wyk, “Optimal design methodology for LLC resonant converter,” in Proc. IEEE APEC, 2006, pp. 19–23. [16] C. Yan, F. Li, J. Zeng, T. Liu, and J. Ying, “A novel transformer structure for high power, high frequency converter,” in Proc. IEEE PESC, 2007, pp. 214–218. [17] C. W. T. McLyman, Transformer and Inductor Design Handbook, 3rd ed. New York: Marcel Dekker, 2004. [18] M. K. Kazimierczuk and T. Nandakumar, “Class D voltage-switching inverter with tapped resonant inductor,” Proc. Inst. Elect. Eng.—B, vol. 140, no. 3, pp. 177–185, May 1993.

Daocheng Huang received the B.S. and M.S. degrees from the Huazhong University of Science and Technology, Wuhan, China. He is currently working toward the Ph.D. degree at Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg. His research interests include high-frequency power conversion, soft switching techniques, magnetic design, passive integration, distributed power systems, and telecom power conversion techniques.

Dianbo Fu (M’09) received the B.S. degree from the Huazhong University of Science and Technology, Wuhan, China, and the M.S. and Ph.D. degrees from Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg. Since 2010, he has been with Huawei Technologies, Plano, TX, where he has been engaged in product design, research, and development. He is the holder of two U.S. patents and has three U.S. patents pending. His research interests include high-frequency power conversion, soft switching techniques, magnetic design, electromagnetic interference, distributed power systems, and telecom power conversion techniques.

Fred C. Lee (S’72–M’74–SM’87–F’90) received the B.S. degree in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1968, the M.S. and Ph.D. degrees in electrical engineering from Duke University, Durham, NC, in 1972 and 1974, respectively. He is a University Distinguished Professor with Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg. He directs the Center for Power Electronics Systems, a National Science Foundation engineering research center. He is the holder of 35 U.S. patents and has published over 200 journal articles and more than 500 technical papers in conference proceedings. His research interests include high-frequency power conversion, distributed power systems, electronics packaging, and modeling and control.

Pengju Kong (M’08) received the B.S.E.E. and Ph.D. degrees from Tsinghua University, Beijing, China, in 2003 and 2009, respectively. He is currently a Postdoctoral Associate with the Center for Power Electronics Systems, Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg. His research interests include electromagnetic interference/electromagnetic compatibility in power electronics systems, magnetics, and micro grid.