2015 20th IEEE European Test Symposium (ETS)
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High Frequency Jitter Estimator for SoCs Hervé Le Gall ST Microelectronics, 12 Rue Jules Horowitz, 38000 Grenoble, France
[email protected]
Abstract!This paper presents an Embedded Test Instrument (ETI) for the estimation of the High Frequency (HF) jitter of an observed clock signal. The ETI uses a second reference clock for under-sampling the observed signal similar to previous approaches. However, the analysis of the test response does not require the construction of the Cumulative Distributed Function (CDF) of the jitter as in previous approaches. Instead, the HF jitter of the input observed signal is transformed at the output of the ETI into a digital value that corresponds to a number of unwanted signal transitions. We demonstrate in this paper that the transfer function of the ETI defined by the ratio of the number of unwanted signal transitions and the input HF jitter is linear. This property leads to a simple circuit implementation. The linearity of the ETI is demonstrated firstly by behavioral simulation, using a theoretical model of the output of the undersampling process, and secondly by transistor-level simulation using the 65 nm CMOS bulk technology by ST Microelectronics. We also present experimental measurements that have been carried out using an FPGA-based test platform to validate the linearity of the transfer function in the presence of non-idealities that can affect the ETI. Finally, we demonstrate the exploitation of the ETI within Systems-on-Chip (SoCs) produced in highvolume by ST Microelectronics. Keywords!Jitter, jitter estimation, under-sampling, embedded test instruments, built-in self-test.
I.
INTRODUCTION
As CMOS technology scales down, higher operating frequencies and data rates are made possible, continuously putting pressure for the development of appropriate test schemes that guarantee high production yield, adequate test quality, and affordable test costs [1]. Testing for timing uncertainty of clock sources is mandatory. This is achieved by measuring, for example, Bit Error Rate (BER) [3-4] which is typically in the range of 10-12 to 10-15 for commercial chips. However, measuring BER in a production environment is very time-consuming. For this reason, the measurement of the Root Mean Square (RMS) value of random jitter (and more specifically Gaussian jitter) is typically carried out, and the BER value is derived from it [2]. Jitter in clock signals can be categorized into lowfrequency (LF) jitter (or cumulative jitter) and high-frequency (HF) jitter (or instantaneous jitter or cycle-to-cycle jitter). LF jitter leads to systematic errors that can be easily determined during test even with a low-cost Automatic Test Equipement (ATE). HF jitter leads to random errors that are more difficult to detect and can severally impact the operation of the device in the actual application. Several techniques for HF jitter
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Rshdee Alhakim, Miroslav Valka, Salvador Mir, Haralampos-G. Stratigopoulos, Emmanuel Simeu Univ. Grenoble Alpes, TIMA, F-38000 Grenoble, France CNRS, TIMA, F-38000 Grenoble, France @imag.fr
measurement can be found in the literature. In [9], an oversampling technique is presented which makes use of a highfrequency comparator that is externally triggered for sampling the observed signal. The rising/falling edges of the input signal are sampled at high frequency and the output of the comparator is analyzed to extract the RMS jitter. A major drawback of this approach is that signal sampling is externally controlled, making necessary the use of a highly accurate ATE, in addition to a clean reference clock (e.g. a clock with negligible or small jitter) to ensure a high measurement accuracy. In [5-6,10-12], several techniques are presented for the estimation of HF jitter using over-sampling Time-to-Digital Converters (TDC). Such architectures can reach the sub-gate resolution (e.g. < 1 ps) for advanced technology nodes. Herein, a reference clock is used again to sample the observed signal, however, the TDC output is analyzed on-chip to extract the RMS jitter. The accuracy of the measurement depends on the resolution of the TDC, which, in turn, is defined by the time delay of the TDC building blocks and the length of the analyzed test sequence. Although this approach can be timeefficient, it suffers from non-ideal effects in the TDC due to on-chip parameter variations, leading to circuit architectures that require higher silicon overhead and power consumption for compensating these effects. The use of signal under-sampling for HF jitter estimation has been considered by several works [7-8,13-15]. In this case, the TDC is replaced by a simple latch and the resolution of the measurement is defined by the difference between the period of the observed and the strobe signal. While this approach may require a longer test time, it results in an Embedded Test Instrument (ETI) with smaller silicon and power consumption overheads. However, the limitations of the approach due to non-idealities of the ETI must be studied. In this paper, we present an ETI for the estimation of the HF jitter of an observed clock signal. The signatures provided by the ETI during production testing are used to reject devices with potential timing faults. The ETI can operate in two modes. In the first mode, the ETI signatures are downloaded to the ATE and a test decision is made afterwards. In the second mode, the ETI operates as a Built-In Self-Test (BIST) function providing a direct pass/fail test decision. As opposed to previous works, the analysis of the test response in the ETI does not require the construction of the Cumulative Density Function (CDF) of the jitter. The HF jitter of the input observed signal is transformed at the output of the ETI into a
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digital value that corresponds to the number of unwanted signal ! transitions due to jitter. We demonstrate in this paper that the transfer function of the ETI defined by the ratio of the number of unwanted signal transitions and the HF jitter is linear. This property leads to a simple circuit implementation. The paper is organized as follows. Section II describes the under-sampling technique for the estimation of HF jitter. The linearity of the transfer function of the ETI is studied in Section III by simulation, firstly based on a theoretical model of the output of the under-sampling process and, secondly, based on transistor-level simulation using the 65 nm CMOS bulk technology by ST Microelectronics. Section IV describes the ETI implementation and the experimental set up. In Section V, we present experimental measurements based on an FPGA-based test platform aiming at validating the linearity of the transfer function in the presence of non-idealities that can affect the ETI. We also show results by deploying the ETI in Systems-on-Chip (SoCs), in order to measure the jitter of high-speed clock signals. Finally, Section VI concludes the paper and provides some directions for further work. II.
Fig. 2. Jitter-free beat signal.
UNDER-SAMPLING CONCEPT
The ETI is based on under-sampling the observed clock signal of frequency fobs by means of a reference clock signal of frequency fref, with fref being slightly lower than fobs [7]. The difference !"between the periods of both signals is given by: !" #$%& ' #()* "
+ &,-.
'
+ &/01
,
(1)
where Tref and Tobs are the periods of the reference and observed clock signals, respectively. As a result of the time difference !, the rising edges of both signals slide in time by a value ! with respect to each other during each clock period, as illustrated in Fig. 1. Initially, both rising edges are aligned, but their phase difference increases by a value ! after each clock period.
Fig. 1. Input signals of under-sampling process.
Fig. 2 illustrates the result of under-sampling the observed clock signal, in the case where there is no jitter in the clock signals. The result of the under-#$%&'()*" (#" $" +beat, signal with a frequency given by 234 " 3546 ' 3789 . The beat signal period can be expressed as follows: :4 "
+ 9;
"
+ 99?@A
"
B?@A 2C2B
