第七屆奈米工程暨微系統技術研討會
2003/11/20-21
High Gate Oxide Leakage and Its Capacitance-Voltage Characteristics Heng-Sheng HUANG (1), Shuang-Yuan CHEN (1), Hai-Chun LINE (1), Chia-Hung HUANG (1), Jen-Kon CHEN (2) (1) Institute of Mechatronics, National Taipei University of Technology, Taipei, Taiwan (2) Central Research/Development, United Microelectronics Corporation, Hsin-Chu, Taiwan Tel:02-27712171-2009 Email:
[email protected] 台北市忠孝東路三段一號機電所
ABSTRACT This work examines different components of the leakage currents in scaled N and P-channel metal oxide semiconductor field-effect transistors (MOSFET) with ultra-thin gate oxide. Experimental results show that the gate tunneling leakage current through the source/drain extension region (also named edge direct tunneling, EDT) is the most serious component. To clarify the relationships between this largest leakage component and the size of the source/drain to gate overlap region and oxide thickness, a capacitance–ratio method (C–R method) is used to precisely extract the dimension of the source/drain to gate overlap, Lov. The behavior of high gate oxide leakage on capacitance-voltage characteristics is also discussed. INTRODUCTION As the requirements of electronic
metal oxide semiconductor field-effect transistors (MOSFET) with ultra-thin
products becoming more complex, such as high speed and superior performance,
gate oxide. The considerations include several kinds of spatial and physical
innovations in process technology have progressed continuously. In order to
properties influenc ing gate direct tunneling leakage current, such as the
achieve these objectives, two of the important methods are the decreasing of
thickness of gate oxide, the source/drain to gate overlap, frequency, the RC delay,
channel length and the reducing of gate oxide thickness. But these approaches
the quantum thickness of the surface carrier layer and the poly depletion
may cause additional problems, for instances the short channel effects and
effect.
the gate direct tunneling leakage current. In this work, we focus our attention
EXPERIMENTS AND ANALYSIS As shown in Fig. 1, an “on-state
on studying gate direct tunneling leakage current phenomenon and its
“ NMOS device consists of three leakage paths, IS, ID and ISUB . By changing the
capacitance-voltage
gate biased voltages, their variations are
characteristics
in 416
第七屆奈米工程暨微系統技術研討會
2003/11/20-21
measured. Figure 2 shows the results.
high
Among them, IS,on ≒ ID,on ＞＞ISUB,on (IS,on≒ID,on, since the test devices have
capacitance can be easily seen. Nevertheless in Figure 7 & 8, the
symmetric structures). Because the thinnest effective oxide thickness is in
capacitance doesn’t drop so early in high frequency cases. A reasonable
the SDE overlap region, we can expect the maximum tunneling leakage
presumption is that the devices get some gate leakage to compensate their RC
happened there. Fig. 3 shows
relationship
delay so that the both sides of C-V curves are not decreasing abruptly. To
between measured SDE tunneling leakage and the Lov length. This implies
further analyze its reason, another model of RC circuit in Fig. 9 is presented
the 2D high electric field effects in this region and may result in the dielectric
emphasizing SDE effect.
damage in this poly gate edge. In order to further confirm the
However, though gate leakage current compensation in high frequency
situation, we gather various thicknesses of devices, their oxide layers from 6.5nm
is adopted, the capacitance value is still not fit to the ideal values. One reason
to 1.3nm. As indicated in Fig. 4, the measurement of IG increases abruptly
discussed above is about the horizontal RC delay of source/drain to channel
when oxide thickness becomes thinner. Obviously, this oxide layer thickness
route; the other reason is supposed to be the quantum effect. As Figure 10 shows：when device is biased at high VG,
the
reducing lets a numbers of energized carriers to tunnel through high insulator
the
frequency
quantum
cases,
the
tunneling
effect
smaller
leakage
of
energy barrier.
inversion/accumulation layer and gate depletion is getting more and more
Capacitance-Voltage Characteristics Figures 5, 7 and 8 are the C-V
evident, especially in ultra-thin gate oxide nano-transistors. Take the 1.7nm
curves under different frequency with Tox equals 6.5nm, 1.7nm, and 1.3nm. In
thickness device for instance, originally we think the capacitance thickness
Fig. 5, from low to high frequency, the capacitance value becomes a little smaller. The reason is presumed that︰as
should be as thick as 1.7nm, but from the measured data, the effective thickness is
the frequency is becoming higher, the
about 2.3nm. This 0.6nm thickness difference is supposed to be supplied by
inversion carriers of source and drain do not have enough time to respond. Fig. 6
quantum layers and the horizontal RC delay (shown in Fig. 6). For the case of
illustrates this RC delay model of above phenomenon. Certainly, in long channel
1.3nm thickness device, the effective oxide thickness is around 2.1nm. The
devices, the RC delay is larger, so to the
0.8nm thickness difference is not only 417
第七屆奈米工程暨微系統技術研討會
2003/11/20-21
caused by quantum layers, horizontal RC
King, C. Hu, X. Wang, X. Guo and T. P. MJ:
delay, but also gate leakage current. This means the high frequency compensation
IEEE Electron Device Lett. 21 (2000) p. 540. 5) W. K. Henson, N. Yang, S. Kubicek, E. M.
in ultra-thin devices is not a total solution.
Vogel, J. J. Wortman, K. De Meyer and A. Naem: IEEE Trans. 47 (2000) p. 1393. 6) H.-S. Huang and J.-S. Shiu, S.-J. Lin, J.-W.
CONCLUSIONS In the future, the gate oxide
Chou, R. Lee, C. Chen and G. Hong: Jpn. J. Appl. Phys. 40 (2001) p.1222.
thickness may be reduced to 1 nm or beyond so the leakage problems will become more serious as listed in the followings. 1. In short channel devices, the ratio of Iedge to total gate current will rise higher. 2. Gate leakage will cause a lot of distortions in device extraction and analysis. 3.
parameter Fig.1 Various leakage paths in an on-state NMOS device.
High frequency makes leakage compensation in capacitance
measurement. 4. In ultra-thin gate oxide devices, the quantum mechanism is more obvious. Through the research presented here, the effects of EDT are better understood and these may consolidate the basis for solving future problems. REFERENCE 1) H.-S. Huang and I.-K. Chen: Proc. 12th VLSI Design/CAD
Symposium, Taiwan,
Aug.,
2001. 2) N. Yang, W. K. Henson and J. J. Wortman: IEEE Trans. Electron Devices 47 (2000) p. 1636. 3) K. N. Yang, H. T. Huang, M. J. Chen, Y. M.
Fig. 2 Practical measured I–V curves of IS/D and ISUB tunneling leakage in (a) NMOS and (b) PMOS. Device size is W/L=50/0.5um and gate oxide thickness, dox = 2.3 nm.
Lin, M. C. Yu, S. M. Jang, C. H. Yu and M. S. Liang: IEDM Tech. Dig., 2000, p. 679.
4) Y. C. Yeo, Q. Lu, W. C. Lee, T.-J. 418
第七屆奈米工程暨微系統技術研討會
2003/11/20-21 frequency gate C source
drain R
R
RC delay
substrate
Fig. 6 A RC delay model in substrate region. Tox=1.7nm C-V with different frequency
Cgg_(pF/um2)
0.03
60 KHz 80 KHz
0.02
100 KHz 120 KHz 140 KHz
0.01
250 KHz 500 KHz
0 -3
-2
-1
750 KHz
0
1
2
3
1 MHz
Vg_(V)
120 KHz 1.7nm ideal
Fig. 7 C-V measurement of Tox=1.7nm with different frequency.
Fig. 3 Measured SDE tunneling leakage current increases with a longer Lov length in both N and PMOS.
Tox=1.3nm C-V with different frequency f=60 KHz
IG increases abruptly as TOX gets thinner
0.05
f=80 KHz
0.04
f=100 KHz
0.03
f=120 KHz
1E-4 1E-5
2 Cgg_(pF/um )
gate leakgage current IG _(A)
1E-3
TO X=6.5nm TO X=1.7nm TO X=1.6nm TO X=1.3nm
1E-6 1E-7 1E-8 1E-9 1E-10
f=140 KHz
0.02
f=250 KHz
0.01
1E-11
f=500 KHz
1E-12
0
1E-13
f=750 KHz
-3 -2 -1 0
1E-14 1E-15 -3
-2
-1
0
1
2
1
2
3
f=1 MHz
Vg_(V)
3
gate bias VG_(V)
120 KHz Tox=1.3nm Ideal
Fig. 8 C-V measurement of Tox=1.3nm with different frequency
Fig. 4 Gate Leakage of various devices having oxide thicknesses from 6.5nm to 1.3nm.
frequency RC delay gate R
Tox=6.5nm C_V with different frequency
C
source
0.008
drain
f=100 Hz f=1K Hz
substrate
f=60K Hz
0.006 Cgg_(pF/um2)
R
C
f=80K Hz
Fig. 9 A RC model for EDT compensation.
f=100K Hz
0.004
f=120K Hz
quantum effect
f=140K Hz
0.002
gate gate depletion
f=250K Hz f=500K Hz
0 -3
-2
-1
0 1 Vg_(V)
Vg bias
source
inversion/accumulation layer
drain
f=750K Hz 2
3
substrate
f=1M Hz
Fig. 5 C-V measurement of Tox=6.5nm with different frequency
419
Fig. 10 The inversion/accumulation layer and gate depletion caused by quantum effect.
