Proceedings of the 8th European Microwave Integrated Circuits Conference
High Power SiGe E-Band Transmitter for Broadband Communication Roee Ben Yishay, Oded Katz, Roi Carmon, Benny Sheinman, Run Levinger, Nadav Mazor and Danny Elad IBM Haifa Research Lab, Mount Carmel 31905 Haifa, Israel
[email protected] Abstract — Fully integrated transmitter at E-band frequencies in a superhetrodyne architecture covering the 7176GHz was designed and fabricated in 0.12μm SiGe technology. The transmitter's front-end includes a power amplifier, imagereject driver, tunable RF attenuator, power detector and IF-toRF up-converting mixer. A variable gain IF amplifier, quadrature baseband-to-IF modulator, frequency synthesizer and x4 frequency multiplier (quadrupler) are also integrated onchip. It achieves output power at P1dB of 17.5 to 18.5 dBm, saturated power of 20.5 to 21.5 dBm, up to 39 dB Gain with an analog controlled dynamic range of 30 dB and consumes 1.75 W.
II. TRANSCEIVER OVERVIEW The superheterodyne 71-76GHz transmitter has variable intermediate frequency (IF) of 7.9-8.4 GHz as depicted in Fig.1. The LO signals for the RF and IF mixers are created by quadrupling (f4xLO – 8/9 of the RF) and dividing (fIF – 1/9 of the RF) the PLL's output signal (fLO – 2/9 of the RF). If desired, an external LO can be alternatively applied from an off-chip source. The transmitter up-converts the baseband signal to IF, filtering and amplifying the IF voltage amplitude by 11dB before up-converting it with a -5dB conversion gain double balanced Gilbert-cell mixer to the RF frequency [6]. A 30 dB dynamic range analog controlled variable attenuator was placed after the up-converting mixer in order to maintain LO suppression level. Finally, the RF signal is 35 dB amplified by the driver and power amplifier, providing maximum output power of 20.5-21.5 dBm. The PA's differential outputs are coupled to power detector with DC voltage output for power leveling. An optional Balun with 1dB insertion-loss (IL) can be added to enable single-ended RF output. An integrated image reject filter is incorporated within the driver stage and attenuates the image (fIM – 7/9 of the RF) by 30 dB.
Keywords—E-Band; SiGe BiCMOS; Transmitter; Millimeterwave Integrated Circuits
I. INTRODUCTION The E-band frequency range (71-76GHz and 81- 86GHz) features a large bandwidth for high capacity, point-to-point wireless applications [1]. Current E-band radio systems employ costly hybrid RF front end components, while only few recent publications [2] examine the possibility to cover the lower band with silicon based monolithic solution in direct conversion architecture. Recently we demonstrated fully integrated SiGe based transceiver chipset at E-band frequencies [3],[4]. This transmitter (Tx) chip is a part of complete chipset of Tx/Rx designed to cover both 71-76GHz and 81-86GHz and initially presented in [5]. In this paper we present a high performance version of the lower E-band (71-76GHz) transmitter (Tx). This enhanced version includes many important new features and will be discussed in details. The chip was designed and fabricated in IBM's 0.12μm SiGe BiCMOS technology (BiCMOS8HP) with 5 metal layers. It utilizes the double conversion superhetrodyne sliding–IF architecture that enables sharing the baseband and IF circuits for both upper and lower band chips, while the RF Front components have to be tuned for each band separately. The chip allows multi-gigabit per second transmission using QPSK or higher QAM modulation, with Tx gain of 35-39 dB, saturated output power of 20.5-21.5 dBm and dynamic range of 30 dB.
978-2-87487-032-3 © 2013 EuMA
Fig. 1. Block diagram of the Tx. Differential signals are bolded.
The ECC [1] channelization requires a 125/250MHz band spacing across the E-band range. The use of versatile transceiver architecture allows the PLL to operate at relatively narrow frequency range (with 7% tuning), controlled by the divider multiplication factor (N) and the VCO frequency. The 4th order fully differential sub-integer PLL is based on Ref [6], with modified divider so that reference clock of 27.777 MHz
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Fig 2.Schematic diagram of one half of the differential Power Amplifier.
is used and N=568-608 at half integer steps. This allows 62.5 MHz center frequency bands at fRF. The PLL shows -111dBc and -131dBc phase noise at 1MHz and 10MHz offsets respectively and sub-integer spurs below -45 dBc. A detailed description of the PLL can be found in [7]. The Tx chip operates under 2.7 V supply, 1.2 V supply for the digital circuitry, and dedicated 2V supply for the PA. III. TRANSMITTER CIRCUITS AND MEASUREMENTS In the following sections, detailed description is given for several of the critical RF-front circuits, as well as measurement results for both circuits and chips. A die photograph of the Tx is shown in Fig 4. The die size is 5.2 x 1.7 mm2.
Fig. 3.Measured S-parameters of the Power Amplifier breakout.
B. Power Detector The power detector (Fig. 5) is coupled to the PA differential output via parallel plate capacitors realized between the two upper metal layers (not shown). Capacitors C1 and C2 together with the shunt stub TL form a matching network between the common-emitter pair (Q1 and Q2) and the coupler's output. Q1 and Q2 are biased in class B regime and driven differentially so that their summed collectors' currents consist of only even harmonics, strongly dependent in the input signal power. After lowpass filtering (by Clow and Rlow) only DC component remains. The second branch (M2, Q3) is designed to carry the same DC current as M1, so that only the excess DC current, formed by the self-mixing action will flow to the resistive load (digitally tuned).
A. Power Amplifier The power amplifier (PA) consists of a balanced configuration in which two unit cells (Fig 2.) are driven differentially and their outputs are summed using either low loss off-chip balun or on-chip ratrace balun with IL of 1dB and >25dB port to port isolation. The unit cell consists of 5 common emitter stages (CE). The first power combining is accomplished by dividing the final stage into two separated transistors and summing their power by a transmission-line impedance transformer providing simultaneous power and impedance matching. The combiner also includes a parallel 100 resistor to preclude odd mode oscillations. Each of the branches in the final stage consists of three parallel transistors. Matching networks utilize shielded microstrip transmission lines to allow a dense layout with total dimensions of 1300x1100μm2. Fig 3 shows the small signal S-parameters of the single-ended PA measured at 250C. S21 peaks to 21dB at 73.5GHz, with 3dB bandwidth of 16.7GHz (23%) and gain flatness of less than 0.7dB in the 71-76GHz range, where both S11 and S22
