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IEEE TRANSACTIONS ON MAGNETICS, VOL. 43, NO. 2, FEBRUARY 2007
High-Rate Modulation Codes for Reverse Concatenation Mario Blaum1 , Fellow, IEEE, Roy D. Cideciyan2 , Evangelos Eleftheriou2 , Fellow, IEEE, Rick Galbraith3 , Ksenija Lakovic1 , Thomas Mittelholzer2 , Travis Oenning3 , and Bruce Wilson1 Hitachi Global Storage Technologies, San Jose, CA 95120 USA IBM Zurich Research Laboratory, Rüschlikon 8803, Switzerland Hitachi Global Storage Technologies, Rochester, MN 55901 USA
We present a reverse concatenation (RC) architecture using Reed–Solomon (RS) error-correction codes (ECCs). The scheme employs very-high-rate pre-RS modulation codes followed by RS parity symbol insertion. The very-high-rate modulation codes in the RC scheme, which facilitate timing recovery and automatic gain control and reduce the detector path memory, are of the same type as the modulation codes that have been used in generalized partial-response maximum-likelihood (PRML) detection systems. Index Terms—Fibonacci codes, magnetic recording, modulation codes, partial-response channel, reverse concatenation (RC).
I. INTRODUCTION ODULATION codes, also known as constrained codes, have been widely used in magnetic and optical data storage to eliminate sequences that are undesired for the processes of recording and reproducing digital data. Various classes of modulation codes are used in practice. For example, peak detection systems employing run-length-limited RLL constrained codes such as rate-1/2 RLL(2,7) and rate-2/3 RLL(1,7) codes have been predominant in digital magnetic storage at low normalized linear densities. At moderate normalized linear densities, the introduction of partial-response maximum-likelihood (PRML) detection channels into data storage [1], [2] required a different type of constrained codes [3]. This class of codes, which are known as codes, facilitates timing recovery and gain conPRML trol, and limits the path memory length of the sequence detector, and, therefore, the decoding delay, without significantly codes are used degrading detector performance. PRML precoders and noise-predictive in conjunction with maximum-likelihood (NPML) channels [4], [5], which generalize the PRML concept. Serial concatenation of outer Reed–Solomon (RS) codes and inner modulation codes has been used in virtually all magnetic and optical data-storage systems. In this type of conventional concatenation, here referred to as forward concatenation (FC), error propagation at the output of the modulation decoder is reduced or eliminated by selecting a sufficiently small block size for the modulation code. However, small block sizes often result in reduced modulation code efficiency, i.e., weak code constraints and/or low modulation code rates. Recently, the rate of codes used in commercial disk drives have been PRML about 0.98, and both code constraints and have been about
M
Digital Object Identifier 10.1109/TMAG.2006.888374 Color versions of one or more of the figures in this paper are available online at http://ieeexplore.org.
30. To improve performance further, it is desirable to increase the modulation code rate and simultaneously tighten the code constraints. Conventional FC schemes, however, do not allow further increases in modulation code rate without loosening the code constraints or suffering from performance degradation due to increased error propagation. An alternative approach to FC schemes is provided by reverse concatenation (RC) [6]. This coding technique employs an efficient pre-RS modulation encoder followed by a systematic RS encoder and a post-RS modulation encoder for RS parity symbols. Although RC architectures with efficient pre-RS modulation codes may employ large block sizes, they do not suffer from error propagation because the modulation decoder for these efficient codes follows the RS decoder. An RC architecture based on inserting error-correction coding (ECC) parity bits into a modulation-encoded data stream has been proposed in [7]. The inherent benefit of such an approach is that soft information from the detector or inner parity decoder is readily provided to the ECC decoder. In this paper, we introduce RC architectures that avoid using a post-RS modulation encoder by inserting RS parity symbols at appropriately chosen positions within the symbol stream at the output of the pre-RS modulation encoder. We refer to this technique as partial symbol interleaving of the code words at the output of the systematic RS encoder. During the past decade, the redundancy of PRML codes in commercial disk drives decreased from 11.2% to about 2% at the expense of increasing the values for the and constraints from 4 to about 30. A further decrease of modulation code redundancy in FC architectures would have undesired consequences such as performance degradation due to error propagation at the modulation decoder output or further and values. However, RC architectures can increase of significantly reduce the and values of current commercial disk drives while simultaneously reducing the redundancy of the modulation code to values below 0.5% and thus improving error performance primarily thanks to decreased rate loss. The class of codes we present is based on the interleaving of two enumerative codes that use generalized Fibonacci weights [8]. This class of codes satisfies tight and constraints. The
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Fig. 2. Balanced interleaved encoder based on rate-3/4 prefix substitution. Fig. 1. RC architecture based on pre-RS PRML(G; I ) coding and partial symbol interleaving of RS symbols.
encoders and decoders for all codes can be designed to reduce latency by using truncated base representations and successive subtractions and additions for encoding and decoding [9]. We evaluate the performance of this RC architecture via simulations using a sector size of 420 10-b user bytes and compare it with the performance of various FC schemes that have been implemented in disk drives. Specifically, a rate-20/21 maximum transition run (MTR) code and a rate-199/200 PRML code have been selected as the pre-RS modulation codes of choice for the simulation study. By interleaving two Fibonacci codes, we obtain codes with high rate and good and constraints. Each component code is a high-rate generalized Fibonacci code. Each Fibonacci code controls the constraint. In this case, the constraint is equal to . The coded bits are then all negated, and the code is used precoder. with a Each Fibonacci code is designed in such a way that the runlength constraints are variable. In this way, we can make them more stringent in certain locations of the code. This allows us to insert the RS check symbols at such locations. The RS symbols are unconstrained. We obtain codes with overall constraints and , including the inserted 10-b RS parity symbols. This paper is organized as follows. In Section II, we describe an RC architecture that employs pre-RS modulation codes of the type PRML . We use a technique of partial symbol interleaving. In Section III, balanced interleaved enumerative codes are described. In Section IV, we evaluate the performance of this RC architecture and compare it with the performance of FC schemes used in disk drive products. Section V contains a summary of the main results and conclusions.
components are high-rate generalized Fibonacci codes and a prefix-substitution, which achieves the balancing in the interleaving process. We present balanced interleaved enumerative codes based on a rate-3/4 prefix-substitution and generalized Fibonacci codes with nonuniform constraint profile. Balanced interleaved enumerative codes are constructed by serial concatenation of this rate-3/4 prefix-substitution and two interleaved generalized Fibonacci codes (see Fig. 2). The coded bits are then all negated and the code is used with a -precoder. The rate-3/4 prefix substitution transforms an input sequence into an output sequence , where both the even and the odd interleave of the output sequence satisfy the same prefix constraint. This prefix constraint requires and . Since there are nine possible 4-b combinations satisfying such a constraint, one can readily find such a substitution. Other types of prefixes are also possible, like a prefix of rate-9/10. A. Generalized Fibonacci Codes A generalized Fibonacci code of length is characterized by its bases, which are also called generalized weights in [8]. For later use, it is convenient to write these weights, which are , [9], where positive integers, as . Given a predetermined parameter , Kautz defines the first weights by , , and requires that the linear recursion holds for . Following Immink [9], the linear recursion can be weakened by replacing the equality by an inequality in the linear recursion. This results in a set of linear inequalities for the bases (1)
II. RC ARCHITECTURE The RC architecture considered in this section employs a pre-RS very-high-rate PRML code and partial symbol interleaving. Fig. 1 shows a block diagram of this architecture. The user data is first encoded by a very-high-rate pre-RS PRML encoder followed by a precoder. The RS parity symbols are then generated as a function of the PRML -encoded data stream and partially interleaved into the constrained PRML -encoded symbol stream. Again, the depth of partial interleaving of unconstrained RS parity symbols into the constrained symbol stream is selected such that the best possible constraints at the recording channel input are achieved. -inner parity bits are then generated as a function of -bits and inserted into the encoded data stream, i.e., the inner parity code rate is .
for . The parameter determines the -constraint of the resulting generalized Fibonacci code. If one allows , one can the parameter to depend on the index , i.e., achieve further generality in the code construction; in particular, the resulting generalized Fibonacci code will have a -profile that depends on the location . In order to achieve efficient encoding and decoding (see [9]), one chooses the to be fractional binary numbers in the range , which have an -bit representation. Here, is referred to as the span of the bases. Given a binary input sequence , the encoder for the generalized Fibonacci code computes the binary output sequence by performing a “generalized base change” (which will be inverted before precoding so that 1’s become 0’s) (2)
III. BALANCED INTERLEAVED ENUMERATIVE PRML CODES The design of balanced interleaved enumerative codes is based on an even–odd interleaving construction. The key
The generalized base change can be computed in a slidingwindow fashion with a window width equal to the span . The
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IEEE TRANSACTIONS ON MAGNETICS, VOL. 43, NO. 2, FEBRUARY 2007
TABLE I BASE AND j -PROFILE OF LENGTH-100 GENERALIZED FIBONACCI CODE
presented algorithm is a sliding-window version of the inverse algorithm in enumerative source encoding [10]. The sliding-window encoder is a finite-state machine, which base elements and which has a state has stored all the space consisting of all -bit strings . The window slides over the input sequence starting at the most significant bits. At each step, the window moves by one position towards the least significant bit, thereby updating its state variable, producing one output bit and reading one input bit. At the beginning, the state variable is initialized to . The output is determined by the difference , which involves the last base element . If is nonnegative, the most significant output bit becomes , and, otherwise . The next state is computed as follows. If , the difference is represented by an -bit number as and the last bit of the next state is determined by the next input bit, i.e., . If , the new state is a left shift of the current state ; that is for and, again, . In the second step, the next state becomes the current state and one forms the difference using the second-to-last base element for the subtraction. The rules for updating the state variable and computing the output bit are the same as in the first step, i.e., the algorithm proceeds as in the previous step. It then moves on until the least significant input bit is read and incorporated into the next state . At this point, the algorithm has to be slightly adjusted because all input bits have been read. By creating an extension of the input vector , which consists of the all-zero vector, the algorithm can then proceed using the same update rules as before and it generates in the last steps the least significant output bits . The decoder performs the generalized base change in the opposite direction. Given a codeword , the decoder forms the weighted sum . This sum computation can be implemented in a sliding-window fashion by an -bit adder, which moves from the least significant bits towards
the most significant bits. At each step, the decoder performs a binary addition with carry-on of two -bit vectors. B. Specification of a 199/200 Balanced Interleaved Enumerative Code The balanced interleaved enumerative code which is described in this section belongs to the class of rate-199/200 PRML codes. The 199/200 code uses a rate-3/4 prefix substitution for balancing the prefix of the even and odd interleave. The generalized Fibonacci code is determined by the base given in Table I, which has span . Table I indicates the runs of zeros at each of the 100 locations of each of the component interleaves of the final code. For instance, starting at location 88, we can have at most eight consecutive zeros. Also, at the beginning and at the end the constraints are such that there is never a run of more than 11 zeros when concatenating two codewords. The resulting code is a rate-199/200 PRML(22,11) code with three locations for 10-b RS parity symbol insertion that do not weaken the - and -constraints, i.e., this code is designed for a 10-b RS code with a rate of 200/230 0.8696 or higher. IV. PERFORMANCE EVALUATION The performance of the proposed RC architecture was evaluated and compared with the reference FC schemes. FC 1 employs a rate-60/62 combined modulation/single-parity code. FC 2 employs a 20/21 MTR code, which is based on the 16/17 MTR code described in [11]. Out of the 20 unconstrained bits at the input of the MTR encoder 16 b are encoded using the 16/17 code from [11], while the remaining four unconstrained bits are appended at the beginning (2 b) and the end of the block (2 b). The inner parity code for FC 2 is a rate-105/108 triple-parity polynomial code with generator polynomial . Note that both FC architectures employ RS codes over the Galois field GF . Specifically, FC 1 is based on an RS code of length 462 and dimension 420, whereas FC 2 is based on an RS code of length 460 and dimension 420. FC 1 and FC 2 can, therefore, correct up to 21 and 20 10-b bytes per sector, respectively.
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performance of the proposed RC architecture was evaluated via simulations. The recording channel was corrupted by 25% electronics noise, 25% colored noise and 50% data-dependent transition noise in the first scenario (see Fig. 3) and by 100% electronics noise in the second scenario (see Fig. 4). The 16-state NPML detector operated on a time-varying trellis whenever the rate-20/21 MTR code was used. A noise-predictive parity postprocessor was used for all simulated schemes [13]. In the schemes FC 2 and RC 1, MTR checking in the postprocessor was turned on. For electronics noise, RC 1 improved the performance of FC 1 by about 0.15 dB already at a sector error rate of 10 . Finally, RC 2 performed best in both noise scenarios and gained over the performance of FC 1 about 0.2 dB at a sector error rate of as little as 10 . V. CONCLUSION Fig. 3. Performance comparison of RC schemes with perpendicular recording 2.65 and mixed noise. at normalized user density
D =
We have presented a scheme for reverse concatenation that allows the insertion of unconstrained RS symbols with good constraints. We have used generalized Fibonacci codes together with interleaving and a rate-3/4 prefix substitution. We have obtained codes of a very high rate, such as 199/200. The technique can also be extended to other rates. Our simulations show an improvement of 0.2–0.3 dB with respect to conventional forward concatenation schemes. REFERENCES
Fig. 4. Performance comparison of RC schemes with perpendicular recording 2.65 and electronics noise. at normalized user density
D =
One variation of the proposed RC architecture denoted by RC 1 employs the same 20/21 modulation code as the reference FC 2 scheme. RC 1 employs a rate-115/118 inner triple. parity polynomial code with generator polynomial This architecture aims at improving performance by reducing or eliminating error propagation due to rate-16/17 modulation deinverse precoding. Another variation coding and local of the RC architecture denoted by RC 2 employs a rate-199/200 modulation code, as described in Section III. RC 2 employs a rate-60/61 inner single-parity code. This architecture has the highest overall coding rate of 0.8942 and aims to enhance performance by operating at a low normalized channel density and eliminating error propagation. Note that both RC architectures process 420 user bytes per sector and employ RS codes over GF . Specifically, RC 1 is based on an RS code of length 483 and dimension 441 whereas RC 2 is based on an RS code of length 462 and dimension 422. RC 1 and RC 2 can, therefore, correct up to 21 and 20 10-b bytes per sector, respectively. perpendicular recording channel model at Using a a normalized user density of 2.65 [12], the sector-error
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Manuscript received July 7, 2006 (e-mail:
[email protected]).
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