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Khoirom Johnson Singh. 1,*, Tripurari Sharan. 1 ... Khoirom Johnson Singh et al. JoVDTT (2018) ..... Jashanpreet Kaur, Navdeep Kaur, Amit. Grover. A Review ...
Journal of VLSI Design Tools & Technology ISSN: 2249-474X (Online), ISSN: 2321-6492 (Print) Volume 8, Issue 1 www.stmjournals.com

High Speed and Low Power Basic Digital Logic Gates, Half-Adder and Full-Adder Using Modified Gate Diffusion Input Technology Khoirom Johnson Singh1,*, Tripurari Sharan1, Huirem Tarunkumar2 1

Electronics and Communication Engineering, North Eastern Regional Institute of Science and Technology, Deemed to be University, Nirjuli, Arunachal Pradesh, India 2 Electronics and Communication Engineering, National Institute of Technology, Manipur, India

Abstract In this paper, modified gate diffusion input (MGDI) technology has been used for the design and implementation of digital integrated circuits (ICs). In today’s digital world, IC plays a vital role in high-performance computing, communication, and many consumer electronics. IC manufacturing technology has scaled down to smaller device dimensions. This scaling has a great impact on the design of digital ICs. The main objective of the IC manufacturing technology is to reduce area, power dissipation and delay for a very fast digital circuit. The demand for low power system and increased logic density has led to the introduction of new design technologies. A new technology has been developed to overcome the inherent issues of the existing circuit technologies, known as Gate Diffusion Input (GDI). GDI is a low power design technique for the rapid digital circuits. It has proved to be more efficient as compared to the Complementary Metal Oxide Semiconductor (CMOS), Pass Transistor Logic (PTL) technology and Transmission Gate (TG) in terms of performances such as lesser transistor count, low power dissipation, high speed and lesser area. A further improvement of GDI technology is the MGDI. It allows further reduction in power dissipation, propagation delay, and layout area effectively as compared to GDI, CMOS, PTL, and TG. The Cadence Virtuoso environment using GPDK 180 nm bulk CMOS process technology has been used to simulate the basic digital logic gates, half-adder, and full-adder. The different parameters such as transistor count, propagation delay, power dissipation and layout area have been compared showing the advantages of the MGDI over the standard CMOS technology. Keywords: Integrated circuit (IC), Complementary metal oxide semiconductor (CMOS), Gate diffusion input (GDI), pass transistor logic (PTL), Modified gate diffusion input (MGDI), Very Large Scale Integration (VLSI)

*Author for Correspondence E-mail: [email protected]

INTRODUCTION The rapid upsurge in the research area of low power, high speed embedded systems such as smartphones, laptops, tablets and biomedical devices, etc., has led the digital circuit designers to scale down the circuit dimensions, so that the storage and logical density can be increased in a chip. The aim of the designer is to reduce the total power dissipation. Earlier, power dissipation has been the secondary concern, nowadays, the customer demand for the portable battery operated devices such as cell phone, smartphones, laptops, etc., is increasing rapidly. All these devices are battery operated and the life of the

battery is of primary concern. However, the existing battery technology has not kept up with the power requirement of the portable devices. Therefore, low power design technology is required to make them commercially viable. During the last 20 years, digital circuit design has been carried out by using different technologies, such as CMOS complementary logic, Dynamic CMOS, Clocked CMOS, CMOS Domino logic, PTL, and TG [1]. A better alternative technology to achieve low power dissipation, smaller physical layout area, and high-speed performance is GDI. It is used to design digital ICs with lesser number

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MGDI Technology in Digital ICs

of transistors. It can be used to design many digital circuits to achieve low power dissipation, less propagation delay, and a lesser area as compared to the CMOS and the PTL technology. This paper utilizes the MGDI technology to implement different basic digital logic gates, 1-bit half adder, and 1-bit full adder and comparing their characteristics with CMOS technology in terms of power, delay, transistor count, and layout area [2, 3]. The remaining portion of the paper is organized as: Next part of the paper explains the early technologies; the following part illustrates the GDI and MGDI technology, provides the schematic and layout design of the basic digital logic gates, half-adder, and full-adder, the simulation results, and lastly, the paper ends with a conclusion followed by an acknowledgment and references.

Khoirom Johnson Singh et al.

B = 1, the upper device is ON, hence the output signalF = A. Similarly, when B = 0, the bottom device is ON and the output signal F = 0. To ensure that the gate is static, the presence of switch driven by the gate signal ‘B’ is necessary. Some of the advantages of PTL are: low power, high-speed and smaller layout area, as the number of the transistor is reduced. PTL also has some problems, like, the circuit speed decreases as the supply voltage decreases, and a very high static power dissipation [5]. CMOS Technology A static CMOS gate consists of two networks, the pull-up network (PUN) and the pull-down network (PDN) and is shown in Figure 3. It consists of an n-input logic gate in which all the inputs are shared to PUN and PDN.

EARLY TECHNOLOGIES Transmission Gate The basic TG is shown in Figure 1. It consists of an NMOS and a PMOS transistor, which are connected in parallel with different gate connections, common source, and common drain connection. The clocked signal ‘A’ is applied to the gate terminal of the NMOS and its complement ‘A̅’ is applied to the gate of the PMOS transistor. The gate voltages applied to both the NMOS and PMOS transistors are complementary to each other. The TG operates as a bidirectional switch and it is controlled by the signal ‘A’. The input and output ports are interchangeable. If, A = 1, then both NMOS and PMOS are turned on and gives a low resistance current path between OUT and IN. Similarly, if, A = 0 then both NMOS and PMOS are turned off and the path between OUT and IN will be an opened circuit. This condition is known as a high impedance state [4]. Pass Transistor Logic PTL is one of the most generally used alternative techniques to the CMOS technology. The main objective of this technique is to reduce the number of transistors and allow the input signal to control the gate, source and drain terminal. Figure 2 shows the implementation of an AND logic function using PTL. When the gate signal

A

OUT

IN

A Fig. 1: Transmission Gate (TG).

B

A F=AB 0

B Fig. 2: Implementation of an AND Gate Using PTL.

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Journal of VLSI Design Tools & Technology Volume 8, Issue 1 ISSN: 2249-474X (Online), ISSN: 2321-6492 (Print)

The function of PUN is to maintain a connection in between the output and the supply voltage (Vdd), when the output signal is logic high. Similarly, when the output signal is logic low, PDN provides a connection in between the output and the ground (Gnd). The PUN and PDN networks are constructed such that only one of the networks is operating in the steady state condition. All the PUNs are constructed by the PMOS transistor while all the PDNs have been constructed by using only the NMOS transistors. Figure 4 shows the CMOS inverter with a load capacitor (CL). The drain of the NMOS and PMOS are shorted and the gate of NMOS and PMOS are shorted. When, the input signal IN = 0, then PMOS is ON and the NMOS is OFF, hence, OUT = 1. Similarly, when IN = 1, PMOS is OFF and NMOS is ON. Therefore OUT = 0 [6].

GATE DIFFUSION INPUT

VDD a1 a2 an

F(a1,a2,….an) a1 a2 an

PDN GND Fig. 3: CMOS Logic Gate. Vdd PMOS

IN

The basic GDI cell is shown in Figure 5. At first look, it is almost similar to that of the standard CMOS inverter. It is a low power digital circuit design technique. It has three input terminals ‘G’, ‘P’ and ‘N’. ‘G’ can be used as a common gate input, ‘P’ and ‘N’ can be used as an input to the source or drain of the PMOS and NMOS transistors, respectively. Some of the basic differences in between the CMOS inverter and GDI cell are that the GDI cell has three input ports (‘G’, ‘N’ and ‘P’) and one output port, but in case of CMOS inverter, it has only one input and output port; GDI cell has no fixed position for Vdd and Gnd but in case of CMOS inverter, it is mandatory that the void is tied to the source of the PMOS and the ground to the source of the NMOS transistor. Here, the body of the NMOS and PMOS transistors are connected to ‘N’ or ‘P’ input terminals respectively, so that it can be biased in contrast with that of the CMOS inverter. All the logical functions can be implemented in the twin-well CMOS or Silicon on insulator (SOI) technologies as all the functions are not possible to implement in the standard p-well CMOS process [7].

PUN

OUT CL

NMOS

Gnd

Fig. 4: CMOS Inverter. P PMOS

G

JoVDTT (2018) 34-42 © STM Journals 2018. All Rights Reserved

OUT

NMOS

N Fig. 5: GDI Cell.

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Khoirom Johnson Singh et al.

Functions of GDI Various logical functions can be implemented by using different input configurations in GDI cell. For, e.g., an OR logic function can be implemented when N = 1, P = B, and G = A. Similarly, an AND logic function can be implemented when, N = B, P = 0, and G = A. Now by changing different input configurations of GDI cell, four different Boolean expressions can be obtained (Table 1). It must be noticed that not all the logical functions are possible in the p-well CMOS technique, but can be successfully implemented in twin-well CMOS technology. With the new GDI logic style, a wide range of complex logical functions can be implemented by using the simple GDI cell.

technologies. Using MGDI, the sub-threshold and gate leakage can be reduced considerably, as compared with static CMOS gate. It can be used to design high speed and low power circuits using few transistors [9, 10].

Modified GDI Some of the problems associated with GDI technology are: logic swing degradation, complexity in fabrication in the standard CMOS twin-well process and bulk connections. These problems can be overcome by using a special technique known as the MGDI. The basic MGDI cell is almost similar to that of GDI cell. It consists of an NMOS and a PMOS device with four nodes, i.e. ‘G’ which acts as common gate input for NMOS and PMOS, ‘P’ and ‘N’ as an outer diffusion port of PMOS and NMOS, respectively and ‘D’ acts as a common diffusion port on both the devices. The various logical functions of the MGDI are shown in Table 2.

Table 1: Logical Functions in GDI.

The MGDI cell is shown in Figure 6. In this cell, the body of the PMOS device is connected to the power supply, i.e., Vdd and the body of the NMOS transistor is connected to the Gnd that increases the stability of the circuit and its loading effect. But in case of the GDI cell, the bulk of the PMOS transistor is connected to the drain, whereas the bulk of the NMOS transistor is connected to the source [8].

SCHEMATIC AND LAYOUT DESIGN The schematic and layout of the basic digital logic gates (AND, OR, XOR, and XNOR), 1bit Half-Adder, and 1-bit Full-Adder have been designed and implemented with the aspect ratio of 3, using the modified gate diffusion input (MGDI) technology, in the schematic and layout environment of the Cadence Virtuoso using the GPDK 180 nm bulk CMOS process technology (Figures 7–18) [11–13].

N

P

G

Output

Function

B

0

A

AB

AND

1

B

A

OR

C

B

A

0

1

A

A+B ̅ AB+AC ̅ A

MUX NOT

Table 2: Logical Functions of MGDI. N

Gnd P

Vdd

G

D

Function Inverter

0

0

1

1

A



A

A

0

A

B

AB

AND

1

0

A

D

B

A+B

OR



0

A

1

B

A̅B+B̅A

XOR

A

0



1

B

AB+A̅B

XNOR

P

Vdd G

The MGDI technology is more efficient as compared to other technologies as it allows reducing the power dissipation, propagation delay and layout area of the digital ICs. In MGDI, the bulk of PMOS is connected to Vdd and NMOS to the Gnd. With four standard terminals, NMOS and PMOS transistors, MGDI can implement all the CMOS

JoVDTT (2018) 34-42 © STM Journals 2018. All Rights Reserved

D

Gnd

N Fig. 6: MGDI Cell.

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Journal of VLSI Design Tools & Technology Volume 8, Issue 1 ISSN: 2249-474X (Online), ISSN: 2321-6492 (Print)

Fig. 10: Layout of the OR Gate. Fig. 7: Schematic of the AND Gate.

Fig. 8: Layout of the AND Gate.

Fig. 11: Schematic of the XOR Gate.

Fig. 9: Schematic of the OR Gate.

Fig. 12: Layout of the XOR Gate.

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MGDI Technology in Digital ICs

Khoirom Johnson Singh et al.

Fig. 13: Schematic of the XNOR Gate.

Fig. 16: Layout of the Half-Adder.

Fig. 14: Layout of the XNOR Gate. Fig. 17: Schematic of the Full-Adder.

Fig. 15: Schematic of the Half-Adder.

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Fig. 18: Layout of the Full-Adder.

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Journal of VLSI Design Tools & Technology Volume 8, Issue 1 ISSN: 2249-474X (Online), ISSN: 2321-6492 (Print)

SIMULATION AND RESULTS The basic digital logic gates, half-adder, and full-adder have been simulated using the Cadence Virtuoso environment with the GPDK 180 nm bulk CMOS process technology at 40 MHz and 27°C, with a load capacitance of 100 fF except for the combinational circuits. The objective of this simulation is to evaluate various performances of the logic gates, half-adder, and full-adder. These performances include power dissipation and propagation delay. The transient analysis with a rise and fall time of 2 ns has been performed to get these performances (Figures 19–24).

Fig. 22: Transient Response and Power Dissipation for the XNOR Gate.

Fig. 23: Transient Response and Power Dissipation for the Half-Adder. Fig. 19: Transient Response and Power Dissipation for the AND Gate.

Fig. 24: Transient Response and Power Dissipation for the Full-Adder. Fig. 20: Transient Response and Power Dissipation for the OR Gate.

MGDI

CMOS

35 30

Transistor Count

30 25

20

20 14

14

15

10 6

10 5

6

6 4

2

4

2

0 AND

Fig. 21: Transient Response and Power Dissipation for the XOR Gate.

OR

XOR

XNOR

HalfAdder

FullAdder

Fig. 25: Bar Chart Comparison of the Transistor Count in MGDI and CMOS.

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MGDI Technology in Digital ICs

Khoirom Johnson Singh et al.

Table 3: Performance Comparison of the Digital Circuits in MGDI and CMOS Technology.

AND

Power (µW) 23.12

MGDI Propagation Delay (ns) 0.53

Transistor Count 2

Power (µW) 76.10

CMOS Propagation Delay (ns) 1.20

Transistor Count 6

OR

23.81

0.57

2

71.79

1.10

6

XOR

89.13

0.38

4

187.30

0.44

14

XNOR

84.29

0.65

4

189.30

0.90

14

Half-Adder

40.19

0.28

6

139.00

0.31

20

Full-Adder

169.30

0.44

10

189.40

0.48

30

Digital Circuits

MGDI 200 187.3

Power dissipation in µW

180

CMOS 189.3

139

160 140

89.13

76.1

120 100

189

169.3

23.12

84.29

71.79 40.19

80 60

23.81

40 20 0 AND

OR

XOR

XNOR

HalfAdder

FullAdder

Fig. 26: Bar Chart Comparison of the Power Dissipation in MGDI and CMOS. MGDI

CMOS

analyzed in MGDI technology. The various performances of the digital circuits have been simulated to calculate the total power dissipation, propagation delay, in conjunction with the transient analysis and are shown in Table 3. From the simulated results, CMOS and other existing early technologies consume more power and large propagation delay as compared to that of the MGDI technology. To implement a full-adder in CMOS, 30 transistors are required, whereas MGDI requires only 10 transistors (Figure 25), which is very less and often leads to low power dissipation and minimum delay. From the bar chart comparison as shown in Figures 26 and 27, it can be seen that the MGDI technology is superior to that of the normal CMOS technology in terms of power dissipation, propagation delay, and transistor count.

1.4

Propagation delay in ns

1.2

1.1

1.2 0.9 1 0.65

0.8 0.53

0.57

0.6

0.44

0.44

0.48

0.31

0.38

0.28

0.4 0.2 0 AND

OR

XOR

XNOR

HalfAdder

FullAdder

Fig. 27: Bar Chart Comparison of the Propagation Delay in MGDI and CMOS.

CONCLUSION Important different basic digital logic gates and few combinational circuits such as halfadder and a full-adder have been designed and implemented using Cadence Virtuoso environment using GPDK 180 nm bulk CMOS process node. Several performances have been

The basic MGDI cell can be used to implement a large number of logical functions efficiently when compared to normal CMOS logic style. MGDI logic style gives a design which has a small physical layout area, lower power dissipation up to 85%, high speed up to 30% faster and low complexity. MGDI cell can be used to design the low power and high speed sequential and combinational circuits. It gives high voltage swing and low static power dissipation. ACKNOWLEDGEMENT This work has been performed in Cadence Virtuoso environment using GPDK180 nm bulk CMOS process technology, utilizing all the available resources of Cadence Laboratory of Electronics and Communication Engineering Department, National Institute of Technology, Manipur. Finally, the authors declare that there is not any conflict of interest regarding the publication of this paper.

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Cite this Article Khoirom Johnson Singh, Tripurari Sharan, Huirem Tarunkumar. High Speed and Low Power Basic Digital Logic Gates, HalfAdder and Full-Adder Using Modified Gate Diffusion Input Technology. Journal of VLSI Design Tools & Technology. 2018; 8(1): 34–42p.

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