high speed low power comparator for ultra

International Conference on Communication, Computer & Power (ICCCP’07)

Muscat, February 19-21, 2007

INTEGRATING INDUSTRY CAE TOOLS AND VHDL INTO DIGITAL SYSTEMS DESIGN COURSES AZZOUZ BENZEKRI Dept of Electrical Engineering Faculty of Engineering University of Boumerdes, Algeria

KAMAL MEGHRICHE Dept of Electrical Engineering Faculty of Engineering University of Boumerdes, Algeria

Phone (213) 24 81 83 33 [email protected]

Phone: (213) 24 81 83 33 [email protected]

ABSTRACT The drastic advances in semiconductor technology in the last decade have made field programmable logic devices (FPLDs) with tens of millions gates common place integrated logic circuits. To allow designers to cope and use these high density FPLDs (densities are still growing) and associated increasingly sophisticated computer-aided engineering (CAE) logic development tools, higher level of abstraction and hierarchy in design description have become the rule to digital systems designers. In this context, Universities’ curricula have to adapt to these changes either by incorporating new courses or by updating existing ones. This paper describes the one-year digital systems design course updated in 2004/2005 at Boumerdes’ University. In this course, we integrated field-programmable gate arrays (FPGAs), the IEEE standard language VHDL and the industry most widely used programmable logic development toolset on PC station, Altera’s Max+Plus II. In the first part of the course, and beside teaching logic design basics with hands-on experiments using the TTL 74xxx series on the protoboard, VHDL was integrated throughout the course by means of simple tutorial examples. In the second part, and as students gained sufficient familiarity with the hardware/software development systems capabilities, students were taught design techniques based on the top-down methodology through hands-on experiments using an CPLD/FPGA-based platform development board. In this part, we did exploit VHDL constructs to make a design reusable, and hence demonstrate how digital design and rapid prototyping are facilitated by FPGAs and VHDL. KEYWORDS: FPGA, VHDL, Max+Plus II, Digital Systems Design with VHDL.

I. INTRODUCTION The Department of Electrical Engineering (DGEE) at the University of Boumerdes, Algeria, (where the language of instruction is English) serves over 500 undergraduate students. The admission of students to the Electrical Engineering program is based on the “Baccalaureat” examination with a minimum grade of 15/20. Electrical engineering students must specialize in one of the following four major areas: Communications

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Engineering, Computer Engineering, Control Systems, or Electric Drives. The undergraduate program follows a five-year curriculum in order to obtain the degree of “Ingénieur d’Etat” in Electrical Engineering. The Digital Systems Design course discussed in this paper is a core course offered in the third year for all majors. Its aim is to use CAE tools to develop the student’s ability to model, simulate and implement complex digital systems than they could build and test using SSI, MSI and LSI devices. Today, systems are getting so complex that even for smaller applications programmable logic devices (PLDs) and FPGAs have to be used. Therefore, students who intend to work on the area of the design of digital systems need to pursue modern high-level design of integrated digital systems [1]. As in most electrical and computer engineering curricula, a student enrolled in this course has already approved calculus, physics, a one-year engineering circuit analysis, a one-year active devices, a onesemester computer programming course and general education. In our department and until 2004, transistortransistor logic (TTL) protoboard-based projects have formed the backbone of our digital system design laboratories. Students used the traditional paper and pencil to draw their circuits which they constructed in the lab using TTL 74xxx and CMOS CD40xxx integrated circuits. These standard off-the-shelf SSI/MSI/LSI chips are placed into a prototyping board and connected together and to logic switches and LEDs with wires. In most cases these relatively small digital circuits would fail to function correctly due to faulty components or wires not correctly inserted into the board or the wiring pattern does not match the drawn schematic. We noticed that most of the students’ laboratory time was spent troubleshooting wiring connection problems rather than testing the theoretical material taught in class. The authors were interested in updating the contents of the course and providing a new paradigm for teaching digital systems design. They found it more convenient to integrate modern CAE tools and FPLDs. FPLDs, which include both FPGAs and complex programmable logic devices (CPLDs), offer a design platform that allows students to work on more meaningful projects with tens of thousands of gates


while still learning the classical fundamentals of digital design [2], [3], [4]. There are many advantages using CAE tools-based digital design compared to traditional pen-paper based design. In the former method, digital designers have the possibility to design their systems at a higher level of abstraction by using a hardware description language such as VHDL. In this method, designers have to think only in terms of functionality, CAE tools take care of the implementation details [5]. The updated structure of the course, now called digital systems design with VHDL, integrated two important technologies: the industry widely used Altera’s Max+Plus II (PC-based design package) software development toolset, which provides most of the desired features (design entry, simulation, verification, synthesis, programming, etc) and CPLD/FPGA devices.

2. VHDL DESIGN ENTRY: OVERVIEW With Verilog, VHDL is probably the most widely accepted and used hardware description language by the microelectronic IC design community in industry and academia. It is supported by most electronic design automation tools (EDA) and extensively used in the logic integrated circuit design cycle implementation. VHDL is a double acronym. It stands for VHSIC Hardware Description Language where VHSIC in turn stands for Very-High-Speed-Integrated-Circuits. It is like Pascal or C programming languages with added features that allow complex design concepts to be expressed as computer programs. VHDL, an industry-IEEE-standard hardware description language tool used to describe the inputs and outputs behavior and function of circuits from the abstract to the concrete level. The language is flexible and technologically independent. In other words, it offers portability across different CAE tools that support VHDL, and different types of programmable logic devices. VHDL is well suited for hierarchical design. The language allows digital systems designs to be described in either strategy: top-down behavioral level design or bottom-up structural level design. The former level describes a system with the highest level of abstraction, whereas the latter describes a system as an interconnection of logical components and gates to perform a desired function. While very powerful in describing a digital design behaviorally, VHDL can be used to mix both structural and behavioral models in the same design. This hardware description language allows the behavior or structure of complex digital electronic circuits to be captured into a design system for automatic circuit synthesis or for system simulation. It can describe lowlevel gates up to very large systems. Due to the strong presence of the hardware language in the integrated circuit design cycle and design automation industry and its growing popularity, no digital systems designer can afford to ignore VHDL-based design. This latter has become an essential topic in today’s electrical and computer engineering curricula. For the above and other reasons, the digital systems design with VHDL course emphasizes on covering as much of the language as possible [6], [7].

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3. MAX + PLUS II DESIGN PROCESS The two leading FPGA companies –Altera and Xilinx- offer comparable technology. However, Altera’s development tools are found to be simpler to use. Another argument which led to opt for Alterabased tools is the CIC-310 low-cost development board. It contains the necessary resources a designers needs to create, implement, and test a logic design. It has a rich set of input and output devices making it an ideal tool for a first course in digital systems. For the above reasons and the familiarity of the authors with these types of tools we decided to use Altera’s FPGAs for this course. The Altera Multiple Array matriX Programmable Logic User System (Max + Plus II) is a fairly complete software package. It provides a multi-platform (editor, compiler, waveform generator, simulator, programmer,…), architecture-independent design environment that ensures design entry, quick processing, and straightforward device programming [8]. Fig. 1 shows a typical Max + Plus II design cycle implementation. The starting point of a new project is the design capture. Design capture is the process of entering the design into the CAE system. The MAX+PLUS II development software provides for both schematic and text entry of a systems design. The Graphic Editor is used to enter the schematic drawing of a system, whereas the Text Editor is used to enter text design files (TDFs) using either VHDL, Verilog or Altera HDL (AHDL). The syntax coloring command of the text editor when enabled, improves the TDF readability and makes it more visible by displaying different parts of the program code in different colors Fig. 2.

Fig. 2. VHDL source code


Design Entry Methods x x

Schematic Capture HDL Text Editor

Compile Project

Repeat if it does not match

Correct I/O assignment with Floorplan Editor Create Test Vectors for Simulation Using Waveform Editor No

Functional Simulation ? Yes Timing Simulation ?

Generated outputs Differ from expected

Design functionally correct

FPGA Programming & In-circuit verification of the actual device against original requirements Results OK ?

No

Yes End of Prototype Fig. 1 Design Cycle Implementation.

It is in the Floorplan Editor where the user assigns the actual input and output pins of the circuit. After all assignments have been made the design is compiled again. In order to check the correctness of the design once compiled without errors, it is necessary to verify that it functions as expected. Simulating the performance of a circuit is an important part of the synthesis process. It gives the designer an opportunity to see if there are any problems before the actual programming of the chip. To simulate the project, the designer uses the Waveform Editor to provide the simulator with input vectors which in turn generates simulating results in the form of a timing diagram. After programming the chip, we can check for functionality. The easiest way is to connect the output(s) to LED(s), and data inputs to logic switches. Once an FPGA design is verified and validated, it is then, possible to manufacture it as an application specific integrated circuit (ASIC) and hence make a “hard-copy” of the prototype.


laboratory session. The course prerequisites include computer programming and active devices. Initially, in the first semester, the digital systems design course was designed to teach students the fundamentals of digital logic. The course devoted substantial time and resources to manual methods. This includes: information representation (number systems and floating point arithmetic), two-valued Boolean algebra, logic gates, logic minimization such as Karnaugh map and Quine-McClusky, combinational circuit analysis and design, and basic sequential circuits (latches, flip-flops, counters, and registers). Also included is an important chapter entitled: “integrated circuits logic families”. In this chapter, the electronic aspects of digital circuits are presented. Students are taught how the basic logic gates are implemented at the transistor level, and the various factors that affect circuit performance such as: propagation delay, power consumption and fan-out. The emphasis is on the most recent technologies with particular focus on CMOS technology and programmable logic devices as well as on interfacing techniques between logic types. To provide necessary background for the second part, a new chapter entitled “simple programmable logic devices (SPLDs) architecture” has been included. This chapter exposes students to the architecture of SPLDs such as: PLAs, PALs and PROMs devices where students are required to generate manually fuse map information for simple designs. In the updated version, the course introduces CAE tools as used in industry. The teaching of VHDL was integrated throughout the course, whenever logic gates, combinational circuits, flip-flops etc are introduced in class; students were given VHDL description of them as “cookbook” examples. This learn by examples approach provided a basic knowledge of language structure and syntax and due to the complexity of the language, we introduced only a subset of the VHDL language sufficient to develop FPGA-based designs. This subset consisted mainly of VHDL constructs such as: Entity, Architecture, Signals, Sequential Statements such as IF-THEN-ELSE, CASE…WHEN, etc,. In the laboratory, students will acquire the practical working knowledge by designing digital systems using CAE tools and SRAM-based FPGA platforms. The authors redesigned two sets of laboratory assignments. In the first, the experiments dealt with designs at component-level whereas the second set dealt with experiments at the system-level. These sets of

4. COURSE STRUCTURE The digital systems design with VHDL is a one-year course. The course meets on week basis, each week consists of three hours lectures and one three-hour

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laboratory

assignments

and

the

developed

new


laboratory projects were designed with two-fold objectives: iTo provide a smooth transition between designing with off-the-shelf standard integrated circuits using bread-boards and wires, and FPGA-based board using Max+Plus II and VHDL iiTo teach students a good design methodology and a fairly strong command of the CAE tools. The first laboratory experiment illustrates Pascal data types, it highlights the differences between byte, integer, longint, and real data types. The next three experiments were carried out using standard off-the-shelf TTL 74xxx chips, wires and protoboards. They took students through the basics of applying standard synthesis methods for combinational logic and troubleshooting circuits on a protoboard. The goal behind starting the laboratory work using 74xxx series was to alleviate the students’ hardware background and help them gain an understanding of the basic digital logic devices, chips, and pins. Also, to enhance their capability to read and use a data-book as well as to get handy with good practice of how all these can be interconnected to construct a digital system. The next experiment was dedicated to a 4-bit BCD adder / subtractor using 2-bit adder chips and gates. The main objective behind this fifth laboratory experiment is to show the hardness constructing relatively complex circuits on protoboards with several chips and a huge amount of wiring interconnections. Not a single hardware implementation did run correctly, and students spent most of their laboratory time rewiring and troubleshooting their circuits. The next four labs involved the use of Max+Plus II and VHDL. The first of the series was devoted to the Altera’s Max+Plus II software supported by a step by step tutorial. The remaining laboratory experiments involved the design of simple combinational and arithmetic circuits using both schematic capture and VHDL design entry methods. In the last experiment, students entered the same 4-bit BCD adder /subtractor of experiment five and performed functional and timing simulation before mapping the error-free design on an FPGA. By undertaking this last design, students understood the advantages of using VHDL for design entry. In the second part of the course and as students gained experience using the schematic capture design entry and basic VHDL constructs, advanced topics were gradually introduced with an emphasis on modular and hierarchical design concepts in order to build complex designs. These advanced topics and associated laboratory experiments include: modular combinational logic using decoders and multiplexers circuit structures, multipliers, barrel shifters, arithmetic and logic unit, standard sequential circuits (updown counter, shift-registers), Mealy and Moore model finite state machines, and memories. As a final project, it was required from students to design and implement an FPGA-based 8-bit datapath system (ALU, register file, and their interconnection paths) capable of performing the basic arithmetic operations and the fundamental logic operations Fig. 3.


The digital systems design with VHDL laboratory experiments are carried out in the Digital Laboratory of the Electrical Engineering Department. The laboratory consists of 10 Pentium machines running Windows XP. Each station has one Development Board, the CIC-310 CPLD/FPGA, one Digi-Designer, and various oscilloscopes and function generators. The Development Board is self-contained system. It is centered around a FLEX 10K SRAM-based FPGA. The board has a wide variety of peripheral input/output devices. Specifically, the board has the following front panel: x Three banks of eight logic switches each for data input. x Two banks of 16 LEDs each to observe outputs. x Four debounced push-buttons for input. x Six 7-segment and one 16-segment displays. x A microcontroller used to load the configuration data to the FPGA or the EEPROM devices via RS232 serial port. The prototyping-board contains a “FLEX 10K” SRAMbased FPGA into which the bitstream of the student’s design is loaded via a download cable.

B. Example: A 4-bit up Counter with Clear The example below shows how a 4-bit unsigned positive-edge triggered up counter with an asynchronous active-high clear is translated into a VHDL code. Fig. 4 illustrates the Max + Plus VHDL Text Editor with the above counter’s VHDL source code, while Fig. 5, shows the timing simulation of the same design. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_unsigned.all; ENTITY counter_1 IS port ( Cnt, CLR: in std_logic; Q : out std_logic_vector(3 downto 0); END counter_1; ARCHITECTURE bhv OF counter_1 IS Signal value : std_logic_vector(3 downto 0); begin process (Cnt, CLR) begin if (CLR=’1’) then value