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High-Voltage and Low-Leakage-Current Gate. Recessed Normally-Off GaN MIS-HEMTs. With Dual Gate Insulator Employing. PEALD-SiNx/RF-Sputtered-HfO2.
IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 2, FEBRUARY 2014

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High-Voltage and Low-Leakage-Current Gate Recessed Normally-Off GaN MIS-HEMTs With Dual Gate Insulator Employing PEALD-SiNx/RF-Sputtered-HfO2 Woojin Choi, Ogyun Seok, Hojin Ryu, Ho-Young Cha, and Kwang-Seok Seo

Abstract— To fabricate gate recessed normally-off AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors, we have employed a novel SiNx /HfO2 dual gate insulator. A plasma enhanced atomic layer deposition (PEALD) technique was used for very thin high quality SiNx (5 nm) as an interfacial layer followed by RF-sputtered HfO2 as a high-k dielectric for the second gate insulator structure. The PEALD SiNx interfacial layer effectively suppresses the forward gate leakage current and the current collapse. We have achieved excellent characteristics such as large threshold voltage of 1.65 V, high breakdown voltage of 900 V, extremely small off-state drain leakage current less than 10−9 A/mm and high ON / OFF drain current ratio of ∼109 , low on-state resistance of 1.84 m · cm2 , and small subthreshold slope of 85 mV/decade. Index Terms— Dual gate insulator, GaN, hafnium oxide, metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs), plasma enhanced atomic layer deposition (PEALD), RF-sputtering, silicon nitride.

I. I NTRODUCTION ATE insulator is the key technology in gate recessed normally-off GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs). Various dielectric materials were tried for gate insulator, such as SiO2 , SiNx , Al2 O3 , AlN, HfO2 , ZrO2 , La2 O3 , and Ta2 O5 [1]. Among these materials, high-k dielectrics with k > 20 have advantages for good channel controllability which leads to low OFF-state leakage current, high ON-state current, high ON/OFF current ratio, and low sub-threshold slope. These characteristics enable low power loss at OFF-state and high efficiency in the power conversion system. Meanwhile, there was a recent study to improve the interface quality of gate recessed normally-off GaN MIS-HEMTs by employing a double-insulator gate [2]. A thermally oxidized AlON was applied as an interfacial

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Manuscript received November 12, 2013; revised November 27, 2013; accepted November 28, 2013. Date of publication December 13, 2013; date of current version January 23, 2014. This work was supported by the Nano Material Technology Development Program through the National Research Foundation of Korea grant funded by the Korean Government under Grant 2012M3A7B4035145. The review of this letter was arranged by Editor S.-H. Ryu. W. Choi, O. Seok, H. Ryu, and K.-S. Seo are with the Department of Electrical and Computer Engineering and Inter-University Semiconductor Research Center, Seoul National University, Seoul 151-744, Korea (e-mail: [email protected]). H.-Y. Cha is with the School of Electronic and Electrical Engineering, Hongik University, Seoul 121-791, Korea. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2013.2293579

layer, demonstrating that a dual gate insulator structure had advantages for interface property. RF-sputtering technique with inherent process simplicity and versatility has been recently applied for gate dielectrics on GaN such as SiO2 [3], TaOx Ny [4], and HfO2 [5]. The numbers of studies on GaN MIS-HEMTs employing sputtered gate dielectric have been limited, mainly due to the difficulty of eliminating the ion-induced bombardment damage to GaN surface [3] that degrades the interface property. In case of normally-off MIS-HEMTs, the sputtered gate insulator/GaN interface of poor quality is becoming closer to the channel electrons and the issues related to the GaN surface, such as forward biased gate leakage current and current collapse, would be more serious. Recently, GaN MIS-HEMTs with sputtered dielectrics have demonstrated good device performances by employing low RF plasma power [3]–[5], but normally-off device has been not reported with sputtered gate dielectric. On the other hand, silicon nitride (SiNx ) has been widely applied as passivation films in AlGaN/GaN HEMTs to reduce the current collapse because of its excellent interface property, which might imply that a high quality thin SiNx film is a good candidate for an interfacial MIS dielectric for GaN MIS-HEMTs. Excellent GaN MIS-HEMTs were fabricated with in-situ metal organic chemical vapor deposition (MOCVD)-grown SiNx as an interfacial layer [6]. However, this technique is not suitable for gate recessed normally-off MIS-HEMT configuration and thus other deposition technique for high quality silicon nitride needs to be investigated. In this letter, we propose a novel dual gate insulator for gate recessed normally-off GaN MIS-HEMTs, employing high quality PEALD-SiNx and RF-sputtered high-k HfO2 . Excellent performances such as high breakdown voltage and low drain leakage current were obtained. II. D EVICE FABRICATION Fig. 1(a) shows the cross-sectional schematic of the fabricated gate recessed GaN MIS-HEMT. The employed epitaxial structure included a 4 nm undoped GaN cap, a 24 nm undoped Al0.23 Ga0.77 N barrier, a 1 nm AlN spacer, and a 5 μm undoped GaN buffer layer on Si (111) wafer. The electron mobility and sheet carrier concentration were 1600 cm2 /V· s and 1 × 1013 cm−2 , respectively. The process started with mesa isolation and gate recess etching using BC3 /Cl2 gas mixture. As illustrated in Fig. 1(b), the AlGaN layer under the gate contact region was completely etched. The samples were cleaned by sulfuric peroxide mixture (SPM) and diluted

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IEEE ELECTRON DEVICE LETTERS, VOL. 35, NO. 2, FEBRUARY 2014

Fig. 1. (a) Cross-sectional schematic of gate recessed GaN MIS-HEMT with 5 nm PEALD SiNx /25 nm RF-sputtered HfO2 as gate insulator. (b) TEM image of recessed gate region showing 5 nm PEALD SiNx and sputtered HfO2 at GaN interface, and fully removed AlGaN barrier layer with sloped profile.

HF (1:10) and a 10 nm SiNx was deposited by inductively coupled plasma chemical vapor deposition (ICP-CVD) for prepassivation film. A Si/Ti/Al/Mo/Au (= 5/20/80/35/50 nm) metal stack was evaporated for ohmic contact and annealed by rapid thermal annealing (RTA) at 780 °C for 1 minute in nitrogen ambient. The contact resistance was 0.45  · mm. After ohmic contact, the pre-passivated SiNx film, which might have been damaged by ohmic annealing, was removed by buffered oxide etchant (BOE) for 2 min, and the sample was immediately loaded into the ICP-CVD chamber. A 5 nm-thick high quality PEALD SiNx for an interfacial layer was deposited by our conventional ICP-CVD system at 350 °C with SiH4 and N2 as precursors of Si and N, respectively. Our detailed PEALD SiNx process in this letter was same as presented in [7]. We deposited PEALD SiNx with the RF source power of 600 W at the pressure of 60 mTorr for N2 plasma step, and non-plasma SiH4 gas flow at the pressure of 70 mTorr for silicon adsorption step. The deposition rate of PEALD process was about 0.5 Å/cycle. After the PEALD SiNx deposition, a 25 nm RF-sputtered HfO2 as a second high-k dielectric was deposited under process pressure of 3 mTorr at a low power of 50W to minimize the sputtering damage with low deposition rate of 7.5 Å/min. A 30 nm thick HfO2 deposited only with RF-sputtering for the control sample. A post-deposition annealing was performed at 500 °C for 10 min in N2 ambient, and a Ni/Au (= 40/360 nm) was evaporated for the gate electrode. The cross-sectional transmission electron microscopy (TEM) image of recessed gate region with sloped etch profile is shown in Fig. 1(b). A 5 nm-thick PEALD SiNx under the HfO2 dielectric layer was clearly identified as an interfacial layer. III. E XPERIMENTAL R ESULTS Fig. 2(a) shows the gate leakage current of the devices without and with PEALD SiNx interfacial layer. Measured gate leakage current under the forward and the reverse bias was asymmetric. This phenomenon could be also observed in other reported high-k dielectrics on GaN MIS devices [6]. To operate normally-off switching devices, large forward biased gate leakage current could give rise to serious problems because the gate insulator should be highly positive-biased for ON-state. With PEALD SiNx interfacial layer, the gate leakage current was significantly reduced by three orders of magnitude. The suppression of the forward biased gate leakage current with high quality in-situ MOCVD-grown SiNx as

Fig. 2. (a) Gate leakage current characteristics of the device (red circle) without and (blue circle) with PEALD SiNx interfacial layer are shown. (b) C-V characteristics of recessed MIS capacitor with PEALD SiNx are plotted and ∼300 mV hysteresis was observed.

Fig. 3. Transfer characteristics of (red line) without and (blue line) with PEALD SiNx interfacial layer at VD = 10 V (a) linear-scaled plot (solid line) for drain current and (dashed line) for transconductance (gm ), and (b) log-scaled plot (solid line) for drain current and (dashed line) for gate current.

an interfacial layer could also be found in [6]. Very thin (5 nm) PEALD SiNx film studied in this letter exhibited a large breakdown field of 11 MV/cm with a large conduction band offset of 2.44 eV between SiNx and GaN calculated by Fowler-Nordheim plot, demonstrating the excellent quality of PEALD SiNx [7]. Capacitance-voltage (C-V) characteristics were measured for both samples with the recessed MIS capacitor diameter of 200 μm, and the characteristics of the sample with PEALD SiNx are shown in Fig. 2(b) with ∼300 mV hysteresis. The C-V characteristic of the sample without PEALD SiNx is not included, because the capacitance was significantly collapsed with increasing gate voltage due to extremely large conductance. Transfer characteristics of the devices without and with PEALD SiNx interfacial layer were measured. As shown in Fig. 3, the device without interfacial layer could not modulate the channel charges with gate voltage more than 4 V due to large amount of gate leakage current, resulting in small maximum drain current. On the other hand, the device with an interfacial SiNx operated well with the gate voltage of 6 V. Threshold voltage of the device with PEALD SiNx interfacial layer was 1.65 V when defined at the drain current of 1 mA/mm. The maximum drain current was 600 mA/mm and the maximum transconductance (gm,max ) was 170 mS/mm. The high drive current is attributed to good epitaxial layer, low damage gate recess etching, and excellent interface quality. Due to good channel controllability enabled by dual gate insulator including a high-k dielectric material, the offstate drain leakage current was extremely small (lower than 10−9 A/mm), and thus very high ON/OFF drain current ratio (∼109) and low subthreshold slope (∼ 85 mV/dec) were obtained. It is noted that the obtained values are better than

CHOI et al.: HIGH-VOLTAGE AND LOW-LEAKAGE-CURRENT GATE RECESSED NORMALLY-OFF GaN MIS-HEMTs

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was calculated as 1.84 m · cm2 in the device with PEALD SiNx interfacial layer. The breakdown voltage of the device with PEALD SiNx was measured and plotted in Fig. 5(a). The breakdown voltage was as high as 900 V at the drain leakage current of 0.1 μA/mm with VGS = 0 V, and the hard breakdown occurred at VD = 990 V. Benchmarked Ron,sp versus breakdown voltage plots including other reported normally-off GaN MIS-HEMT data [8], [10]–[12] are shown in Fig. 5(b), which demonstrates the excellent performance of GaN MIS-HEMTs fabricated in this letter. Fig. 4. Pulsed I-V characteristics of the devices were measured with the pulse width of 200 ns and the pulse separation of 1 ms.

IV. C ONCLUSION We have proposed a novel dual gate insulator configuration employing PEALD-SiNx /RF-sputtered-HfO2 for gate recessed normally-off GaN MIS-HEMTs. The fabricated device with the dual gate insulator exhibited superior characteristics in breakdown voltage, ON-state resistance, subthreshold slope, and ON/OFF drain current ratio. Though further improvement are needed including improved HfO2 quality and optimized field plate structure, this letter suggest that the proposed dual gate insulator structure has a great potential for normally-off GaN MIS-HEMTs. R EFERENCES

Fig. 5. (a) Off-state breakdown voltage characteristics of the device with PEALD SiNx interfacial layer at VGS = 0 V. (b) Breakdown voltage versus Ron,sp is plotted with other reported normally-off GaN MIS-HEMTs.

other outstanding MIS-HEMTs with FinFET structure [8]. These excellent results suggest that the proposed gate insulator stack takes advantages of high quality SiNx interfacial layer and high-k gate insulator simultaneously. However, Vth hysteresis of 350 mV under the maximum gate voltage of +6 V and Vth drift of 940 mV under the gate voltage of +5V for 1000 s with the grounded source and drain were observed. Such Vth instability might be in a large part caused by bulk traps in HfO2 [9]. In order to further investigate the improved interface property, pulsed I-V characteristics were measured for the samples without and with PEALD SiNx interfacial layer, as shown in Fig. 4 Without PEALD SiNx interfacial layer, there were large discrepancies between pulsed I-V characteristics with even low quiescent drain bias point (VD,Q ) of 0 and 10 V. This severe current collapse was greatly suppressed with PEALD SiNx interfacial layer as shown in Fig. 4, suggesting that the interfacial layer indeed played an important role in improving the interface quality. However, significant current collapse was still observed for the sample with PEALD SiNx interfacial layer as the quiescent drain bias was increased further, implying that the PEALD SiNx layer itself would not be enough. On the other hand, there was a recent study on the trap effects in ALD-HfO2 gated AlGaN/GaN MOS-HEMTs [9]. With the investigation on the trap location using the ac-transconductance method, the traps were found to be located in the gate oxide. In order to reduce the current collapse phenomena further at high quiescent bias conditions in HfO2 MIS-HEMTs, more work is needed to improve the quality of HfO2 layer and to optimize the field plate structure. With the slope of the pulsed I-V curve at the VD,Q of 0 V and the active region area of the device (WG × LSD ) taken into account, the specific ON-state resistance (Ron,sp)

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