High Voltage Operational Amplifier Design For Piezoelectric Based Microrobots E.Montané, P. Miribel-Català, S.A. Bota, M. Puig-Vidal, J. Samitier SIC. Sistemes d’Instrumentació i Comunicacions.Departament d’Electrònica. Universitat de Barcelona. C. Martí i Franquès, 1. Barcelona, 08028. Tel. 34-934021141 Fax: 34-934021148 e-mail:
[email protected]
Abstract A high-voltage operational amplifier capable to withstand 80 V has been designed using a commercial BCD (Bipolar, CMOS and DMOS) technology. The use of a source cross-coupled pair input differential amplifier instead of classical single common source solution has been used in order to improve the internal slew-rate behavior of the amplifier to increase the speed of the system. Circuit will be used to drive piezoceramic actuators, which demand high voltage – high current operation.
1. Introduction During last years, a great effort in high precision robotic systems is being developed in order to achieve higher resolution operation conditions, by decreasing the size of the actuator unit of the robot. Unfortunately, these units are currently based on commercial piezo-ceramic materials, which demand high voltage biasing. CMOS standard integrated technologies are not capable to withstand this required high voltage biasing, so, usually, driver circuits for these piezoactuators are based on hybrid solutions using discrete components, like operational amplifiers, fabricated under non-standard processes [1]. This fact has suposed a great penalty on the robot performances due to the stress induced by electrical link between driver and robot. Recent developments in material research allow the possibility to use new custom piezoelectric materials with values of bias voltage in the range of 50 V [2]. High voltage accessible technologies could be used to design circuits suitable to drive this new generation of piezoactuators and they could also improve the link between these circuits and the piezoactuators in order to build a microrobot with a considerable reduced size. Our work is focused in the development of a power interface circuit, based on a high voltage operational amplifier, using an standard BCD technology (that allows the combined integration of bipolar, CMOS and DMOS devices on the same substrate). The piezoelectric actuator can be modelled as a capacitor (typical values are in the range of nF).
To obtain a high performance microrobot we have considered speed of the final actuator as a merit figure to be optimized in the design process, but also taking into account that for safety reasons, the working temperature must be restricted in a given range by limiting the power compsumption.
2. High Voltage Technology
A 1.2 µm BCD technology (Bipolar, CMOS, DMOS), HBIMOSF from MIETEC-ALCATEL is used to design these specific Smart Power Integrated Drivers. Using this technology it is possible to integrate, on the same substrate, power and control devices. Standard low voltage analogue and digital circuitry could also be implemented using standard library cells. DMOS transistors are frequently used in power blocks. As a difference with standard NMOS and PMOS transistors, NDMOS and PDMOS devices are able to withstand high voltage, with breakdown voltages arround 80 V, although voltage difference between gate and source is limited to 20 V or less. Two possible NDMOS transistors can be implemented: floating and non-floating devices. Floating transistors, labelled as FNDMOS, presents a greater threshold voltage (VT=7 V) than non-floating ones (labelled as NDMOS, VT=1 V). Also precision resistors and High Voltage Zener diodes can be used in this BCD technology. As a practical design aspect, we have to notice that power devices have a high cost in terms of area because they need to be laid with guard rings. Designer must try to minimize the number of these devices and their size in order to achieve a reasonable waste of area.
3. Operational Amplifier Architecture Usual operational amplifier architecture consists of an input common source diferential amplifier (Fig. 1) followed by some gain stages. Input differential amplifier is used mainly to reject common mode signal. The low value of gain of this amplifier stage is increased to acceptable values by adding gain stages between its output and the output of the operational amplifier.
Due to fact that the current in any branch of the differential amplifier stage can not exceed the total bias current Ibias, this architecture show an inherent slew-rate limitation, related to the fact that current that flows in the stage drives the input capacitor of the following stage. Considering the high size needed of the output transistors in order to deliver high current to the piezoelectric actuator, the capacitance of their gates will be high, in the order of pF, and it’s necessary to charge them in an efficient way, not provided by standard solution. To increase the speed of this charge static compsumption must be increased, but this solution is not allowed by thermal constraints. The Cross-coupled input diferential amplifier [3] is an useful solution to avoid this limitation. In Fig.2 it can be shown a complete class AB OTA build using this input configuration. Input diferential amplifier consists of two branches connected to each input. The external branches are used to generate appropiate voltage bias for the internal cross-coupled branches. When a positive diferential voltage is applied between the inputs V+ and V_, there is an increase of the gateto-source voltage in the input transistor of the positive cross-coupled branch that causes a relative current increase in the pull-up PMOS transistor and in the pull-down devices of the opposite branch. The current imbalance is delivered to the input of the next stage. The main goal of this architecture is that maximum current can flow by any branch is only limited by input voltage margins, there is not any inherent limitation like common source case. Due to this fact, the charge of the gate capacitance of the output transistors becomes more efficient.
Fig.1. Common source diferential input stage
4. High Voltage Operational Amplifier Design The schematic at transistor level of the High Voltage Operational Amplifier is presented in Fig.3, in which power DMOS transistors have been labelled as PD, ND and FD. Topics used to design the final structure can be summarized in the following tips: - The most useful configuration for the robot power driver involves low voltage input values due to the fact that is better to control final driver by means of a low voltage input circuitry. The complementary version of Fig.2 is used due to the fact that higher low input margin is achieved using PMOS input transistors. An input source follower is also used to increase this margin.
Fig. 2. Cross-coupled input stage operational amplifier
- Output power transistors are designed to obtain a maximum current output level of 6mA to assure safety temperature conditions of the system. This fact is achieved limiting VGS value of output transistors using Zener diodes. - DMOS transistors are used to withstand high voltage. Because their size, every branch includes one DMOS transistor whenever is possible. - In the circuit of Fig.2, voltage value of gate terminal of output transistors is defined through a diode connected transistors in a current mirror configuration. Using this configuration, relationship between static current and output current is defined by the relationship between both transistors. To optimize the power comsumption of the circuit is better to use an amplifier stage for the output transistor as can be seen in Fig. 3. This solution use to envolve the addition of a compensation capacitor between input and output nodes of gain stage. The piezoactuator can be modelled as a 25nF capacitor. This high value for the capacitive load applied to operational amplifier output allows the supression of compensation capacitor with a proper design. The capacitors that can be implemented with the BCD technology have a low value of capacitance per unit area and they are not capable to withstand high voltage values between their terminals. Series connection of high size capacitors are needed to build a high voltage capacitor. The supression of these capacitors is one of the best solutions to decrease the waste of area of the final design. - Current needed to bias the circuit has been delivered by a High Voltage version of a classical low-voltage beta-multiplier autopolarization reference circuit [4] wich includes a new start-up circuit that uses a Zener diode to cut-off this startup circuit when static behaviour of reference is achieved (Fig. 4).
Fig. 3. Final design of the High Voltage Operational Amplifier. The label PD designes Power PDMOS transistors, ND power NDMOS transistors and, FD floating power NDMOS transistors
The whole amplifier configuration will include the integrated resistors to define internally the value of the gain, 16 in our case, as can be seen in Fig. 5.
Fig. 5 . Driver circuit configuration.
4. Layout aspects Fig. 4. Autopolarization reference circuit
Current delivered by the reference circuit could be obtained using the following equation:
2 I= Rβ MN 1
1 1 − K
2
Where K is the relationship between the β of transistors MN2 and MN1.
Some design rules to reduce the coupling between power and low-voltage transistors of the circuit has been taken into account at layout level: -
Power transistors are located in the centre of the design and have been isolated from lowvoltage transistor by means of a majority carriers guard ring. Taken into account that substrate in this technology is P-doped, this guard ring has been implemented by means of a ground connected P+ diffusion to collect holes flowing by substrate.
Fig. 6. Location of the different transistors in the layout
-
High voltage PMOS and power PDMOS transistors, located inside the majority carriers guard ring, have been isolated also from NDMOS and FNDMOS power devices by means of a minority carriers guard ring, implemented using N type wells in order to collect electrons flowing by the substrate.
In Fig. 6 were depicted these topics in a graphical way, by means of the location of the different transistors inside the whole chip. A photograph of the integrated circuit is presented in Fig. 7 and Fig.8, that represent, respectively, detailed views of the power part and low-voltage part of the circuit. In Table 1 are presented the final dimensions of the transistors. Bias current is 15 µA, delivered by the reference circuit, that could be observed in Fig. 9.
Fig. 7 . Power transistors. Fig. 8 . Low voltage transistors.
Transistor I54, I56 I39 I55, I57 I37,I38 I49, I4 I11, I12 I5, I6 I13, I14, I43, I44 I9, I10, I52, I53
µm) W (µ 25 5.5 5.5 65 85 5.5 15 300 200
µm) L (µ 5 5 15 5 5 3 3 5 5
Type PDMOS PDMOS PMOS PDMOS PMOSHV FNDMOS FNDMOS PMOS NMOS Fig. 10 . DC transfer of the driver.
Table 1 . Sizes of the transistors.
Fig. 10 represents the AC behaviour of the driver. A cut-off frequency of 2.5KHz is obtained. This low value is needed due to the fact that piezoceramic materials exhibit a ressonance frequency in the order of 10KHz. Also power constraints, due to the high voltage biasing and the high value of the capacitance limit the maximum frequency to 1KHz.
Fig. 9 . Photograph of the Reference circuit.
5. Experimental results Fig. 10 represents the DC transfer of the amplifier. Due to the fact that source-coupled input amplifiers usually exhibit higher level of offset [4], we control externally the voltage value on the operational amplifier positive input to reduce it. Good results are obtained using a value of 4.6V.
Fig. 11 . AC transfer of the driver.
Fig. 12 . Output of the driver for a 100 Hz sinusoidal input. Input amplitude 5 V, Output amplitude 76.8 V.
In Fig. 12 is depicted the output of the driver for a sinusoidal input signal of 100Hz. A good behaviour of the driver could be observed.
Acknowledgements This work has been partially support by European ESPRIT project 33915. References
5. Conclusion A high voltage operational amplifier has been designed to obtain a high performance power driver for piezoelectric actuators. Good results obtained have involved as a conclusion the future assembly with the microrobot. These devices will be tested in a few months.
[1] S. Fatikov, U. Rembold " Microsystem Technology and Microrobotics". Springer. Berlin 1997. [2] M. Bexell, S. Johasson "Fabrication and evaluation of a piezoelectric miniature motor" Sensor and Actuators A - Physical, 1999, vol 75. Nº 1, pp 8-16. [3] R. Castello, P.R. Gray, "A High-performance micropower switched-capacitor filter" IEEE JSSC, Vol. SC-20, No. 6, 1985, pp. 1112-1132. [4] M.G. Degrauwe, J. Rijmenants, E.A. Vittoz, H.J. De Man, " Adaptive Biasing CMOS Amplifiers" IEEE JSSC, Vol. SC-17, No. 3, June 1982, pp. 522-528.
