High-Voltage Pulsed-Power Supply Operating at ... - IEEE Xplore

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IEEE TRANSACTIONS ON PLASMA SCIENCE, VOL. 43, NO. 9, SEPTEMBER 2015

High-Voltage Pulsed-Power Supply Operating at Repetitive Discharge Mode for Driving Very Small Plasma Focus Devices Hossein Jafari, Morteza Habibi, and Hamid Reza Aali Vaneghi Abstract— The technology of switched-mode power supplies (SMPSs) has been employed to design and build a much simpler and portable high-voltage pulsed-power supply (HVPPS) as an efficient pulse drive unit for very small plasma focus devices (PFDs). The HVPPS is designed in such a way that it is able to charge a low-energy capacitor bank (84 nF, 7 kV, 2.1 J), from 4 to 7 kV at a repetitive discharge mode of 5 Hz. All control processes are carried out via a laptop through a graphical interface, written in C# language. The experimental runs were carried out in argon at 4-mbar gas pressure and the 7-kV maximum charging voltage level of the HVPPS. The results of diagnostics at a repetitive discharge mode of 5 Hz successfully confirmed the accurate performance of the SMPS and the spark gap switch for driving a very small PFD. The rise time of 10%–90% of the charging voltage, at each single-shot trace was obtained to be 110 ms. This consequence demonstrated that the control and sampling circuits were being implemented as well. After discharging, the pinching evidence was genuinely observed in the capacitor bank voltage trace. The quarter period of the discharge traces was observed to be 100 ns, which leads to a total system inductance of about 48 nH. The measured inductance was low enough to be compatible with successful performance of the very low energy PFD, leading to fast and high magnitude discharge pulses to assist the pinching evidence. This HVPPS could emerge as one of the very low cost, compact, light weight, and highly efficient power supplies used for driving the very small PFDs so far. Index Terms— Discharge voltage and current traces, high-voltage pulsed-power supply (HVPPS), repetitive discharge mode, very small plasma focus device (PFD).

I. I NTRODUCTION

D

URING the last decades, high-voltage pulsed-power supplies (HVPPSs) operating at repetitive discharge mode have been widely used in various scientific researches and industrial applications. The plasma focus device (PFD) driven by means of an HVPPS is one of the most noteworthy apparatus that has been extensively studied as a pulsed radiation device in engineering applications like substance detection, microlithography, X-ray imaging, and medical neutron therapies [1]. The PFDs consist of a low pressure gas-filled chamber in which two electrodes are provided.

Manuscript received April 12, 2015; revised July 15, 2015; accepted July 24, 2015. Date of publication August 14, 2015; date of current version September 9, 2015. The authors are with the Amirkabir University of Technology (Tehran Polytechnic), Tehran 15875-4413, Iran (e-mail: [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPS.2015.2461595

Then by applying a pulsed high voltage (HV) across the electrodes a short-duration high-density plasma region is created at the open end of the electrodes, entailing the conditions of controlled fusion reactions. Many remarkable studies have been performed in PFDs with various ranges of energies from less than 1 J–1 MJ. Nevertheless, recent works have shown that the plasma-physics scientists and engineers are interested in employing very low energy devices such as relatively stable sources of X-ray, neutron beams, and charged particles, because of their being capable of working at a repetitive discharge mode from hertz to kilohertz and being compact, portable, and safer devices [2]. To achieve such that purpose, the significant part of the last decade’s researches have been geared toward designing and building very low energy PFDs and their compact and portable HVPPSs operating at a repetitive discharge mode. The HVPPS is comprised of a HV power supply, a capacitor bank, and a triggering module. The performance of an HVPPS in driving a PFD is in such a way that during a sufficient time (regarding the PFD’s bank energy and the output power of the power supply, it is of the order of a few milliseconds to a few seconds), the electrical energy is stored in the capacitor bank. Then, during a few nanoseconds to a few milliseconds, the bank energy is discharged through the plasma chamber commonly by means of a spark gap switch. The power electronics used as pulsed-power generations, and the pulse voltage multiplier circuits [3], [4] are the most utilized and proposed HV power supply to charge the capacitor bank of PFDs. In the following, we summarize the extension of the recent research studies on HVPPS for energizing the PFDs operating at single or repetitive operation modes. The battery (24 V dc, 7.5 A) powered tabletop miniature PFD, having a single capacitor (200 J, 4.0 μF, 10 nH) has been reported [1] that uses a dc-to-dc converter to charge the bank energy of 10 kV in 10 s and also provides a 30-kV trigger pulse for the spark gap switch. The 15-kV/100-mA constant-voltage power supply has been used [5] for charging the capacitor bank of the FMPF-1 device (270 J, 2.4 μF, 27 ± 2 nH), incorporating a high-frequency series-resonant inverter. The FMPF-1 uses a trigatron switch with an operating voltage range of 8–18 kV and a trigger voltage of about −20 kV to operate in the single shot mode. The FMPF-2 device (135 J, 2.4 μF, 56 ± 3) has employed [5] a constant-voltage power supply (1–40 kV/450 mA, 9 kJ/s) and a trigatron spark gap switch (operating voltage of 10–40 kV, trigger voltage of about 20 kV) for operating at a repetitive mode up to 10 Hz.

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JAFARI et al.: HVPPS OPERATING AT REPETITIVE DISCHARGE MODE FOR DRIVING VERY SMALL PFDs

The compact and miniature PFD (75 J, 8.4 μF, 60 nH) composed of an astable multivibrator driven by a 12 V battery, a 1.5-kV rms HV transformer, and a voltage-doubler circuit has been reported [6] that operates at the lowest voltage of 4.2 kV among all those reported for PFDs. The capacitor bank energy of this miniature PFD is switched by a manual operating switch as a single shot. The next report about this miniature PFD with the same bank energy has been presented [7] to drive the PFD at 50-Hz repetition rate and a charging voltage of 4.2 kV in which the switching of the capacitor bank is done by means of a spark gap. It has been reported [8] that eight parallel solid-state modules with an effective storage capacitance of 36 μF and an output inductance of 12 nH have been designed to operate up to an 85-Hz pulse rate at an 8-kV charging voltage from a variable HV power supply (1150 J, 80 kJ/s), so that the solid-state driver using the snubber diodes successfully power the PFD with no current reversal through the discharge electrodes. There are also many significant attempts that have invested in PFDs with a bank energy in the order of a few kilojoules to achieve repetitive operation mode, creating a high time-averaged neutron or X-ray yields. The NX1 PFD (2.2 kJ, 12 kV) and the NX2 PFD (1.9 kJ, 11.5 kV), a small chamber Mather-type PFD (4.7 kJ, 30 kV), and a mobile and repetitive PFD (6 kJ, 21 kV) are operating at a repetitive frequency mode on 3 and 16 Hz [9], 0.2 Hz [10], and 1 Hz [11], respectively. The voltage multiplier circuits can also be used [12] for some pure scientific research works and industry level applications like particle acceleration and gaseous discharge experiments. Nevertheless, obtaining a fast HV pulse is the main purpose of researchers for driving experiments in PFDs, Z -pinches, capillary discharges, and etc. There are some studies and reports about the design and construction of the HV multiplier circuits [13]. The Blumlein pulse voltage multiplier consisting of a set of transmission lines connected in parallel at the entry and in series at the end has been presented [3] to produce an output fast HV pulse with a multiplication factor of about 4. It has been shown that a nanosecond pulser made by cascading three stages of Blumlein lines (50-kV output peak, 3-nF total cascaded Blumlein capacitance) [14] could provide a constant charging rate of 125 J/s and a maximum pulse repetition rate of the order of 33 Hz. The 32-stage voltage multiplier with a 0–280 V input voltage has been reported [15] to produce an approximately 12-kV maximum output voltage with a slow rise and fall times. The output voltage takes about 1 min to reach its final value, but it takes several hours to fall to zero. Consequently, the user could discharge the bank energy manually every time. The configurations of the voltage multiplier circuits are essentially not suitable for the miniaturization of the pulsedpower supply, so in this note, we present a very compact and portable HVPPS that is utilized for driving a very small PFD in which the repetition rate of discharges is up to 5 Hz. Due to the continuous improvement of the power electronic in designing the very low cost, simpler, compact, and high efficiency pulsed-power devices with operation at a high-frequency charging mode, we use the technology of

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TABLE I S PECIFICATIONS AND R EQUIREMENTS OF THE P ROPOSED F LY-BACK C ONVERTER FOR D RIVING THE V ERY S MALL PFD

switched-mode power supply (SMPS) to design the prototype of the HVPPS. The repetitive discharge operation of an HVPPS has a direct relationship with the electrical parameters of capacitor bank, spark gap switch, and electrodes of the PFD, especially with the total system inductance. Hence, in order to perform fast charging and discharging processes and also to achieve a high magnitude of the discharge current, the total system inductance should be as low as possible [16]–[18]. These results are considered in designing the capacitor bank and the spark gap switch of the system. II. S PECIFICATION AND D ESIGN The average output power of an SMPS depends on the repetition rate of the discharges. For operating the PFD at a discharge frequency of 5 Hz, the time intervals required for each charging process should be less than 200 ms. Hence, by assuming a 50% of reliability coefficient in the charging process of the 84-nF capacitor bank up to a maximum charging voltage of 7 kV, the maximum output power of the SMPS can be calculated to be about 41 W. With respect to this low power level of our power supply, a dc-to-dc fly-back converter is recommended to be used [19]. The fly-back converter is one of the commonly used topologies by which the output current during the start of the charging mode, the charging interval and the final voltage level can be controlled [20]–[22]. The design of the proposed converter for capacitor charging application involves a dc input power, a power switch driver, a HV transformer, a voltage regulation circuit, an output protecting circuit, and a central microcontroller circuit. In our design, the dc input power of the HVPPS equipped with a 220 V ac to 32 V dc power module that provides input voltages related to the fly-back transformer, the protecting circuit as well as the controlling circuit. Since, there is a desire to isolate the digital ground currents from the analog ground currents, a PWA_MD dc/dc converter is provided to prevent the analog noise effect on the operation of the digital elements. Table I shows the design parameters of the proposed HVPPS for driving the very small PFD. A. Fly-Back Transformer Design With respect to the transformer current, the fly-back converter can operate in two distinct modes, i.e., the continuous

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conduction mode (CCM) and the discontinuous conduction mode (DCM). For CCM, the energy stored in the transformer is not completely transferred to the secondary; that is, the converter current is always greater than zero before the next switching cycle. Under this situation, in CCM, the design complication increases due to the difficulty in controlling the output current of the converter efficiently. In our design, due to the relatively low value of the minimum switching frequency and the light load, the diode-rectified fly-back converter allows the secondary current to flow in only one direction and would operate in DCM. DCM fly-back converter is usually the preferred operating mode, due to its simpler control loop implementation and lower turn ON. Before starting the fly-back transformer design, it is important to define the power supply parameters such as input voltage, output power, minimum switching frequency, and maximum duty cycle. Another important parameter that should be taken into account is the estimated power supply efficiency. Since we intended to design a HV power supply, the estimated efficiency was considered to be about 85% as it is recommended. The maximum input power is a function of the output power and the estimated converter efficiency; that is, calculated to be about 48 W. From there, we can calculate the transformer parameters and select an appropriate core. Table I shows the specifications and requirements of the proposed fly-back converter for driving the very small PFD. Using the given variables, the transformer design includes the following steps. 1) Primary Transformer Current: The primary side inductance of the transformer, L p is obtained by Lp =

(Vin · Dmax )2 2Pin · fsw · K RF

(1)

where Dmax is the maximum duty cycle and K RF is the ripple factor. The peak and rms primary side current can be estimated, which would guide the effective core volume calculation and power switch selection. The peak primary current is given by I p( pk) =

2 · Pout(max) . η · Vin · Dmax

(2)

And the primary rms current can be calculated from Dmax . (3) I p(rms) = I p( pk) 3 2) Core Selection: There are two important fundamental equations that are used in high-frequency transformer design, i.e., [23]–[25]. Induced voltage equation for transformers V = 4N Bm Ae fsw .

current density of copper, K w is the window space factor, and Aw is the window area of the chosen core. By combining these fundamental equations, an important equation is derived that assists to select an appropriate core from the transformer core data sheet usually supplied by the manufacture. This equation is defined as a product of effective cross-sectional area and window area as follows: V·I . (6) Ae · Aw = 2K w · Bm · f sw · J The maximum flux density is specified using the information that is found from the core material characteristics Bm = Bs − Br

where Bs is the saturation flux density and Br is the residual flux density. Transformer cores for fly-back converters require an air gap in the core. Air gap, by avoiding saturation under dc bias condition, flattens the hysteresis curve and allows more energy handling by decreasing the permeability of the core [26]. Then, the required length of air gap, l g is calculated as follows: lg =

2 0.4π L p I p( pk)

Ae · Bm2

× 108

(8)

where μ0 , n, L s , and D are the permeability of free space, turns ratio, secondary side inductance, and center pole diameter that is found from the core material characteristics, respectively. Despite the importance of air gap in saturation consideration, however, a compromise between saturation and leakage is always the main criterion in air-gap design. In repetitive discharge mode power supply, the transformer leakage inductance and transistor and rectifier switching speeds play an important role in governing the switching transition times. A high leakage inductance not only slow down the switching transition times due to dumping its energy into a clamp, but also it can prevent the energy stored in mutual inductance from being delivered to the output. Hence, it is important to minimize leakage inductance using cores with long narrow windows, and by distributing the windings by which the efficiency increases. 3) Primary/Secondary Turns: After determining the standard shape core type with its appropriate material, the next step is to calculate the required turns ratio for primary and secondary windings. The minimum number of turns on the primary is defined in terms of the magnetic core area and the allowed operating maximum flux density for the chosen material; that is given by Np =

(4)

And volume of the conductors 2N I = K w · Aw (5) J where V is the primary/secondary voltage, N is the primary/secondary turns of winding, Bm is the maximum flux density, Ae is the effective cross-sectional area of the chosen core, I is the primary/secondary current, J is the

(7)

L p · I p( pk) . Bm · A e

(9)

In this case, the turns ratio and the number of turns for secondary winding can be calculated from n=

Np Vin Dmax = · Ns Vout + V D 1 − Dmax

(10)

where V D is the forward voltage drop of the output rectifier. Next, regarding the current density of copper conductor and current of the windings, the required wire area of the windings


Fig. 1.

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Circuit diagram of the proposed switch driver using IC chip1768. TABLE II F LY-BACK T RANSFORMER PARAMETERS

are obtained. As a result, the wire sizes can be selected using the required area from the standard wire table. For this design, we found the fly-back transformer parameters using the specifications and requirements of the fly-back converter as summarized in Table II. B. Central Microcontroller Circuit In order to manage the effective performance of all circuits and produce a pulsewidth modulated (PWM) signal for driving the power switch, a LPC1768ARM Cortex-M3-based microcontroller is used. PWM switching technique is used for its high power capability and fast transient response to increase the power density and actual efficiency. LPC1768ARM contains seven match registers and a timer by which allows us to configure it at maximum six single-edged PWM outputs or three double-edged PWM outputs. In our application,

we configured LPC1768 at a double-edged PWM signal. Therefore, the frequency always remains to what it was set at the beginning and only the duty cycle changes. The circuit diagram of the proposed switch driver using IC chip1768 is shown in Fig. 1. As shown in Fig. 1, the classical JTAG interface of the chip1768 (pins from 1 to 5) is dedicated for its programming and debugging. Choosing an operating HV level as the charging voltage can be performed by changing the state of one of the output pins of 6–9 from high to low. Output pin 46 provides a minimum switching frequency of 30 kHz as a PWM signal for switching the gate-trigger circuit of the power switch. The choice of the semiconductor technology utilized in this power switch function is influenced by factors such as low cost, peak voltage and current, frequency of operation, and heat sinking. In view of these considerations, a IRF1010E power FET is chosen as the power switch. The MOSFET can be completely turned ON, flowing the drain current i D through the MOSFET, when the gate-to-source voltage slightly exceeds the threshold voltage of switch (VGS(th), typically in the range of 2–4 V). This low threshold voltage of the switch provided by the central microcontroller circuit is due to its low ON-state losses in low voltage ratings, its fast switching speeds, and a high impedance gate that leads to requiring a small voltage and charge to facilitate ON / OFF transition [27]. For attaining the repetitive discharge process in the PFD, regarding the chosen discharge frequency by the user, pin 44 generates a signal to power the trigger circuit of the spark gap switch in a standard format. The trigger circuit can

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Fig. 2.

Circuit diagram of the HV control section.

Fig. 3.

Circuit diagram of the feedback and sampling section.

generate a HV pulse of −15 kV to trigger the spark gap switch during a discharge cycle of 5 Hz. As it is apparent from Fig. 1, an isolating situation has been created by means of an opto-isolator between the chip in/out pins and the trigger circuit to avoid HV from affecting the chip by receiving the signal. There is also a potentiometer in the series with the

PWM signal output, which can tune the operating point of the power switch. C. Feedback and Control Circuits Figs. 2 and 3 show the HV control circuit diagram, the feedback and sampling circuit diagram, respectively.


In this paper, the proposed SMPS would be able to produce the high operating voltage levels from 4 to 7 kV being available in the 1-kV discrete steps. Thus, as shown in Fig. 2, a circuit based on the LM339 quad comparator chip is used to compare the output sample voltage (V _Sample) with each of the four reference voltages. When the voltage across the capacitor bank stepped up to the chosen operating voltage, it is necessary to either drop the input current of the fly-back transformer to zero or connect the gate terminal of the MOSFET to the ground, turning it OFF (Fig. 3). For this purpose, a CD4066 quad bilateral switch chip is used to connect the comparator output (which corresponds to the chosen voltage) to the turn OFF terminal. In this case, as shown in Fig. 3, the related opto-isolator causes the gate terminal of the MOSFET to be connected to the power ground. Higher switching frequency results in the increase of efficiency, and also helps in dimension reduction of components of the HVPPS. Nevertheless, this also leads to an increase in the electromagnetic interference (EMI) and power losses, which brings about a lower efficiency. Thus, during the designing, the choice of switching frequency and components, in order to obtain a high efficiency and prevent EMI should be considered as a tradeoff. To improve the efficiency of the HVPPS, one must be able to identify and roughly quantify the various losses. Losses within an SMPS roughly fall into three categories: 1) magnetic components; 2) winding; and 3) power switch losses. These losses are separately treated due to the occurrence in combination within any lossy component. Core loss is determined by considering the hysteresis and eddy-current losses [24], [28]. However, preliminary core losses can be predicted using a factor found from the transformer core material data sheet, i.e., core loss per volume Pv = Pvf · f sw

(11)

where Pvf is the core loss factor. Core loss factor at a temperature of 25 °C and a minimum switching frequency of 30 kHz is 144 mW/cm3 . Therefore, regarding the core volume and for worst case operation of the transformer core, core loss is calculated to be about 501 mW. It should be noted that as inverter frequency increases, core losses dominate the design. Winding losses are associated with the dc/ac primary and secondary resistance of the windings. As mentioned above, the primary rms current is an aid in estimating the power switch and transformer conduction losses. The primary peak and rms currents are calculated to be 6.03 and 2.46 A, respectively. By calculating the ratio between ac resistance and dc resistance of the primary winding for an operating frequency of 30 kHz, the winding loss of primary side can be calculated as follows: 2 2 + R p(ac) · I p(ac) Ppw = R p(dc) · I p(dc)

(12)

where R p(dc) is the dc resistance of the primary winding, R p(ac) is the ac resistance of the primary winding, and I p(dc) = and Iac =

Dmax · I p( pk) 2

2 − I2 . Irms dc

(13)

(14)

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In a similar manner, the winding loss of secondary side can also be calculated. In this case, winding losses for primary and secondary sides are calculated to be about 34.5 and 108 mW, respectively. The power switch is another prominent source for losses within SMPSs in which the losses are basically associated with the conduction and switching losses [29]. Conduction loss is where the power switch is in the ON-state after the drive. However, switching loss occurs when the power switch has been driven into ON- or OFF-state of operation. Conduction loss Pcond for worst case operation of the IRF1010E power FET can be predicted using high temperature values for drain–source resistor as follows: 2 Pcond = RDS(ON) · I p(rms)

(15)

where RDS(ON) is the drain–source resistance. The drain–source resistance from the power FET data sheet is 12 that leads to a conduction loss of 72 m. For DCM fly-back converters, turn-ON is at zero current and is nearly lossless [28]. Hence, turn- OFF loss are the primary concern, and are a function of turn-OFF switching time, snubber networks and the device technology. For the fly-back supply, switching loss can be calculated from Vin Psw = fsw · · I p(OFF) · tOFF (16) 2 where I p(OFF) is the peak current on the primary at turn-OFF and toff is the turn-OFF switching time. As is observed from (16), a higher switching frequency begins to lead to excessive switching losses. Due to the maximum duty cycle of 0.5, the turn-OFF switching time would be 16.67 μs that leads to a switching loss of 20 mW. As a result, the total loss that includes core losses, winding losses, and power switch losses is calculated to be less than 1 W. This predicted the total loss is well within a common limit loss considered in SMPSs that causes the HVPPS to achieve a high efficiency. EMI consists of any unwanted signals such as radiated and conducted EMI emissions that can cause degradation in effective performance of equipments. As shown in Fig. 3, a simple polarized snubber circuit is used for reducing the power losses and conducted EMI. In order to prevent the radiated EMI problems on the surrounding circuits of the power supply, all electronic and electric circuits are packaged by means of a conductive case that has been earthed through an appropriate earthing system. III. E XPERIMENTAL R ESULTS AND D ISCUSSION A very compact and portable HVPPS was designed and built to charge a 84-nF capacitor bank from 4 to 7 kV being available in the discrete 1-kV steps in which the repetition rate of discharges is up to 5 Hz. Fig. 4 shows the prototype control section of the fly-back converter assembled in order to control the operation of the HVPPS. The input/output terminals of this module are associated to the HV transformer, the trigger circuit of the spark gap switch, and the sampling circuit. The transformer and the sampling circuit terminals of the control

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Fig. 4.


Prototype control section of the fly-back converter.

section are connected to the HV generating section, which has been comprised of the HV fly-back transformer and the capacitor bank. The 84-nF energy bank consists of 12 ceramic HV capacitors assembled in parallel (each 7 nF, 15 kV), which will be connected to the spark gap switch in a completely coaxial configuration to provide a minimum inductance connection. By connecting the trigger circuit terminal of the module to the designed trigger circuit of the spark gap switch, the set of the HVPPS is accomplished. In order to appoint the communication between the user and the HVPPS, a graphical interface, written in C# language, has been provided so that the user can control the charging and discharging processes by means of a laptop via a serial port communication. The communication between the power supply and the laptop has been provided by a 2-m coaxial cable. The user can set the charging voltage level, the shot frequency, and the number of total shots. Since the capacitor bank should be precisely charged up to the desired voltage level, we considered an option in the graphical interface to provide the situation for the user to tune the duty cycle of the PWM signal. In this case, during the repetitive operating mode, the user can achieve an appropriate rise time at charging duration that helps the capacitor bank to be charged completely. In the prototype design of the HVPPS, the discharge process is performed by means of an indigenously designed spark gap switch, so that it starts conduction by applying a −15-kV short-duration pulse to it. The distance between the electrodes of the spark gap and also the shape of electrode’s head has been designed such that after the trigger pulse quenches, the spark gap has had enough time to turn- OFF before the next trigger pulse appears. After the HVPPS is built, its performance should be tested to verify the design parameters and functional integrity. In order to evaluate the device performance, the experimental runs of the HVPPS are performed over a very small PFD whose design has previously been described in detail [30]. The geometrical parameters of the very small PFD include a 1.263-mm anode radius, an effective anode length of 4.53 mm, a cylindrical cathode with inner radius of 7.17 mm, and a 13-mm-long

Pyrex glass insulator sleeve. A very small PFD is connected to the 84-nF capacitor bank through the shortest path to minimize the total inductance of the system. To analyze the discharge pulses, we used a HV probe and a CWT-Rogowski current transducer manufactured by the Power Electronic Measurements Ltd. to show the charging voltage and the discharge current, respectively. At first, the repetitive discharge mode of the device was chosen, so that the duration of the repetitive operation was 20 s, leading to the occurrence of 100 shots. Fig. 5 shows the results of the diagnostics at a repetitive discharge mode of 5-Hz shot frequency with the charging voltage of 7 kV and 4-mbar argon gas pressure. As it is observable, the charging and discharging processes of the capacitor bank were successfully occurred, indicating the accurate performance of the SMPS and the spark gap switch for driving a very small PFD. It can also be seen that the rise time of 10%–90% of the charging voltage, at each single-shot trace is 110 ms as expected from the design. This consequence demonstrates that the control and sampling circuits are being implemented as well. As it is known, the most important electrical parameter of a PFD is the total inductance of the system (i.e., inductance of capacitor bank, spark gap switch, and electrodes of the PFD), because it has a remarkable effect on the magnitude of discharge current and consequently on the pinching occurrence [17]. In order to make a PFD efficient, the total system inductance should be maintained as low as possible. Using a compact and coaxial layout in connection among the capacitor bank, spark gap switch, and electrodes of the PFD can assist to minimize the total system inductance. In our case, we designed a symmetrical configuration for the capacitor bank using 12 ceramic capacitors, and a short coaxial spark gap. Then, these components along with the plasma chamber were integrated without using any cables. Under the same condition of the repetitive discharge mode, i.e., with 7-kV charging voltage and 4-mbar argon gas pressure, the single discharge mode of the HVPPS was indicated to compute the total system inductance. Typical discharge pulses of the system at single discharge mode are illustrated in Fig. 6. As it is shown in Fig. 6, the pinching evidence can be genuinely observed in the capacitor bank voltage trace; however, this event cannot be seen in the discharge current trace. This issue is because of the low bandwidth of the Rogowski coil (its bandwidth is up to 16 MHz), leading to the rejection of the pinch frequency from the main discharge current trace. As an explanation, it should be mentioned that regarding the radial speed of the plasma sheath that is of the order of 15–25 cm/μm and the anode radius of the very small PFD, the radial phase duration can be calculated to be from 5.05 to 8.42 ns, corresponding the pinch frequency to be of the order of 118–198 MHz [30]. Under this situation, the used Rogowski has a lack of ability to detect the pinching evidence. It is observed in Fig. 6 that the capacitor bank is charged to its preset value and is maintained stable within a negligible tolerance at the refresh mode. After discharging, the discharge current was measured to be 5.7 kA. It should be noted that, the insulator sleeve dimensions, anode radius, and the plasma sheath thickness in very low energy devices are considerably


Fig. 5.

Results of the diagnostics at repetitive discharge mode with 5 Hz shot frequency.

Fig. 6.

Discharge pulses of the capacitor bank at single discharge mode.

lower than those in larger energy devices [18] that cause an increase in the plasma resistance in very low energy PFDs. This high plasma resistance would have significant influence on the magnitude of the discharge current. Nevertheless, the measured discharge current results in a low system impedance that is acceptable for a very small PFD. It can also be deduced from the discharge current trace that the quarter period of the discharge current is 100 ns. Hence, regarding the 84-nF capacitance of the capacitor bank, the total inductance

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of the system was computed to be 48 nH. For the sake of comparison with small PFDs, the main electrical and geometrical characteristics of several small PFDs with energy in the range of a few tens of joules to a few hundreds of joules have been listed in Table III. As it is observed, some of these small PFDs, in spite of obtaining high quarter periods, could own the low inductances, which are due to their higher capacitances than that used in our test. However, the measured inductance is low enough to be compatible with successful

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TABLE III M AIN E LECTRICAL AND G EOMETRICAL C HARACTERISTICS OF S EVERAL S MALL PFDs

performance of the very low energy PFD, which leads to obtaining fast and high magnitude discharge pulses to assist the pinching evidence. IV. C ONCLUSION A very simpler, portable, and highly efficient HVPPS was successfully designed, built, and tested. The HVPPS was employed to charge a 84-nF capacitor bank from 4 to 7 kV operating at a repetitive discharge mode of 5 Hz. The communication between the user and the HVPPS was provided through a graphical interface, written in C# language, so that the user could control the charging process by means of a laptop via a serial port communication. The spark gap configuration was indigenously designed such that after the trigger pulse quenches, the spark gap has had enough time to turn-OFF before the next trigger pulse appears. At the repetitive discharge mode, the results of diagnostics successfully validated the accurate performance of the SMPS and the spark gap switch for driving the very small PFD, at a repetitive operating mode of 5 Hz with a maximum charging voltage of 7 kV and 4-mbar argon gas pressure. As it was expected, the rise time of 10%–90% of the charging voltage, at each single-shot trace was obtained to be 110 ms. This consequence demonstrated that the control and sampling circuits were being implemented as well. Subsequently, in order to calculate the total system inductance, the single discharge mode of the HVPPS was tested. In this test, the pinching evidence was genuinely observed in the capacitor bank voltage trace. In addition, the quarter period of the discharge current was observed to be 100 ns. As a result, the total inductance of the system was computed to be about 48 nH. The measured inductance was low enough to be compatible with successful performance of the very low energy PFD, which leads to obtaining fast and high magnitude discharge pulses to assist the pinching evidence. This HVPPS could emerge as one of the very low cost, compact, light weight, and highly efficient power supplies used for driving very small PFDs so far. R EFERENCES [1] R. K. Rout, P. Mishra, A. M. Rawool, L. V. Kulkarni, and C. G. Satish, “Battery powered tabletop pulsed neutron source based on a sealed miniature plasma focus device,” J. Phys. D, Appl. Phys., vol. 41, no. 20, p. 205211, 2008.

[2] P. Silva, L. Soto, G. Sylvester, M. Zambra, H. Bruzzone, and A. Clausse, “Design and construction of a very small plasma focus in the limit of low energy,” in Proc. AIP Conf., 2001, pp. 235–239. [3] L. Soto and L. Altamirano, “A pulse voltage multiplier,” Rev. Sci. Instrum., vol. 70, no. 3, pp. 1891–1892, 1999. [4] S. Zabihi Sheykhrajeh, “Flexible high voltage pulsed power supply for plasma applications,” Ph.D. dissertation, Faculty Built Environ. Eng., Queensland Univ. Technol., Brisbane, QLD, Australia, 2011. [5] R. Verma, “Construction and optimization of low energy (