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409. HTS Multilayer Technology for Optimal Bit-Error. Rate RSFQ Cells. D. Cassel, Th. Ortlepp, K. S. Ilin, G. Pickartz, B. Kuhlmann, R. Dittmann, H. Toepfer, A. M. ...
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 13, NO. 2, JUNE 2003

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HTS Multilayer Technology for Optimal Bit-Error Rate RSFQ Cells D. Cassel, Th. Ortlepp, K. S. Ilin, G. Pickartz, B. Kuhlmann, R. Dittmann, H. Toepfer, A. M. Klushin, M. Siegel, and F. H. Uhlmann

Abstract—The operation of Rapid-Single-Flux-Quantum logic (RSFQ) circuits is strongly influenced by thermal noise. Especially for higher temperatures the bit-error rate (BER) is a critical issue. A new design concept focused on improved noise immunity has been developed to reach an optimal BER for high-temperature superconductor (HTS) RSFQ cells. For example, we expect for a T-Flip-Flop (TFF) of our cell library a theoretical improvement of the BER of six orders of magnitude at a temperature of 50 K. To verify the new design approach, we have designed basic RSFQ cells using parameter values derived from our multilayer technology. The process with two superconducting YBCO layers is based on substrates with two bicrystal lines. The article is focused on the multilayer technology to realize the optimal design parameters. One of the most crucial issues is patterning of small structures on a micron scale, especially the small vias. This new patterning process is described in detail. Index Terms—Circuit optimization, digital circuits, high-temperature superconductors, Josephson junctions.

I. INTRODUCTION

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OR high-speed integrated circuits, energy consumption is an important issue. The switching of rapid-single-flux quantum (RSFQ) logic has a very low power consumption and allows operating frequencies above 100 GHz [1]. This makes RSFQ logic a serious solution for high-speed electronics. In this circuit technique the digital information is represented by a single magnetic flux quantum. RSFQ logic with high-temperature superconductor (HTS) is most promising because of the high characteristic voltage. A big advantage of HTS is the operation at temperatures of about 20 K or more. This reduces the cooling costs of the electronic system. The desired higher operating temperatures of HTS digital circuits lead to a higher noise level, and increase the probability of switching errors. Therefore, the main challenge is the optimization of the bit-error rate (BER). We used our new analytical method to determine switching errors. The detection of switching errors was based on circuit simulations and measurement results [2]–[4]. Usually circuits are designed to maximize fabrication

Fig. 1. Schematic of a TFF-circuit composed of basic cells designed for optimal BER. The circuit includes dc/SFQ converter, JTL, TFF, JTL and output.

yield [5]. With our new approach [6], [7] cells are designed with respect to optimal bit-error rate. II. BASIC CELLS DESIGNED FOR HIGH NOISE IMMUNITY Our library of basic RSFQ cells with high noise immunity includes Josephson transmission lines (JTL), asynchronous and synchronous dc/SFQ-converters, T-Flip-Flops (TFF) and SFQ/dc-converters. Fig. 1 shows the schematic of a TFF embedded in a HTS circuit with a dc/SFQ converter and a SFQ/dc converter connected with JTL’s. The circuit is designed taking into consideration an operating temperature of 50 K at a clock frequency of 50 GHz. The basic function of this circuit is that a steady voltage at the entrance of the DC/SFQ converter creates a permanent flow of magnetic flux quanta. The frequency of flux quanta per time is devided by a factor of two after crossing the TFF part. The measured voltage at the output should be half of the voltage measured in front of the TFF. Fig. 2 shows the dependence of BER of TFF on the critical . The BER of the TFF has been calculated with parameter the new algorithm with consideration of parasitic inductances. The solid line shows the BER for an optimized design and the single square represents the BER calculated for the centered design method neglecting the noise. The BER determined with the new approach is about six orders of magnitude lower than the BER which is calculated with the centered design method. III. TECHNOLOGY

Manuscript received August 4, 2002. This work was supported by the German DFG Projects Si 704/1-1, Si 704/1-2, and Uh 53/4-2. D. Cassel, K. S. Ilin, G. Pickartz, B. Kuhlmann, R. Dittmann, A. Klushin, and M. Siegel are with the Institut fuer Schichten und Grenzflaechen, Forschungszentrum Juelich, D-52425 Juelich, Germany (e-mail: [email protected]). Th. Ortlepp, H. Toepfer, and F. H. Uhlmann are with the Institut fuer Allgemeine und Theoretische Elektrotechnik, Fakultaet fuer Elektrotechnik und Informationstechnik, Technische Universitaet Ilmenau, D-98684 Ilmenau, Germany (e-mail: [email protected]). Digital Object Identifier 10.1109/TASC.2003.813881

The basic cells are designed for implementation in two basic technologies. The first technology is based on a two layer YBa CuO (YBCO) technology on a bicrystal substrate with two grain boundaries. The other one is a three layer YBCO technology with interface-engineered Josephson junctions -characteristic which (IEJ’s). Our fabricated IEJ’s have an behaves like the RSJ model [8], [9] for negligible capacitance at temperatures over 50 K. At 77 K they have current densities from 10 to 10 A cm and characteristic voltages from 50

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Fig. 2. Comparison of bit error rates at a temperature of 50 K and clock frequency of 50 GHz calculated with the new design approach with consideration of parasitic inductances. In comparison to the centered design method the BER of the optimized design is six orders of magnitude improved.

to 500 V and at 30 K up to 1 mV [10]. In the testing phase we used the bicrystal technology due to problems with trapped magnetic flux in integrated circuits based on ramp-edge junctions. The first step of the bicrystal process, shown in Fig. 3., is pulsed-laser deposition (PLD) of an CeO /YBCO/CeO multi-layer on a YSZ-substrate followed by an annealing step. The bottom CeO layer is a buffer layer. The superconductive 180 nm thick YBCO layer serves as a ground plane and the 50 nm thick insulator CeO is a protection layer. In the next step the base electrode is patterned. After photolithography the AZ 5214 resist is post-baked at 150 C for five minutes to create a shallow ramp. The base electrode is prepared by ion-beam etching (IBE) at an angle of 30 from normal angle of incidence. The resulting ramp angle is less than 45 . This is important to prevent the formation of grain boundaries in the upper YBCO film during later depositions. A 150 nm thick CeO layer which separates the ground plane from the upper YBCO wiring is then deposited by PLD. An oxygen annealing step follows. The method of preparing the via to the ground plane is a crucial step. Small rectangular vias with an area of (2 4) m were etched with IBE using a mask of post-baked photoresist. This leads to re-deposition effects caused by ion milling. The re-deposition is due to the fact that etched material from one side of the ramp was deposited on the opposite side of the mask. Such fabricated vias had current densities three orders in magnitude smaller than expected. To prevent re-deposition now we use a thin platinum layer as an etch mask. The mask is patterned by standard negative photolithography with AZ 5214 resist. Platinum is then deposited by evaporation while the chip is rotated during the process. After lift-off the remaining Pt-mask serves as an etch mask for the via. Using this mask the via is etched into the CeO layer. The thickness of the mask is chosen so thin that it is used up when reaching the YBCO layer. The etching continues partly into the CeO layer. We stop the etching until 2/3 of the YBCO layer was etched. Thus, we get rid of the mask which saves a cleaning step. The prepared ramp is very shallow with an angle less than 15 . The open YBCO surface is treated for one second

Fig. 3. Multilayer technology on a bicrystal substrate. The ground plane enables low inductance values. Additionally it provides implementation of sufficient complexity for the fabrication.

in diluted (0.03%) Br-ethanol to remove the IBE-damaged surface of YBCO [11]. The sample is again annealed in oxygen directly before deposition of the YBCO wiring with PLD. After the deposition of YBCO, a 100 nm thick gold layer for bond pads and resistor-contacts is sputtered in-situ. Using photolithography with a thinner resist (AZ 5206) and IBE, the wiring is patterned into small microbridges. Finally, for the resistors a 400 nm thick PdAu layer is patterned, by lift-off. Fig. 4 displays a microscopic image of a fabricated circuit which corresponds to the schematic shown in Fig. 1. IV. CRUCIAL TECHNOLOGICAL ISSUES The basic components of our multilayer technology can be tested on specially designed test areas of the chip. This includes inductance, isolation, critical current density of Josephson Junctions (JJ’s), critical current density of cross-overs and vias, the contact and total resistance. The inductance, shown in Fig. 5., is determined by feeding a control current into a dc-SQUID and measuring the modulation period. The solid line shows the

CASSEL et al.: HTS MULTILAYER TECHNOLOGY FOR OPTIMAL BER RSFQ CELLS

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Fig. 6. Current-voltage characteristic of a 1.5 m wide bicrystal junction at 50 K. It fits the RSJ model for neglicible capacitance. Fig. 4. Microscopic image of fabricated circuit. The black solid lines indicate the positions of the bicrystal lines.

Fig. 5. Temperature dependence of the inductance per square of a 2 m wide microstrip line over a ground plane. Solid line shows a fit based on the Chang formula.

calculation of the inductance per square based on the Chang K and an formula [12] with the fitting parameters nm. The YBCO London penetration depth of other two parameters used in the fit had been meassured before. These are the insulator thickness of CeO which is about 60 nm and the thickness of the superconducting YBCO layer which is about 200 nm. The geometric factor caused by border field effects, is neglected [13]. Because of the ground plane the required small inductances can be realized. The next important issue is the adjustment of the critical current density of the bicrystal junctions to about 50 kA cm at a temperature of 50 K. This can be done by annealing the chip in an argon or oxygen plasma. The bicrystal substrates have a symmetric misorientation angle of 24 . The current voltage characteristic of a 1.5 m -characterwide bicrystal junction is shown in Fig. 6. The istic measured at 50 K behaves like the RSJ model for negligible capacitance. Fig. 7 displays the measured critical current density versus temperature of a junction with a width of 2 m. The required current density of about 50 kA cm could be adjusted. As mentioned before, the fabrication of small vias is an important technological task. We established a process to fabri-

Fig. 7. Temperature dependence of critical current density J of a bicrystal junction with a width of 2 m. The value of about 50 kA=cm at a temperature of 50 Kelvin fits the planned design values.

Fig. 8. SEM image of photoresist for the preparation of the via mask (a). SEM image after lift off (b). The Platinum mask has been deposited by evaporation, while the sample was rotating.

cate (2 4) m vias with a very shallow ramp to get high critical currents. Fig. 8 shows scanning electron microscope (SEM) images of the photoresist (PR) before evaporation of the Platinum mask (a) and the thin platinum mask after lift off (b). Fig. 9(a) shows the via hole after the ion-beam treatment. No re-deposited material can be seen on the image. We measured the profile of this ramp with an atomic force microscope (AFM) (b). The CeO /YBCO ramp is very shallow with an angle less than 15 . Such a shallow ramp is optimal to prevent the formamA tion of grain boundaries. The fabricated vias have an at 50 K, which is more than a factor of ten higher than required

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REFERENCES

Fig. 9. SEM image after the etching of the via hole (a). With AFM the profile of the etched ramp has been meassured. The angle of the ramp is less than 15 (b).

for chip design. The properties of the other fundamental compoof cross-overs, the contact and total renents like isolation, sistance of the resistor are close to the values presented in [14]. The latest measured values of these components are: The isois higher than 100 G m . The 10 m wide lation mA. Accordingly cross-overs have critical currents of the cross-overs is higher than the critical current density 800 kA cm . The contact resistance between PdAu and upper cm . This is small enough to get YBCO is about total resistances of 1 .

V. CONCLUSION The implementation of all basic components in the new library of basic cells designed for HTS RSFQ circuits with optimal BER in a multilayer technology, has been tested successfully. This technology allows the fabrication of HTS RSFQ circuits with sufficient complexity in order to investigate the BER experimentally.

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