Journal of the Korean Physical Society, Vol. 50, No. 4, April 2007, pp. L933∼L936
Letters
Hydrogenated Amorphous Silicon Gate Driver Made of Thin-Film Transistors Ja Hun Koo, Jae Won Choi, Young Seoung Kim, Moon Hyo Kang, Se Hwan Kim, Eung Bum Kim, Heiju Uchiike, Seung-Woo Lee and Jin Jang∗ Department of Information Display and Advanced Display Research Center, Kyung Hee University, Seoul 130-701 (Received 4 January 2007) We developed a hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) gate driver having a long operation. The gate driver, composed of 9 a-Si:H TFTs including two pull-down transistors and one capacitor, was demonstrated in the present work. The pull-down transistors, under an AC bias during operation, prevent the floating of the gate line. The bias-stress effect of the fabricated a-Si:H TFTs was studied with various bias conditions to study the lifetime. The simulation results based on the experimental results indicate that the lifetime of the proposed a-Si:H gate driver can be over 5 years. PACS numbers: 84.30.Sk Keywords: Shift register, Stability, a-Si:H, Gate driver
results show that the proposed circuit has a lifetime of 5 years.
I. INTRODUCTION Hydrogenated amorphous silicon (a-Si:H) and polycrystalline silicon thin-film transistors (TFTs) are widely used for active matrix liquid-crystal displays. Recently, Integrating driver circuits on the TFT backplane has been of increasing interest because of its many advantages, such as overall cost reduction, compactness, and mechanical reliability [1–6]. The integrated circuits using a-Si:H TFTs have several advantages: mature manufacturing technology, large-area arrays up to 100 inches, low temperature, and low-cost processing, and elimination of the driver ICs. However, there are two important issues in designing integrated circuits using a-Si:H TFTs. One is the low mobility and high threshold voltage. The other, the instability of an a-Si:H TFT, is a more critical issue. The threshold voltage of an a-Si:H TFT increases with increasing operation time and gate voltage [7, 8]. The instability of an a-Si:H TFT is due to charge trapping and defect creation [9–16]. Charge trapping near the interface, which is dominant at higher electric fields and shows a logarithmic time dependence, is due to trap sites in the SiNx /a-Si:H interface. Defect creation, which is dominant at lower electric field and exhibits a powerlaw time dependence, is due to the breaking of the weak Si-Si bonds in a-Si:H. In this work, we demonstrated a new gate driver made of a-Si:H TFTs on glass. The threshold voltage shift (∆Vth ) was measured for various duty ratios and frequencies of the gate bias pulse. A simulation of the lifetime was carried out based on the gate voltage shift of our TFT under AC or DC bias stress. The simulation ∗ Corresponding
Author:
[email protected]
II. THRESHOLD VOLTAGE SHIFT UNDER A GATE-BIAS STRESS An a-Si:H TFT with an inverted staggered structure was fabricated for the present work. The processing of the a-Si:H TFT was as follows: Cr was deposited on Corning 1737 glass by DC sputtering and was then patterned for the gates. Layers of SiNx (400 nm), a-Si:H (150 nm), and n+ a-Si:H (50 nm) were consecutively deposited on the gates by using plasma-enhanced chemical vapor deposition (PECVD) without breaking the vacuum. The SiNx layer was deposited by using a SiH4 , NH3 and N2 mixture; then, undoped a-Si:H was deposited from a gas mixture of 20 % SiH4 diluted in H2 at 260 ◦ C. The n+ a-Si:H was deposited from a gas mixture of a 1.5 % PH3 in SiH4 . Cr was deposited on the n+ aSi:H and was then patterned for source/drain electrodes. Then, the n+ layer between the source/drain electrodes was etched away to make a back-channel etched TFT. Finally, a passivation layer was deposited and patterned for contact holes. The channel width and length of the TFT were 20 µm and 5 µm, respectively. The TFTs were annealed at 230 ◦ C for 2 hours before bias-stress measurements to restore their initial performances. Figure 1(a) shows the AC signal used for the biasstress test of the a-Si:H TFT. The Vp, defined as the peak voltage, was 25 V while the Vb, defined as the base voltage, was 0 V. The frequency for the pulse was 1/tc , where tc is the pulse period, and the duty ratio is tvp /(tvp +tvb ), where tvp is the time of the peak voltage,
-L933-
-L934-
Journal of the Korean Physical Society, Vol. 50, No. 4, April 2007
Fig. 2. Schematic diagram of the proposed a-Si:H gate drivers with AC bias: (a) the gate driver with two pull-down transistors and (b) the timing diagram of the gate drivers. Fig. 1. Measurement method and results for the instability of a-Si:H TFT at 60 ◦ C: (a) the definition of the AC signal, and (b) the threshold voltage shift for different duty ratios of 50 %, 70 % and 100 %.
tvb is the time of base voltage, and tvp +tvb is equal to tc . The bias-stress effect was measured up to 10,000 s. The measurement temperature was fixed at 60 ◦ C to accelerate the threshold voltage shift. The threshold voltage was obtained from the intercept of the transfer curves on a linear scale. An HP 41501B pulse generator and an HP 4156 precise semiconductor parameter analyzer were used to carry out the bias-stress experiment. We measured the transfer characteristics after a certain period of bias stress. During the bias-stress, the source and the drain electrodes were commonly grounded to avoid electric-field distortion. Figure 1(b) shows the threshold voltage shift as a function of effective stress time, the integrated time applying the peak voltage, at various duty ratios. The ∆Vth as a function of the bias stress time (t), the temperature (T), and the stress voltage (Vst ), is given by −Ea , (1) ∆Vth = A|Vst |β tγ exp kT
where, Ea is the activation energy and A, β, and γ are constants (β = 0.91, γ = 0.3 at DC bias, 300 K). As one can see in Figure 1(b), the ∆Vth increases with increasing effective stress time, but depends on the duty ratio. The shift decreases with decreasing duty ratio due to a detrapping of carriers during the off-state. We conclude, therefore, that trapped charges can detrap during the off-period of the applied signal. The γ measured at 60 ◦ C decreases from 0.5 to 0.46 with decreasing duty ratio from DC to 50 %. Note that the γ increases with increasing temperature [17]. Consequently, the Vth shift is the highest under a DC condition, as shown in Figure 1; therefore, it can be reduced by using an AC bias in a-Si:H integrated circuits.
III. AMORPHOUS SILICON GATE DRIVER Figure 2 shows a schematic diagram of the proposed circuit and its timing diagram. It is made of 9 TFTs and one capacitor. The pull-down transistors (T7, T9) are under AC driving, resulting in much less threshold
Hydrogenated Amorphous Silicon Gate Driver Made of· · · – Ja Hun Koo et al.
-L935-
Fig. 3. Simulation results for the proposed gate driver as a function of the operation time.
voltage shift compared to those under DC driving. The pull-down transistors (T7, T9) are turned on alternately to discharge P and the output node potentials. The operation of the proposed gate driver circuit is as follows. When the input signal is high, the P node is charged by the input signal; then, as CLK2 is changed from low to high, the P node voltage is boosted up due to the gatedrain capacitive coupling of T8. Therefore, the output driving ability is achieved by using the bootstrapping voltage of the P node. At this time, the high voltage of the P node is applied to the gates of T4 & T5 simultaneously. Therefore, T7 is turned off, and the high voltage is kept at the P node. After generating an output voltage, the P node voltage is discharged when the reset signal (n + 1) is applied to the gate of T2; then, T4 & T5 are turned off. After that, the P node is alternately discharged through T7 by using the CLK2 signal. When CLK2 is high, the P node is discharged at a low voltage. When CLK2 is changed from high to low, the P node is floated; then, the P node potential has a negative fluctuation caused by capacitive coupling of T8. When CLK1 is changed from high to low, the output has the same negative fluctuation as that caused by capacitive coupling of T9. There is no positive fluctuation, which is the critical issue in conventional circuits. Figure 3 shows simulation results for the output voltage of the proposed circuits as a function of the operation time. The negative fluctuation (Circle A, in Figure 3) does not influence gate driver operation. The lifetime of the proposed circuit is at least 5 years. At early operation times, the P node is kept at the base voltage by using the T7 pull-down transistor to prevent the P node from floating. If the P node is floated or without the T7 pull-down transistor, the p node voltage has a positive fluctuation caused by the capacitive coupling of T8 when CLK2 is changed from low to high. The positive
Fig. 4. Fabricated gate driver and its measurement results: (a) the optical image of the fabricated gate driver and (b) the 1st and the 4th output waveforms of the fabricated gate driver.
fluctuation can lead to an abnormal output. After a 2year operation time, the T7 pull-down transistor cannot work because of threshold voltage shift; then, T2 plays the role of pull-down transistor. The positive charge of the P node is discharged through T2, and the P node is floated. At that time, the Vth of the driving transistor (T8) is already shifted; therefore, the output voltage is not influenced by the positive fluctuation of the P node. Figure 4(a) shows an optical image of the gate driver fabricated in this work. The gate driver has 6 stages. Figure 4(b) shows the 1st and 4th output waveforms of the gate driver at room temperature. As Figure 4(b) shows, there is no difference between the 1st and the 4th outputs. The Vth shift depends on the duty ratio due to the
-L936-
Journal of the Korean Physical Society, Vol. 50, No. 4, April 2007
accumulation of stress time. The pull-down TFTs in the proposed gate driver are under AC driving. Most of the a-Si:H gate drivers have two reset transistors under AC driving, one at the output node and the other at the P node [18,19]. However, in our circuit only one reset transistor is used for charging and discharging at the output and the P node, respectively. The pull-down TFTs turn on alternately to keep a gate line and the P node at low voltage. As a result, the area of the integrated circuits and the number of TFTs are reduced without degrading the stability. The a-Si:H gate drivers under AC driving were developed by Samsung and LGPhilips-LCD [18, 19], but our driver uses 9 TFTs for one stage, which is less than theirs. Note that the numbers of TFTs in the gate drivers developed by Samsung and LGPhilis-LCD are 14 to 15. Therefore, the area for the gate drivers can be reduced by adopting our gate drivers.
IV. CONCLUSION In this work, we proposed a new a-Si:H gate driver with long lifetime based on the bias-stress experiments of the TFTs fabricated in our lab. The Vth shift depends on the duty ratio due to the accumulation of stress time. The pull-down TFTs in the proposed gate driver are under AC driving. The simulation results showed that the lifetime of the proposed a-Si:H gate driver was remarkably improved. And we demonstrated a gate driver made of 9 TFTs and one cap. We found that the gate driver had a lifetime of longer than 5 years and had fewer TFTs. We therefore concluded that the proposed a-Si:H TFT gate driver could be used for the gate drivers of slim LCDs.
ACKNOWLEDGMENTS This research was supported by a grant (F000 40822006-22) from the Information Display R & D Center,
one of the 21st Century Frontier R & D Program funded by the Ministry of Commerce, Industry and Energy of the Korean government.
REFERENCES [1] C. C. Wei, W. C. Lin, S. H. Lo, C. J. Chang and Y. E. Wu, Int. Display Workshops. 2, 1023 (2005). [2] M. Chun, Y. H. Jang, S. Y. Yoon, B. Kim, H. N. Cho, C. D. Kim and I. J. Chung, Int. Display Workshops 2, 1077 (2005). [3] V. M. Da Costa and R. A. Martin, IEEE. Solid State Circuit 29, 596 (1994). [4] B. Kim, Y. H. Jang, S. Y. Yoon, M. D. Chun, H. N. Cho and I. J. Chung, Int. Display Workshops 2, 1073 (2005). [5] J. W. Choi, J. H. Oh, S. H. Kim, J. H. Hur, B. S. Bae and J. Jang, J. Korean Phys. Soc. 48, S98 (2006). [6] B. S. Bae, J. W. Choi, J. H. Oh and J. Jang, IEEE Trans. Electron Dev. 52, 494 (2006). [7] J. H. Yoon, J. Korean Phys. Soc. 25, 115 (1992). [8] J. W. Choi, J. H. Oh, S. H. Kim, J. H. Hur, B. S. Bae and J. Jang, J. Korean Phys. Soc. 48, S98 (2006). [9] C. Y. Huang, T. H. Teng, J. W. Tsai and H. C. Cheng, Jpn. J. Appl. Phys. 39, 3867 (2000). [10] M. J. Powell, C. van Berkel and J. R. Hughes, Appl. Phys. Lett. 54, 1323 (1989). [11] F. R. Libsch and J. Kanicki, Appl. Phys. Lett. 62, 1286 (1993). [12] K. S. Karim, A. Nathan, M. Hack and W. I. Milne, IEEE Electron Device Lett. 25, 188 (2004). [13] H. Gleskova and S. Wagner, IEEE Trans. Electron Dev. 48, 1667 (2001). [14] S. K. Kim, K. S. Lee and J. Jang, J. Korean Phys. Soc. 28, S116 (1995). [15] I. K. Han, J. I. Lee, M. B. Lee, S. K. Chang and E. K. Kim, J. Korean Phys. Soc. 45, S949 (2004). [16] J. S. Park, S. J. Lee, Y. K. Jhee and H. S. Shin, J. Korean Phys. Soc. 47, S392 (2005). [17] M. J. Powell, C. van Berkel and A. R. Franklin, American Phys. Soc. 45, 4160 (1992). [18] S. H. Moon, Korea Patent. No.10-2004-0007814, 2004. [19] B. Kim and S. Y. Yoon, Korea Patent. No. 10-20040039136, 2004.
