RCe = R C buck. = Rc/D' boost and buck/boost. = +. - RC. Req. R e. RCe. = iIL_f-6. 0 e ...... Let g = R2/(Rl + R2) be the divider ratio of the dc loop, the voltage gvo.
N81-10301
IlllllllllllllUtlllllrrlllll NASA CR-165172 TRW20922-6001-RU-01
APPLICATION HANDBOOK FOR A STANDARDIZED CONTROL MODULE (SCM) FOR DC TO DC CONVERTERS VOLUME I FINAL REPORT BY .,... t
DR. FRED C. LEEAND M. F.MAHMOUD VIRGINIA POLYTECHNIC INSTITUTE AND STATEUNIVERSITY
DR. YUAN YU TRW DEFENSEAND SPACE SYSTEMSGROUP
•.:_,"-. ,._
Preparedfor: NATIONAL AERONAUTICS AND SPACE ADMINISTRATION LEWIS RESEARCH CENTER 21000BrookparkRoad Cleveland, Ohio 44135 CONTRACT NAS-3-20102
1. Report No. NASA CR-
3. Recipien"s Catalog No.
J 2. Government Accession No.
I
165172
4, Title end Subtitle Application for DC-DC
5. Report Data
Handbook Converters,
for a Standardized Volume I, Final
Control Report.
Module
April 1980
(SCM)
6. Performing Organization Code TRW
7. Author(s} Dr.
29922-6001-RU-01
8. Performing Organization Report No.
Fred
Lee,
Mr.
M.
F. Mahmoud
and
Dr.
Yuan
Yu 10. Work Unit No.
9. PerformingOrganization Name and Addrm TRW Defense and Space Systems Group Power Conversion Electronics Department One Space Park Redondo Beach, California 90278
11. Contract or Grant No. NAS 3-20102 13. Ty_
NASA
Lewis
Research
21000 Brookpark Cleveland, Ohio 15. Sup_ementary NASA
of Report and PeriodCov_ed
Final TECH.
12. Sponsoring Agency Name and Address
Jun¢
Center
1976-Jan.
1990
14, Sponsoring Agency Code
Road 44135
Notes
Technical
Monitor:
Joseph
Kolecki
16. Abstra_ The Standardized Buck/Boost DC-DC
Control Module (SCM) has Converters. The SCM uses
and output load regulation, adaptive compenstion of the constraints. This
project,
stable feedback control system, good dynamic transient control loop for changes in open loop gain and output
"Application
Handbook
developes the necessary modeling the SCM to DC-DC Converters. A discussion techniques. The The
Power
is presented Average Time
Stage
been developed for application in the Buck, multiple feedback loops to provide improved
Transfer
and
for a Standardized
analysis
tools
Control
to aid
the
Module
design
(SCM)
engineer
Boost input
and line
response and filter time for
in the
DC-DC
Converters"
application
of
on the SCM Functional Block Diaqram and the different analysis Domain Analysis technique is chosen as the basic analytical tool. Functions
are
developed
for
the
Buck,
Boost
and
Buck/Boost
Converters.
The Analog Signal and Digital Signal Processor Transfer Functions are developed for the three DC-DC Converter types using the constant on-time, constant off-time and constant frequency control laws. A discussion is presented on the adaptive control concept of the SCM. An
analysis
is • • • • •
presented
on the
The Design Handbook (VolumeII) Report (Volume I), and establishes specifications
using
the
Standardized
17, Key WordslSuggmtedbv Author(s)) DC-DC Converters Standardized Control Module Analog Signal Processor Diqital Signal Processor Stability Analysis Discrete Time Domain Analysis 19. Security _auif.
(of this report)
Unclassified
following
DC-DC
Converter
characteristics:
Stability. Audio-Susceptibility. Output Impedance and Load Transient. Input Filter Interaction. Discontinuous Curre.t Operation. is based on the design guidelines Control
Module
technical results presented in the Final Technical and procedures to meet regulator performance (SCM).
18. Distribution Statement Performance
Analysis Unclassified
20. Security Clauif, (of this pagel
- Unlimited
21. No. of Pages 240
' Forsale bytheNationalTechnicalInfatuationService.Springfield,Virginia22151
NASA-C-168
(Ray.
6-71)
22. Price"
NASA
CR-165172
TRW 29922-6001-RU-01
APPLICATION
A STANDARDIZED
HANDBOOK
FOR CONTROL MODULE (SCM) FOR
DC TO DC CONVERTERS VOLUME I FINAL REPORT
BY
DR. FRED C. LEE AND M.F. MAHMOUD VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY
DR. YUAN YU TRW DEFENSEAND SPACE SYSTEMS GROUP
Prepared for: NATIONAL AERONAUTICS
AND SPACE ADMINISTRATION
LEWIS RESEARCH CENTER 21000BrookparkRoad Cleveland,Ohio 44135 CONTRACT NAS-3-20102
FORWARD
The modeling
and analysis
Dr. Fred Lee at TRW Defense
tasks were
and Space
performed
Systems
by
Group
and
later at Virginia
Polytechnic
Institute
under subcontract
GB2313CHBM,
by Dr. Yuan Yu at TRW Defense
and Space Systems
Group,
Polytechnic Degree
Institute
in Electrical
helped
review,
to improve
working
toward
at Virginia
his Master
Engineering.
this work by the NASA thorough
and by M. F. Mahmoud
while
The authors wish
whose
and State University
to acknowledge Project
the contribution
Monitor,
numerous
Mr. Joseph
to
Kolecki,
con_nents and suggestions
the report.
_i__p
TABLE OF CONTENTS PAGE NO. INTRODUCTION ........................
Io
2.
STANDARD
3.
SELECTION
CONTROL
5.
BLOCKS ........
............
3.2
DIGITAL
SIGNAL
NONLINEARITY ......
3.3
VARIOUS
NONLINEAR
3.4
SELECTION
MATRIX
PROCESSOR
ANALYSIS
OF THE AVERAGE
FUNCTIONS
FORMULATION
DOMAIN ANALYSIS
.
12 12
FOR THE SCM.
]6
REGULATED
CONVERTERS
......
17
AND BLOCK
DIAGRAMS.
......
20
FOR POWER STAGES
DURING ON TIME 20
5.2
STATE-SPACE
24
5.3
LINEARIZATION
5.4
TRANSFER
AVERAGING
AND SYSTEM
FUNCTION
SIGNAL
AND PERTURBATION .......... BEHAVIORS .............
6.1
PROCESSOR
ASP TRANSFER
TRANSFER
FUNCTIONS
FUNCTION
IN TERMS
DERIVATION
6.3
ASP TRANSFER
AND BLOCK
DIGITAL
SIGNAL
OF Vac AS A FUNCTION
PROCESSOR
7.1
DEFINITION
7.2
CONSTANT-FREQUENCY
7.3
DUTY-CYCLE
7.4
EXTENDING
7.5
DESCRIBING
7.6
DSP BLOCK
COMPLETE
STABLE
DIAGRAM
•
•
°
•
°
•
OPERATION
FOR OTHER
•
•
•
DIAGRAM •
°
°
52 54
DIAGRAM..
•
-ii-
54
ANALYSIS. CONTROL
FOR THREE
°
°
63 LAW.
•
•
°
73
POL-ER STAGES.
•
•
•
6? 69
LAWS ........
OF SCM-CONTROLLED •
.
RANGE .......
CONTROL
REPRESENTATIONS
S_,tALL-SIGNAL BLOCK
REGULATORS
44
STAGE ............
FOR CONSTANT-FREQUENCY
DUTY-CYCLE
FUNCTIONS
......
AND BLOCK
DSP DESCRIBING-FUNCTION
INSTABILITY
42
DIAGRAM ..........
FUNCTION
OF PULSE MODULATOR
40
A
OF Vo AND cl
AND BLOCK
TRANSFER
DIAGRAMS .
A ^
FUNCTION
29
OF Vo AND Vac .......
A
6.2
27
DERIVATIONS ...............
^
e
.
TECHNIQUES .........
TIME
DC-DC SWITCHING
lO
AND OFF TIME .......................
ANALOG
b
IO
POWER STAGE NONLINEARITY
POWER STAGE TRANSFER
6
APPROACH ................
3.1
5.1
B.
(SCM) FUNCTIONAL
OF ANALYTICAL
SCM-CONTROLLED
no
MODULE
1
76
SWITCHING •
•
°
•
•
79
TABLE
9.
lO.
ADAPTIVE
OF CONTENTS
CONTROL-BASIC
9.1
ADAPTIVE
9.2
OTHER SMALL
9.3
DISCONTINUOUS
9.4
OPTIMAL
9.5
PARAMETER
CONCEPT
(Cont.)
AND IMPLEMENTATION ........
85
COI_TROL-BASIC CONCEPT .............. SIGNAL
PERFORMANCE
INDUCTOR
CHARACTERISTICS
CURRENT
85 .......
96
OPERATION .........
I02
COMPENSATION .................... ADAPTATION
SCM CONTROLLED
REGULATOR
I05
OF THE THREE-LOOP STABILITY
lO.l
OPEN LOOP TRANSFER
I0.2
SIMPLIFICATION
OF OPEN-LOOP
I0.3
STABILIZATION
OF SCM CONTROL
I0.4
NORMALIZATION
OF OPEN-LOOP
CONTROL
REGULATOR..
ANALYSIS ...........
122
FUNCTION ................ TRANSFER
122
FUNCTIONS .......
125
...............
FREQUENCY
131
RESPONSE .......
135
If.
I0.5 QUALITATIVE ANALYSIS OF THE OPEN-LOOP TRANSFER FUNCTION. I0.6 AII_PTIVE SCM CONTROL. .................. SCM-CONTROLLED REGULATOR AUDIOSUSCEPTIBILITY ANALYSIS ......
12.
OUTPUT
13.
14.
IMPEDANCE
AND LOAD TRANSIENT
12.1
SMALL SIGNAL
12.2
TRANSIENT
r4ODEL INCLUDING
RESPONSE
INPUT FILTER EFFECTS
............... LOAD DISTURBANCE
TO STEP LOAD CHANGE
TO SWITCHING
13.1
INTRODUCTIOR
13.2
r4ODELING OF POWER STAGES
13.3
INPUT FILTER
INTERACTIONS
13.4
INPUT FILTER
DESIGN
WITH AN INPUT
....
DEVELOPMENT
OF ASP TRANSFER
14.3
DUTY CYCLE PULSE MODULATOR
14.4
SMALL SIGNAL
14.5
SUMMARY
OF DISCONTINUOUS
18,1
.................
14.2
FUNCTION MODEL
185
15. CONCLUSIONS .......................... ..........................
17. DISTRIBUTIO_I LIST .......................
-iii-
.
. . 19_I
IN DISCONTINUOUS 19; CONVERTER
WITH 19B
..........
............
CHARACTERISTIC CURRENT
IBO 180
FILTER .......
POWERSTAGE MOnELING OF THE BUCK/BOOST DISCONTINUOUS MMF .....................
16. REFERENCES
176
CONSTRAINTS ............
PERFORMANCE
166
..........
MODELING AND ANALYSIS OF SWITCHING REGULATORS INDUCTOR MMF OPERATION ..................... 14.1
.......
PERFORMANCES.
.............
. 138 148 154 166
...........
REGULATOR
I16
204 • 206
..........
210
MODELS ..........
217 220 ..223 225
LIST
OF ILLUSTRATIONS
PAGE NO.
FIGURE 2.1
SCM CONTROLLED SWITCHING REGULATORS...........
7
2.2
SWITCHING REGULATOR BLOCK DIAGRAM ............
9
3.1
INDUCTOR CURRENT WAVEFORMS ...............
II
3.2
BUCK/BOOST CONVERTER TOPOLOGY..............
13
5.1
CONVERTER TOPOLOGY VARIATIONS ..............
21
5.2
TRANSFER FUNCTION BLOCK DIAGRAM .............
37
5.3
EQUIVALENT CIRCUIT
6.1
ANALOG SIGNAL PROCESSOR SCHEMATIC ............
41
6.2
SMALL SIGNAL MODEL FOR THE ASP .............
53
7.1'
SCHEMATIC OF A BUCK REGULATOR EMPLOYING THE SCM.....
55
7.2
IMPLEMENTATION OF CONSTANT FREQUENCY DUTY CYCLE CONTROL.
56
7.3
WAVEFORMS (CONSTANT FREQUENCY) .............
58
7.4
SEPARATION
7.5
INJECTION
OF DISTURBANCE
7.6
WAVEFORMS
WITH DISTURBANCE
7.7
EXTENDING
CONSTANT
7.8
MEASUREMENT OF PULSE MODULATOR GAIN AND PHASE CONSTANT VOLT SECONDS CONTROL ..............
FOR
MEASUREMENT OF PULSE MODULATOR GAIN AND PHASE CONSTANT FREQUENCY CONTROL ...............
FOR
7.9
8.1
BLOCK DIAGRAM .....
,
OF SMALL AND LARGE AMPLITUDE
......
39
RAMP WAVEFORMS
59
SIGNAL .............
FREQUENCY
61
............... STABLE
62
DUTY CYCLE
.....
70 74
75
SMALL SIGNAL BLOCK DIAGRAM OF SCM CONTROLLED SWITCHING REGULATORS ..................
80
SMALL SIGNAL BLOCK DIAGRAM OF SCM CONTROLLED SWITCHING REGULATORS WITH LOAD DISTURBANCE .......
81
9.1
OPEN LOOP GAIN
.....................
86
9.2(a)
BODE DIAGRAM
(GAIN) ...................
90
9.2(b)
BODE DIAGRAM
(PHASE)
91
9.3
OPEN LOOP GAIN AND PHASE MEASUREMENT
(TEST
SETUP) ....
93
9.4
OPEN LOOP GAIN AND PHASE
MEASUREMENT
(e:l)
.......
94
9.5
OPEN LOOP GAIN AND PHASE
MEASUREMENT
(_=0.355)
9.6
AUDIOSUSCEPTIBILITY
9.7
OUTPUT
8.2
IMPEDANCE
..................
OF SCM CONTROLLED
CHARACTERISTIC
-iv-
.....
BUCK REGULATOR
.............
95 o .
97 99
LIST OF ILLUSTRATIONS
FIGURE
PAGE NO.
9.8
TRANSIENT
RESPONSE
DUE TO STEP LOAD
CHANGE .......
lOl
9.9A
BODE DIAGRAM
(GAIN)
DISCONTINUOUS
CURRENT
......
I03
9.9B
BODE DIAGRAM
(PHASE)
- DISCONTINUOUS
CURRENT ......
104
9.10
OPEN LOOP GAIN AND PHASE
9.11
S - PLANE DIAGRAM
9.12
OPEN LOOP TRANSFER
9.13
OPEN LOOP CHARACTERISTIC
9.14
OPEN LOOP CHARACTERISTIC WITH COMPENSATION DISCONTINUOUS CURRENT .................
MEASUREMENT ..........
106
.................... FUNCTION
I09
..............
WITH COMPENSATION
Ill LOOP
....
ll3
LOOP If4
9.15
AUDIO-SUSCEPTIBILITY
CHARACTERISTIC
..........
I15
9.16
AUDIO-SUSCEPTIBILITY
CHARACTERISTICS
..........
If7
9.17
OUTPUT
IMPEDANCE ....................
118
9.18
OUTPUT
TRANSIENT
119
9.19
S - PLANE DIAGRAM
RESPONSE
...............
...................
I0.I
INJECTION
lO.2(a)
OPEN LOOP GAIN OF BUCK/BOOST
lO.2(b)
OPEN LOOP PHASE OF BUCK/BOOST
I0.3
S - PHASE DIAGRAM
I0.4
ASYMPTOTIC
I0.5
OPEN
LOOP TRANSFER
CHARACTERISTIC
(SOl)
........
141
I0.6
OPEN
LOOP TRANSFER
CHARACTERISTIC
(S02)
........
142
lO.7(a)
OPEN
LOOP GAIN .....................
144
lO.7(b)
OPEN
LOOP PHASZ
145
lO.8(a)
THREE
DIMENSIONAL
PLOT
(GAIN) ..............
146
lO.8(b)
THREE
DIMENSIONAL
PLOT
(PHASE) .............
147
IO.9(a)
OPEN
lO.9(b)
OPEN LOOP PHASE
IO.IO(a)OPEN I0.I0(b)OPEN
OF DISTURBANCE
SIGNAL
120
............
132
REGULATOR .........
133
REGULATOR
........
...................
134 136
CURVE ....................
140
....................
LOOP GAIN ..................... ....................
149 150
LOOP GAIN .....................
151
LOOP PHASE
152
....................
II .l
S - PLANE DIAGRAM
II .2
AUDIO-SUSCEPTIBILITY
................... ..................
-V-
157 158
LIST OF ILLUSTRATIONS
PAGE NO.
FIGURE
ll.3
THREE DIMENSIONAL
PLOT OF AUDIO-SUSCEPTIBILITY
If.4
THREE
PLOT OF GA($) ..............
If.5
CLOSED
ll.6
DIMENSIONAL
LOOP TRANSFER
......
160 161
FUNCTION ...............
182
AUDIO-SUSCEPTIBILITY
MEASUREMENT
164
If.7
AUDIO-SUSCEPTIBILITY
(DATA) ................
165
12.1
TWO-WINDING
BUCK/BOOST
..................
167
12.2
SINUSOIDAL
DISTURBANCE
..................
169
12.3
EQUIVALENT
CIRCUIT
12.4(a)
OUTPUT
12.4(b)
THREE
DIMENSIONAL
PLOT
..................
174
12.4(c)
THREE
DIMENSIONAL
PLOT
..................
176
12.5
OUTPUT
IMPEDANCE
12.6
OUTPUT
VOLTAGE
13.1
CONTINUOUS
13.2
CANONICAL
13.3
SMALL SIGNAL
13.4(a)
TRANSFER
FUNCTION
(GAIN) .................
18B
13.4(b)
TRANSFER
FUNCTION
(PHASE) .................
188
13.S(a)
OPEN
LOOP GAIN WITH
INPUT
FILTER
(GAIN) ..........
190
13.5(b)
OPEN
LOOP GAIN WITH
INPUT
FILTER
(PHASE)
19]
13.6
AUDIO-SUSCEPTIBILITY
13.7
OUTPUT
14.1
SMALL SIGNAL
14.2
BLOCK DIAGRAM
14.3
Fp(s) GAIN AND PHASE
14.4
INTEGRATOR
14.5
OPEN
14.6
AUDIO-SUSCEPTIBILITY
IMPEDANCE
....................
173
.....................
TRANSIENT
..............
INPUT TRANSFER
IMPEDANCE
MODEL
MODEL
FILTER
.........
..........
............
................
......................
VOLTAGE .................
...................... CHARACTERISTIC
183 184
193 195 200 203
...................
-Vi -
......
MODEL ...........
INPUT FILTER
WITH INPUT
OUTPUT
179 IB2
FUNCTIONAL
CIRCUIT
WITH
CIRCUIT
177.
...................
EQUIVALENT
LOOP GAIN
]71
.....................
MMF MODEL DUAL
(TEST SETUP) .......
205 207. 213
............
216
LIST OF TABLES
PAGE NO.
TABLE 7-I
PULSE MODULATOR
TABLE 8-I
SUMMARY
TABLE
PARAMETER
14-1
GAIN
OF TRANSFER
VALUES
............
78
FUNCTIONS ........
FOR CANONICAL
LIST OF NOTATIONS ..............
-vii-
CIRCUIT
82
MODEL.
199
viii-xiii
NOTATIONS
The
symbols
have
subscripts.
used
to
small
For
for The
distinguish
signal
currents uppercase
between
low-frequency
example:
vI
and
:
voltages
and
at
lowercase
instantaneous averaged
input
v I : Vl+6.
and
of
devices
subscripts
quiescent
instantaneous
values,
value
i
:
input
voltage,
dc
vi
:
input
voltage,
small
:
symbols
values,
VI
v0
terminals
values.
voltage,
average
the
average
value
signal
low-frequency
term
output
voltage,
instantaneous
value
vO = V O + 60
V0
o
:
output
voltage,
dc
:
output
voltage,
small-signal
average Period
of
a switching
Switch
on
time
TFI:
Switch
off
TF2:
A portion
T
:
average
term
low-frequency
term. cycle
P TON:
has d
"
TON T
D
:
Steady
a
:
Small
d'
:
TOFF
time of
in
the
continuous
switching
off
:
Steady
time
vanished duty
cycle
ratio
d = D + a
state
duty
cycle
ratio
signal
duty
cycle
variation
d' _ D'
-
Tp D'
inductor
state
value
for
d'
-viii-
mmf
when
operation
the
inductor
mmf
are and
J
vC
:
Output
filter
iL
:
Inductor
current
of
:
Magnetic
flux
the
winding
capacitor
of
the
T
x-- [_, vc]
and
converter
inductor
state
variables
for
buck
state
variables
for
the
: dc
loop
sensing
voltage
vAC
: ac
loop
sensing
voltage
vDC
=
of
the
two-
and
boost
converter
buck/boost
converter
v0
Stage
L
energy
Rz
winding
resistance
of
L
winding
resistance
of
the
Rp,R S
boost
converter
vDC
Power
buck
energy-storage
buck/boost
[i L, Vc ]T
X
voltage
:
storage
winding,
inductor
respectively
primary of
the
winding
and
two-winding
secondary
buck/boost
converter C
output
filter
capacitor capacitor
RC
:
output
filter
NL
:
number
of
turns
of
Np,N S
:
number
of
turns
for
two winding
= RI/(D')
= Rs/(D')2
L the
buck/boost
buck
Re = R1 2
ESR
boost
buck/boost
-iX-
primary
and
converter
secondary
windings
of
Le = L
buck 2
RCe
= L/(D')
boost
= Ls(D ,)2
buck/boost
buck
= RC
boost
= Rc/D'
Req
= Re +
RCe
-
and
buck/boost
RC
= iIL_f-6 0
e
i
rZl
Control
=
1
Re + RCe
RcC
Circuit control
loop
R3
dc
loop
resistor
R4
ac
loop
resistor
R5
compensation
Cl
operational
C2
compensation
N3
number
RI,R 2
n
:
ac
of
loop
resistor
loop
X
g
R1 H
resistor
amplifier
loop
turns
sensing
buck/boost R
divider
integrator
capacitor
capacitor
of
the ac
winding
turns
converter.
R2
R2/(R I + R 2)
-X-
sensing
winding
ratio
• n =
N3/N S
for
RY -- (R3 + Rx)/g m
= R4/(n Ry) buck
= R4/(n Ry)
boost and buck/boost
= R4/(D'n Ry)
buck
A1 = i
R
=
1 _
=
DR 1 -_
=
0
A2
2_moL e
eq+__
boost
2_moDL e
+
buck/boost
buck
= l/(RLC)
boost
:
D/(RLO
buck/boost
_Z2
:
(R5 +
rPl
:
R5C2
Ry)C2
(x |
=
A I - A2_Z2 a !
_z2
:
buck
TZ2 L
=
(_Z2
R
boost +____e)_RL (i - --_) L
:
Pulse
(_z2
L +
(l-a)_
DR
+__ __e_e _ ) (z-
_
L DL
) + (l-_)
buck/boos
_L e
Modulator:
FM
M
: 2R4C I nM
is
defined
duty
in
Table
7-1
_'Xl -
cycle
modulator
gain
t
Others
: 2 VI KI
2V I K I = D-_
buck,
M
N S 2V I boost,
K1
N
buck/boost
DM P
=
K2
D
buck
D
2VILe boost
=
_, (i + -_-)
=
=
System
NS
D
NP
D' (i +
2VlL_____e D) _M
buck/boost
I/D
buck
D'
boost
(NpD')/(NsD)
buck/boost
model:
A.
Power
stage
transfer
Fp(S)
:
equivalent
Fl(S)
:
input
functions
output
voltage
filter
gain,
transfer
(F I Fp
input-to-output-voltage
FD(S)
:
duty
cycle
gain,
output-voltage
Zp(S)
:
the
output
stage
Fl(S)
and
due
turbances
the
open
loop
function)
(FDF p represents
impedance
inductor
F4:
the
duty-cycle-to-
gain)
to
F2(s ) together ac
3 and
function
represents
transfer
of
(Zpl ° represents
variation
FI,FD,Fp,Zp,FI,F2F
(or from
the
the the
load
open-loop
current the
magnetic
flux)
output
output
open-loop
provides
the
converter
current
voltage
voltage
disturbance
small-signal
V
power
io )
low-frequency due
and
to
duty
discycle
d.
O
F3(s)
:
Impedance current Vac(S)
function or
employed
magnetic
across
the
flux sensing
-xit-
to convert
into
an
winding.
ac
the
loop
inductor
error
voltage
F4(s )
B.
:
Transfer
function
turbance
of
Analog
FDc(s)
signal
: the
the
C.
FM
: the
Duty
transfer
: the
Analytical
pulse
current
transfer
the
amount
due
to
of
load
functions:
of
the
combined
of
the
ac
dc
dis-
disturbance.
FDC
loop
and
and
FAC:
RC
loop.
function
modulator
describing
expression
(ASP)
function
transfer
cycle
inductor
processor
compensation
FAc(s)
characterizing
transfer
function
for
-xiii-
F's
are
of
the
defined
loop
function
duty
FM
cycle
in Table
pulse
8-1.
modulator
CHAPTER
I
INTRODUCTION
Due to the finite must
flux capacity
be oscillatory
operating state.
in nature.
the _ower switch Consequently,
accept
duction
obtained
it into discrete
The electrical
performance
of its control
system.
verter designer
include
multiple-loop the control minates
concept
of the power
concept
Adaptive
ac loop sensing
to a con-
response
major
program
Control
The
development Ill.
Since
efforts,
Module
of a then,
which
cul-
(SCM) for dc-dc
[3].
the following:
dc control
the inductor
the LC output
filter
dynamic
stabilities
changes
can be maintained.
exist
on the quality
of interest
the initial
[2] and NAS3-18918
loop, sensing the capacitor
iable in the form of output-capacitor
converters
primarily
Stability
In the SCM, a conventional
with
depends
from the line and the load.
prompted
several
NAS3-14392
the con-
as the converter-output
of a Standardized
of the SCM include
and the reference,
at NASA in the late sixties
has undergone
under Contracts
be able to
circuit
characteristics
both
improvement
and non-conduction
switch.
as well
disturbances,
converter
by cyclically
in controlling
of a dc-dc converter
in the development
converter
(1)
control
system must
time intervals
a dc-dc
is achieved
from the sensing
stability
for performance
elements,
in conduction
control
The performance
to step and sinusoidal
Features
of the converter
and non-conduction
incentive
The oscillation
the converter
an analog signal
and to convert
of the inductive
do employ
state.
provides
voltage, is argumented The total
the converter
in that stable operation
filters,
compensations
-l-
by an additional
of states associated
with excellent
static and
immune to output-filter
Such a characteristic
second-order
if proper control-loop
sensing
state var-
can be significant
and poor phase are notprovided.
margins
parameter as most
invariably
Conventional
frequency-response power/control operating
component
condition,
banks). defined
shaping
The
can become grossly
parameters
and more
reactive-loading
at all during
compensation
may turn out
to be grossly
loads are ultimately
and adaptively
(2)
Power Component
Stress
such as step
starting.
Without
quality
assurance
reliability electrical
(3)
between
Implementation
Various
control
conduction objective
mandatory magnetic
changes,
rates
on the ability steady-state
sudden
becomes
standard
output
load
of the
reactive
Ioadings,
and dynamic
faults,
and converter
and no elaborate The SCM achieves
implementations,
components
steady-state
of its control
data based on collective
meaningless,
circuit
power
and predictable
to limit
on an instantaneous
as well
the
as transitional
basis, op-
states.
While
Control
Laws the power
it is true that quite
and that the means
the use of a given
for many specific compatibility
resistive
stability.
the level of confidence.
through
of Various
is important
in that
late staqe
including
the reliability
laws can be used to govern
(off).
irrelevant,
failure
steady
system
depends
in all converter
orderly
or not
used in the SCM will accom-
parameters
control,
can increase
stresses
thus ensuring erations
line/load
enhancement,
(e.g. capacitor
and the complex
incoveniently
stresses during
this stress
statistical
for an assumed
aging,
Limiting
of a dc-dc converter
operations
A risk thus exists
control
the converter-load
loadings
poorly defined
the converter
at a rather
system to limit power-component
component
when
in power/control
maintain
The reliability
ineffective
of
environments,
reactive
are often
conceived
the multiple-loop
changes
external
development.
immaculately
due to variations
from tolerances,
configurations
introduced
In contrast,
modate whatever
importantly,
the converter
the original
program.
resulting
ineffective
duty cycle
applications.
may dictate
employed control
based
conduction
(on) and non-
only the achievement
to accomplish
of a control
the objective
law for dc to dc converter
For example,
a control
-2-'
often
switch
requirements
on a constant
is
is
on electro-
switching
frequency,
whereas power
in series
type of applications
switch for one half of a resonant
law based
on a constant
SCM is capable imum circuit (4)
resonant
of implementing
of Design
power
control
method
method
result
in incompatible provides
the control
audiosusceptibility
merits
design
of control
controlled
impetus
the
laws through
the following
ingredients:
and outstanding
min-
which
control
(compensation)
network
The lack of universal necessitates
the under-
which
frequently
characteristics.
The SCM
enables
the designer
through
to
given
power
stability,
power
characteristics,
system design
can be predicted.
-3-
concept
capable
(2) various
performances, guidelines
performance
programs.
system to flourish
system
NASA with
of the SCM.
cost and improved
processing
in-
through
have provided
applicability
lead to reduced
exhibited
with NASA's
cost reduction
features
the widespread
superior
performances
In conjunction
for a given control
control
and parts
can be met concurrently.
these
a basic
Often
the most
concerning
and manufacturing
(1)
is chosen
so that, for an arbitrarily
demonstrated
invariably
dictated
scheme chosen.
iterations
performance
by the SCM.
system and demonstrating
of analytically-based
design
response
NASA and military-related
conditions
often
characteristics
to enhance
are largely
on selecting
performance.
standardization,
will
regulators
stabilization
strategy
parameters
thoroughly
The necessary
performance
a control
In this regard,
configuration
procedure
and transient
Such an enhancement
control
design
performance
and fabrication
the necessary
unique
design
demand for development
for future
demands
and control
stage
system
and intricate
have been
switching
paper and bench
circuit
by power processors creasing
time.
number
is focused
and frequency
a unified
stage, the prescribed
These
attention
and a uniform
of time-consuming
select
of dc-dc
the overall
taking
control
a maximum
when a power
the subsequent
in order to optimize control
conduction
stage configuration
in the design practice,
suitable
inherently
in the
Approach.
characteristics
by the particular
designed,
cycle
current
changes.
Unification
Performance
power-switch
a sinusoidal
must
contain
of providing
equipment
using
the
and (3) the availability from which
the converter
Previous SCM-related programs have been, to a large extent, oriented toward the first two conditions. The effort was essential in establishing the multipleloop SCMas a high-performance control concept that is applicable to a variety of power converters, thus paving the way for its acceptance and further development. With such a demonstration now properly fulfilled, attention is naturally focused on the third aspect concerning the design/analysis of the SCM. It is therefore the objective of the current contract to perform the SCMcontrol-system analysis and to generate control-system design guidelines. These guidelines are expected to enable an engineer to design readily the SCMcontrol-circuit parameters and to confidently
predict that the converter performances based
on such a design will
the specified
apparent
that such an endeavor
whose singular Rather,
objective
the ultimate
of control hensive
satisfy
To achieve
- a design
results
(1)
involved
analysis.
design
that is so intrinsically
in a task
as a function
based on compre-
in such a SCM design further
analysis
to meet by a
SCM user.
this goal, extensive
Analytically
useful design
handbook
characterize
control linking
Analyze
the converter
the power
stage
performance
practice
system
functional
key
functional
power
stages
that
(buck, boost,
stage effecting
characterisitics
to perform
functional
SCM error
pro-
based on models
blocks.
Since it
the initial design
of a non-
in terms of linear operations,
for evaluating
blocks
and the pulse modulation.
block is linearized,
used jointly
can then be form-
The following
laws, and (c) the multiple-loop
for the aforementioned
is a common
information
(b) the pulse modulation
converter
obtained
is a prerequisite.
for the user.
(a) three most commonly-used
various
linear
effort
comprised:
and buck-boost),
cessor
analytical
results,
are therefore
include
(2)
normally
the control
that the confidence
into a SCM application
activities
It is immediately
only the control-system
indeed can be upheld without
Based on the analytical ulated
the effort
goal here is to provide
all given requirements prospective
is to provide
requirements
analytical
transcends
requirements.
each aforementioned
and all linear
system performances.
-4-
blocks are then
(3)
Extract both qualitative and quantitative relationships between SCMdesign parameters and required performance characteristics, formulate SCMdesign parameters and required performance characteristics, and formulate SCMdesign guidelines to meet a given set of performance requirements.
-5-
CHAPTER STANDARDIZED
Functionally
CONTROL
speaking,
a power circuit
circuit
handles
commonly
the energy
The control
circuit
manages
controlled
the compliance
signals.
quantity
limiting
provide
protection
effective
circuit
presents
in accordance
operations,
is not to conduct
against
control
as
and transient
reference,
and (B)
objective
associated
to
command becomes
with the converter
to
catastrophic/degration
types
the multiple
of regulation,
reference
the inclusion
functions
occupying
can be described
of fail-
published
here
self-contained
of this report
a previous
has
contract
of the current
is merely
work.
intended
for the benefit
For details
is shown
from a raw input Vi to a regulated
are shown here as buck, boost,
output,
under
are features
to
of those
of the SCM implementation,
in Figure 2.1. The power
the upper half of the block diagram,
power-stage
for the SCM.
recommended.
dc-dc converter
the rate of energy
through which
of SCM; such a description
of the SCM description
[3].
converter,
that the purpose
and design
to be somewhat
[3] is strongly
A SCM-controlled
functions
in NASA CR-135072,
Instead, the SCM analysis
this report
SCM-controlled
description
who have yet to read reference
ulates
transfer
(A) the tracking of
with a given
the control
at this juncture
a detailed
been given
Therefore,
energy
energy
with
A
is assumed.
such as the system response
for all elements
a generalized
It should be emphasized
enable
and the buck-boost.
steady-state
are associated
thus serves
the three aforementioned
[3].
nominal
Three most
and protection.
This chapter
already
to the load.
the boost,
into two
the power
line and load disturbances, and to external
electrical-stress
command,
During
specifications
transient
A control
By definition,
from the source
objectives
During
ures.
can be divided
the rate of the source-load
to converter
step on sinusoidal
circuit.
BLOCKS
on the part of the readers
of the load demands. the control
converter
are the buck,
of these circuits
a certain
regulated
transfer
Familiarity
operations,
(SCM) FUNCTIONAL
and a control
used power circuits
a function
MODULE
a dc-dc
parts:
2
processes
output Vo.
and buck-boost.
transfer.
and delivers
It receives
a discrete-time -6-
the transfer
Three
The control an analog interval
circuit, of
basic power circuit signal
stages
reg-
from the
signal d to achieve
Q.
r
•
t_ Z -'IU F-
_z Om _z
._1 _J O Fz O
1
0 I.i.I _,._I,-. E
,--I I
0
I'E J
14. Z k&.'_
El-....14. EO
ZO Q(.,_
O---_..ip I-,. _z_ _UUE ul I-- _ Q. ¢¢J _-
-7-
the required
on-off
The discrete-time averaged
signal
voltage
by an LC filter
crete-time ligible
or current
only
switch within each
pulses
having a much
generated
longer
The averaged
switching-frequency containing
components,
time constant
output
Signal
therefore
and DSP are standardized; to discrete-time
(DSP).
they combine interval
to provide
conversion.
As a result, filter which
an adaptive
parameter processes
the control-signal
control
duty-cycle
signal
respond
The command
function
signal capable
generally
of the power switch.
peak-stress
limiting
the
dc sensing
is completed
by the ASP. of the
by the DSP,
switch
within
have been presented
The three basic functional in the block
diagram
with a via a
of the basic analytic
approach
command
the converter
control
to
signal d in function
shutdown
undervoltage,
Detailed
includes
in the event
or overcurrent
These
functions
ASP and DSP implementations
[3]. blocks of an SCM-controlled
of Figure 2.2.
in Chapters
requires
level and duration.
SCM by the DSP. in reference
also include
and the converter
tolerable
a predetermined,
be presented
within
is independent
The protection
beyond
will
of the SCM
signal
of the power
of overriding
such as overvoltage,
shown
which
functions
of a sensed abnormality
are performed
analog
from the ASP in conjunction
the on-off
the control-circuit
the on-off
power-component
of both ASP
d.
to an external
determining
Processor
are processed
function
output
law, and operates
previously,
and protection.
is obtained
The SCM control
the con-
to the conventional
ac signal and the dc error
changes.
prescribed
As stated
is in addition
stability
neg-
Signal
The key feature
utilization
The sensed
performs
the required
power stage. Vo.
are
as an analog
Implementations
of an inherent ac switching-frequency
of output
contains
an Analog
is the utilization This
stage
information.
It contains
Processor
stage.
than the dis-
and can be regarded
lower-frequency
the converter.
(ASP) and a Digital
power
in the power
the lower half of the block diagram,
function within
signal
of the power
pulse intervals.
The SCM, occupying trol
control
Analysis
4, 5 and 6, following presented
-8-
in Chapter
converter
of these a general 3.
three
are
blocks
discussion
V o
Vi POWER
STAGE d
v
Q O f,.;
ERROR
DIGITAL
ANALOGUE
SIGNAL
2.2,
SWITCHING
REGULATOR
SIGNAL
PROCESSOR
PROCESSOR
FIG,
i
BLOCK
-9-
DIAGRAM
CHAPTER 3 SELECTION OF
A dc-dc switching-regulated containing
multiple
ANALYTICAL
converter
APPROACH
is an inherent nonlinear
nonlinearities.
The first major
in the power stage, and is due to the operation Different
circuit
time intervals exists
topologies
in the switching
in the Digital
which
are multiples
are encountered
a specific
3.1
Processor
of
such
and response
chapter,
approaches
(DSP).
frequency,
assessments
attenuation
switch.
nonlinearity frequencies, are contained difficulties
of various
system
of sinusoidal/step
to sinusoidal/step
line
load disturbances.
these nonlinearities
are elaborated,
and various
of treating these nonlinearities
of analytically-based approach
Harmonic
of this program,
as the basic
are dis-
which
and performance-oriented
is then selected
exists
on and off
system nonlinearities,
performance
capable
of the power
The second major
In light of the stated objective
preparation
entire
Because
in reaching
In the present
cussed.
cycle.
such as stability,
disturbances,
analytical
Signal
nonlinearity
to the respective
of the input disturbance
in the DSP output.
performances
correspond
device
is the
design
analytical
guidelines,
tool for the
program.
Power Stage Nonlinearity
Each of the power stages shown the inductor MMF status
in Figure
in the output
erred to as "continuous-conduction" ascends
never vanishes
during
In Figure
Mode
I of operation,
inductor.
to as "discontinuous-conduction" from zero MMF at the beginning additional OFF, during
or
which the inductor
is ON.
In Figure
Notice 3.1(B),
Mode 2 of operation,
both the power
MMF remains
by the output-filter
-lO-
zero,
capacitor.
3.1(A),
often
of
ref-
the MMF
is ON and the diode
of Ton, and descends
off time TF2 exists when
entirely
switch
TFI when the diode
in the output
as a function
filter.
during on time Ton when the power
OFF, and descends
supplied
or
2.1 can be divided
that often
is
the MMF referred
the MMF ascends
during
TF I.
An
switch and the diode
and the load current
is
are
0 l-f-,. uJ 0
0
b.1
Z
,-4
I,-
I--
I,tJ
W iv,
0
,-b U
E E 0
z c_ I--
0
z ,--
Z
z
Z 0 U
'-'
cg "el.l,Jr._ I,.LI "_I -.-_,
.I__.225
E 0
f, z
I-, Z w
u 0 _J Z l--Z
u_ ZU..
T _-
0 -m i_ P-,
i
'-' Z
=E:
-11-
Taking
the continuous-conduction
circuit
topologies
Even though
corresponding
switching
a nonlinear
cycle
circuits
problem.
3.2
the combination
of analyzing
a
of both Ton and TFI becomes here is how to integrate
evaluate
having a much longer
3.2.
Ton in Figure
Being
3.2(B),
thus severely and causing
caused
their responses
to
time period than
in-
DiBital
discrete-time
the power switch
seeks a complete the analysis,
using Fourier
of the disturbance frequency
frequency
and the regulator
input results
circuit
3.3
Nonlinear
A common
starting
portrait
regulator
in how the duty cycle
(ASP) output.
in the processed
Obviously,
if one
have to include all harmonics
as well as the beat frequencies switching
d(t) of
of the propagation, such a disturbance,
techniques, would
frequency. output,
of the disturbance
Thus a single-frequency an inherent characteristic
operation.
Analysis
point
Techniques
for switching-regulator
of a state vector X and an input the system
in the analog-signal-to-
by a small disturbance
in an multiple-frequency
of nonlinear
Various
is propagated
Processor
analytical
of a linear
Nonlinearity
affected
error at the Analog Signal
of the power-
purposes.
one is interested
is being
in Figure
in the derivation
and design
how a disturbance conversion,
its presence
the nonlinearity
complications
Signal Processor
To characterize
part of the power stage
it withdraws
increasing
major
by the input filter is also demon-
an.lntegral
power stage model for analysis
system
composed
and collectively
disturbances
in Figure
3.2(C),
3.2
in Figure
the
Ton or TFI.
strated
stage,
for the purpose
The difficulty
The power stage nonlinearity
during
for illustration,
to Ton and TFI are shown
of operation
topologies
lihe/1oad
dividual
linear
analysis
these different various
converter
the power stage is linear for each time interval,
of the two different complete
buck-boost
state variables, input voltage,
representation
while
vector U.
etc.
is:
x_ = Flx_ + GIU
during Ton
x_ = F2x + G2U
during
TFI
is the identification
The (nxl) vector X contains
the (nxl) vector
the reference,
-12-
analysis
U is associated
For continuous
all
with
the
conduction
the
V o v I
i
T
v_-
T (A)
Buck/Boost
Converte r.
JC
I. Ns
Z V_-4_mmmmm
I
J m
! I
UL
I
L_
I
a
i
i
vo
v
(B)
Buck/Boost
Topology
During Ton.
Vo Cr_
L v_
N:__J
m,m b.
9mmm,
H-
T
a.
z_
i T w
i
(C)
FIG,
3,2
Buck/Boost
BUCK/BOOST DURING
EACH
Topology
CONVERTER SWITCHING -13-
During TFI.
TOPOLOGY INTERVAL,
CHANGES
The (nxn) matrices F1 and F2 and the (nxn) matrices G1 and G2 are constant matrices composedof various circuit and input parameters. discontinuous conduction, an additional equation x : F3x + G3U
In the case of
during TF2
is added to complete the system representation. Starting from this commonrepresentation, various analysis techniques differ only by the meansthrough which linearization of the nonlinear system is achieved. These techniques have been described in detail in the literature [4,5].
In the Discrete numerically
Time Domain AnalEsis,
evaluated
and linearization
by analytically/numerically where function instant
"f" relates
switching
into functional practical
state.
regulator
switching-regulator
Time Domain
the disturbance
in the nonlinear
through
which
threshold
the disturbance
The process entirely
on digital
piece
is allowed
computer
simply
it
For most is indispen-
the nonlinear-circuit
is needed
as
to propagate
to one switched
for that interval
into the next switched
simulates
applies
analysis.
corresponding
condition
by piece.
a digital
time
separating
[8], no linearization
system
matrices
enters
actually
In the AveraBe tation
Simulation,
the state-transition
until a specific
each block
numerical
of Bf/Bx,
the linearization without
is
is achieved
differentiation
as a single entity
out the detailed
state
tk+ l to X at an early
By so doing,
applications,
In the Discrete
the equilibrium
the partial
X at time instant
blocks and attacking
sable in carrying
about
performing
tk in the equilibrium
to a complete
[6,7], the system equilibrium
is reached,
interval
interval upon
recurringly.
response,
thus depending
or analog computers.
Time Domain Analysis
for a complete
switching
[9,10],
an averaged
period T is formulated
-14-
state-space
represen-
by simply summing
the
state-space representation
of the individual
switched interval
Ti properly
weighed by the corresponding time ratio Ti/T. Linearization is accomplished through straightforward perturbation of the averaged representation. A small-signal power-stage transfer function is thus obtained in the frequency domain. The transfer function of the ASPis readily derived using linear circuit analysis, as the ASPis strictly a linear device in smallsignal operations. The nonlinear DSPis treated by the describing-function technique, Ill,12]. The power stage, the ASP, and the DSPare treated as as three separate functional blocks, and the transfer function for each is derived to facilitate a complete regulator system analysis.
In the
Discrete
in Figure
Time
Impulse
3.2 is described
manipulation
of the state
interval, and matching representation This discrete continuous details
transition
up boundary
can be derived system
impulse
response
of the linear The discrete
impulse
frequency
frequency,
approximation,
the existence
the system
exactly.
and approximated
The frequency
technique
by a
switching domain
the Laplace
time domain
transfer
transformation
lhe technique, to obtain
increases
beyond
rather
model
which
however,
is only a low rather
solution
the second order. complicate
up to half of
becomes
a closed-form
approach
The model
is exact
than close-form
-15-
a uniform
inductor.
technique
unlike the average
results
provides
and discontinuous
of an input filter will
that only numerical
time
time domain
to neglect
by performing
modeling
impossible,
order of the system
mathematical
response.
time domain
some, sometimes
a discrete
linearized
if one is willing
simply
from the discrete
the switching
conditions,
trends.
Through
for each specific
that characterizes
covers both continuous
derived
[13, 14], each topology
equations.
matrices
is subsequently
can be derived
Anlaysis,
by state-space
and study the long range
function
which
Response
cumber-
as the
Consequently,
the analysis solutions
considerably
so
can be obtained.
3.4
Selection
Although degree
of the Average
the discrete
of accuracy
are, basically,
Time
time domain
analysis
in describing
numerical
Domain Analysis
the behavior
approaches.
gain from the discrete-time
approach
control-performance-oriented
design
response
model
sentation, becomes
of the power stage
the method
rather
the second order.
procedures.
offers
of analytically-based
the average
time domain
engineering
tool to fulfill
analysis
resides
the stated
frequency
domain)
analysis,
analysis
to
the discrete
increases
impractical
of this program
impulse repre-
solution beyond
for generation
is the pre-
design guidelines,
is seen as a more suitable
objective.
In conjunction
and performing while
the average
is selected
they
and to visualize
a closed-form
somewhat
approach
system,
and closed-form
and performance-oriented
in most engineers
said for the time domain
Although
and obtaining
the fact that the skill of comprehending domain
insight
the order of the system
analysis
a higher
it is difficult
high accuracy
Since the objective
offer
of the control
any closed-form
The method is therefore
of design guidelines. paration
when
simulation
Consequently,
is sophisticated
cumbersome
and/or
for the SCM.
with
the frequency
the same cannot be time domain
as the basic
(continuous
analytical
tool
for this program. In essence, linear
the averaging
circuit
duty cycle. averaging
As a result,
The analysis
is plausible
behaviors
range considerably
configurations will
a means
of the system
exists at a converter
the small-signal
a frequency
The circuit
nature
The approach
generally
provides
with all the RLC elements
The discrete
process.
pass filter
fined to
model,
technique
5, with
derivations.
-16-
an equivalent
by the appropriate
is therefore
lost in the
due to the fact that a lowfor ripple attentuation.
of practical
to be analyzed
start in Chapter
modified
output
lower
of deriving
concern are usually
than the switching
are presented power stage
con-
frequency.
in Chapter 4. transfer-function
CHAPTER SCM-CONTROLLED
DC-DC
SWITCHING
Three most commonly
used power-stage
and the buck-boost,
are shown
identical
SCM shown
voltage
Vo.
stored ing
When
switchS
causes
contributed entirely alent
L, which
and continuity
through
D, which
lecting
all dissipative
excursions dictate
Rc.
supplies
in L during
C, partially
When
resistanceR{.
Capacitor
load RLand
in L is maintained
replenishes
drops
associated
in RL is and
C has an equivoff time TFI by a current
the charge with
is
The conduct-
for the buck converter
on tin_ Ton is completed,
of current
voltage
by an
V i to an output
and load current
converters.
in C.
Neg-
L and C, equal flux
Ton and TFI for "continuous-conduction"
operations
that
Vo -- Vi/(l + TFl/Ton ) Vo = V i (I + Ton/TFI) Vo : V i (Ton/TFI)
Thus,
the boost,
during on time Ton, energy
has a series winding
for the boost and buck-boost
is initiated,
an input voltage
S conducts
capacitor
series resistance
the buck,
half of Figure 2.1.
diode D to be back biased,
by output
CONVERTERS
configurations,
stages converts
power switch
in inductor
REGULATED
in Figure 2.1. Each can be controlled
in the lower
Each of the three power
4
by controlling
for a varying
(Ns/N p)
the time ratio
central
(4-I)
boost
(4-2)
buck-boost
(4-3)
Ton/TFl,
a constant
Vo can be maintained
Vi for as long as
V° < V i
buck
V° > V i
boost buck-boost
Vo _ Vi
As stated
buck
in Chapter
element
2, the SCM is composed
of an ASP and a DSP.
of the ASP is an integrator-amplifier
-17-
The
with a feedback
capacitor
e
CI, as shownin Figure 2.1. It processes the following
The dc output
voltage
vo through
the dc loop resistance •
The ac voltage
Vac across
The rate of change and resistance
a winding
the dc error
voltage,
of vo, i.e., dVo/dt,
Vac,
amplified
the duty
change
amplifier
in the direction
The leading
cycle control
of restoring
(2) constant
[3].
include:
TFI,
variable
Ton,
Vo per equations
The following •
should
Since there always configuration, sing
within
become
exists,
an inherent
change
applied
state.
of combinations
(Ton + TFI), ViTon
is capable
apparent
within
variable
detector
ac waveform
to achieve -18-
Ton),
suitable
the desired
variable
a regulated
stages.
from the foregoing
any switching
the duty-
Ton and TFI,
of providing power
time
of Ton
(or constant
the ASP, the SCM implementation
can be readily
in the duty
of IC oscillators,
(4-I) to (4-3) for the respective
features
Any
is processed
from the threshold
a variety
(3) Constant
Any of these DSP mechanizations
actuates the transient
on how the DSP is mechanized,
through
(1) constant
ET, which
To improve
in C2-R5, which
The DSP is composed
on the
to sense dvo/dt.
vo to its nominal
Depending
Both Vdc and Vac
level
switch S.
pulse output
an ac
is superimposed
threshold
R5 are added
level VT
Concurrently,
to cause a corresponding
can be achieved
and TFI, which
TFI.
a fixed
gv o
gvo-E R becomes
The dc output
output
cause a current
the DSP.
and memories
C2
the voltage
Vdc =
by Vdc.
cycle of power
edge of the digital
is used to actuate
capacitor
fed to the amplifier.
C2 and resistor
in vo will
by the integrator
amplifier.
integrator
dc error to intersect
transient
through
The difference
is determined
the triangular
capacitor
delays,
ER.
is differentially
response,
cycle
reference
amplifier
the DSP to control
inductor L, through
ratio of the dc loop,
input to the integrator
are integrated;
on filter
R5.
with
of the integrator
RI-R2 and
R4.
Let g = R2/(R l + R2) be the divider is then compared
divider
R3.
the ac loop resistance •
a voltage
three signals:
description.
regulator for ac-loop
shown
proces-
in Figure 2.1
analog-to-discrete-
time convertion All possible
for all types
duty-cycle
ready implementation
The circuit various basic
shown
in Figure
power circuits
configuration
The analysis
starts
for all three power
of switching
control
regulators.
laws are within
the
of the DSP.
2.1 thus exhibits
as well as control
for all analytical in Chapter
a commonality
laws.
effort
It therefore
to be pursued
5, with the derivation
stages.
-19-
in accommodating serves as the in this program.
of transfer
functions
CHAPTER 5 POWER STAGETRANSFER FUNCTIONS ANDBLOCKDIAGRAMS Having adopted the average time domain analysis,
the power-stage functional
block is now analyzed for each of the three power stages shown in Figure 2.1. The analysis will be carried out in the "continuous-conduction" operation, as this is the prevalent operating modefor most dc-dc converters. The discontinuous-conduction
operation will
seldom used as the intended design at full semiconductor
peak current
ponent Currents.
and a poorer
Consequently,
for the continuous-conduction conduction However,
operation
no design
on the control
The continuous-conduction the input voltage transfer
quantities.
Matrix
(2)
State-space
(3)
Linearization
(4)
Transfer
To enhance treated
5.1
commonality,
d.
for all the power-comwill
The effect
of the discontinuous-
be treated
be formulated
in Chapter
for power
two small-signal
To derive
output
15.
in the following
stages during
inputs:
the power-stage
v0 in relation
can be acieved
averaging
to these
two
sequences:
Ton and TFI.
and perturbation.
and System
function
it leads to a higher
Behaviors.
and block diagram
the three different
derivations.
power
stages
in Figure 2.1 will
concurrently.
Matrix
During
formulation
is
have been contemplated.
one must formulate
(1)
load, but it
guidelines
system will
power stage receives
The formulation
since
form factor
only.
v I and the duty cycle
function,
load
the SCM design operation
guidelines
occur at light
Formulation
Ton and TFI,
in Figures follows:
5.1(A)
For Power
Staqes During On Time and Off Time.
three power stages shown
to (C), respectively.
-20-
in Figure
2.1 can be represented
State variables
are chosen as
be
TOFF
TON
R_. L
R_. L
(A)
Rl
BUCK
L
R{
Rc
vl
L
R L VT
C
(B)
BOOST
Rp
Rs
_L VT
Rc
--
I
RL
Ls
RL
C
(C)
FIG,
5,1
CONVERTER TON
AND
BUCK/BOOST
TOPOLOGY TOF F, -2l-
VARIATIONS
DURING
Buck
x/ : [iL,
Boost
_
Buck-boost
x
(5-i)
vC]
T = [iL, VC]
(5-2)
= [¢
(5-3)
T , vC]
Where iL is the inductor current, _l. Flux _ is chosen as the state place of the inductor the current
as the flux is continuous
is not in this converter.
stage can be described
For T
current,
and VC is the capacitor voltage in Figure variable for the buck-bOost converter in
by the following
The complete
with time whereas
behavior
of each power
two sets of equations:
Interval : on
(5-4)
: A1 x__+ b I v I
Vo= C1T x_
For TFI Interval:
_x : A2 x + b 2 vI
v0:
(5-5)
c2T
Here, AI, bI, C_, A2, b2, and C_ are constant parameters. following
It is proved matrices
matrices
that if the assumption
are obtained:
-22-
composed
of circuit
RL_mR C + R_ is made,
the
For buck
power staqe:
11
Al =
l
_ I_ 1 (R_ + Rc) C
(5-6)
i]
bI =
'b2=I °]o
0
C1T =
For boost
[
Rc
I]
,C 2
Rc
power stage:
A1 = I
01
L 0 R
R_ + Rc L
A2=
1
l L
l
CRL
(5-7)
;] L
bI
=
, b2 =
0
C1T=
For buck-boost
[
0
I]
,c2T
:
staqe: R _E
A
l
RS
N
CR L
'b2:
0
T
Cl ' =
[° l]
I
S
l
LsC
CR L
0 N R S
c2T: -23-
C S
-l
I]
R
+
L
A2=
Lp 0
bI =
i]
[ Rc
[
Ls
C
5.2
State-Space
Averagin 9 and Perturbation
Averaging over a single period (dT + d'T) where d = Ton/T , T = Ton + TFI , and d' = l - d, equations (5-4) and (5-5) are combined to give:
= [dA 1 + d'A2] _ + [dbI + d'b2] v I
(s-g) Vo=
[dcIT + d,c2T ] x_
Oft
)_ = Ax + b vI
(5-1o) Vo:cTx_
Substituting obtain:
eqs.
(5-6),
(5-7), and (5-8)
-24-
into (5-9) and (5-I0),
one can
For
buck power
stage: R_ + Rc
A = IdA l + d'A 2] :
CR L
(5-11)
cT=[dCT + _'CT] = [R_
I]
For boost power stage:
A--
d'
R_ + d'R c k
"_
L
!
C
CR L 1 (5-12) b:
cT=
L
[d'Rc
i] -25-
For buck-boost
power stage:
!
Rs + d'R c
Ls
N s
assuming d'N s
1
_I_ -
Rs
Lp
Ls
LsC
(5-13) Np
b
0
cT= d,Ns L s Rc
In the derivation made.
The state-space
of (5-13), a simplifying
averaging
has combined
assumption
the different
corresponding
to Ton and TFI into equivalent
are presented
in equations
be linearized
using perturbation
(5-II) to (5-13). techniques,
A
variation
Rp/Lp = Rs/L s has Seen
circuit
time-varying
topologies
systems
Each of these by introducing
which
systems can the line
A
¥i and the duty-cycle
variation
d in the following
forms:
a
vi = VI + vi a
d
=D+d
d'
=
A
where
D'
-
(5-14)
d
V I is the dc line in)ut voltage,
esponding
to VI for a given
cause the state vector
_and
D is the steady-state
VO, and D' is equal output
voltage
-26-
to (l-D).
duty cycle
corr-
Such perturbations
v0 to be similarly
perturbed:
x = X + ^x
(5-15)
A
v0=
V0+
v°
(5-16)
Substituting one obtains:
(5-14) and (5-15)
x = (A _X + b V I) +
into the first
(A ^ x + b ^v i)
+
[(A l - A2)
(line variation)
(steady-state)
A
part of (5-I0), and knowing
(duty-cycle
x t 0,
_X + (b I -b2)Vl] ^ d variation)
^
+[(A l - A2) __ + (bI - b2) vii d (nonlinear
(5-17)
term)
Substituting
(5-15) and (5-16) into
o:C T _
_x d
(line)
from (5-17) and
voltage
5.3
Linearization
Assuming
itself,
x
perturbation value
is small
the departure in relation
of each state
from
to the steady-state
A
x
I
(6-19) is given by the expression:
+R_\ +
•
eqe ._// 1 L L-_c-
in eqs.
the following:
-46-
(5-I), (5-2), and (5-3), one
(6-20)
For buck power
-_(s) _
_ l
^v i (s)
stage:
l
D
(I + sCR L)
A LeC RL
(6-21)
A
i_(s)
_ l
(s)
l
V0
A LeC
(6-22)
(l + sCR L)
DT L
For boost power
stage:
A
i (s) vi(S )
1
1
1
A
LeC
(D,)2RL
(6-23) (I + sCR L)
(6-24) i_(s)
1
l
V0
_(s)
_
LeC
(D')2R L
(2 + sCR L)
-47-
For buck-boost
power stage:
(6-25) _i(s )
__(s) ^ d(s)
:
A
Np
: I Vo a
DNs
s + RL c
s + RL l+__D_D C )
-48-
(6-26)
A
From eqs. become
(6-21)
to (6-26),
the composite
expressions
A
of i_ and
the following:
For buck
power stage:
1
1
?_(s)=_ _ l
l LeC
For boost
D
^
_ (i+ sCR L)vi(s )
(6-27)
Vo (l + SCRL) _(s)
DRL
power stage:
^
1
1
1
A
LeC
i_(s) -
(l + sCR L) _i(s)
1
(D')2
RL
1
VO
LeC
(D,)2R L
^
+
(2 + SCRL) d(s)
For buck-boost
)(s) -
power stage:
D Np
VO ÷
(6-28)
(1) S
÷ R--_-
A
vi(s) I +D
DN-_ (s+ R,C
) _'(s)
-49-
(6-29)
The term vi(s) on the right-hand now be replaced
by expressions
three power stages. the composite
side of equations
involving
Equations
(6-27) thorugh
(6-29) may
So(S ) and _(s) for each of the
(5-37) and
(5-46) are combined
to yield
expression
o(S): Fr(s)Fp(S) which may be solved
for Vi(S)
+ FD(S ) Fp(S)C(s)
to yield
A A
^
Vo(S)
Vi(s)
Equation
=
_-_
and holds
(6-30) successively
(6-29), and using the expressions chapter
5, equations
(6-3o)
rl(s )
(6-30) is general,
tuting equation
FD(S) d(s)
relating
for all three power
into equations
stages.
(6-27),
(6-28),
for FI(aS), Fp(S), and F_(s) A
the terms
uA
These
and
found
i_(s) and ¢(s) to Vo(S)
for each of the three power stages may be obtained.
Substi-
in
and _(s)
equations
are:
For buck power stage:
^ (s) is
-
1 RL
1 + sCR L 1 + sCR C
^ Vo(S)
(6-31)
For boost power sta.ge:
^
1 + sCR L
^
V0 ÷
is(s)
= D-,RL(I+'SCRc) Vo(S)
(D')2
-50-
RL
(6-32)
For buck-boost
:
power staqe:
Ls Ns
_(s)
Substituting
^
Vac(S)
1 + SCR L D'R L (l + sCRc)
(6-31),
=
(6-32),
and
_o(S )
L_s s Ns
Vo (D,)2RL
(6-33) into (6-12) and
[
F3(s)
+
Fl(S) _(s)
+
F2(s)_o(S)
]
_(s)
(6-33)
(6-13),
(6-34)
where:
For buck power stage:
Fl(S)
=
0
1
1 + sCR L
RL
I + sCR c
D
F2(s)
(6-35) F3(s )
:
snL
N3 N
n
For boost power stage:
F](s)
-
Vo (D')2R L
l + sCR L F2(s)
=
b'rRL (l + SCRc)
F3(s)
=
snL
(6-36)
N3 fl
-
N -51-
For buck-boost
stage: Vo
FI(S)
: (D')2R
L
1 + sCR L F2(s) :
D'R L {I + sCR c)
F3(s) = snL
(6-37)
N3
n
6.3
ASP Transfer
Equations
Function
(6-8)and
ASP.
An equivalent
where
FDC, FAC,
(6-36),
for each
Diagram
(6-34) completely block diagram
define
is readily
Fl, F2, and F3 are given
and (6-37),
three different
and Block
respectively.
power stages,
power stage.
-52-
shown
function
of the
to be that of Figure 6.2,
in eqs. (6-9),
Functions
whereas
the transfer
(6-I0),
(6-35),
FDC and FAC are identical
Fl, F2, and F3 are somewhat
for
different
A A
T
T ,,
F3
]
FAC
I ii
FIG,
6,2
SMALL
SIGNAL
MODEL
-53-
FOR
THE
ASP,
CHAPTER 7 DIGITAL SIGNALPROCESSOR DESCRIBING FUNCTION ANDBLOCKDIAGRAM The Digital Signal Processor (DSP) converts the output voltage vT of the ASP into discrete-time pulses to control the on-off of the power switch. Voltage vT, which contains the amplified dc error and the triangular ramp, is made to intersect a fixed threshold level. A digital signal is issued at the DSP output when the intersection occurs. This signal initiates a switching event for the power switch. The duration of the switching event and its repetition rate are prescribed by a control law implemented in the DSP. The present chapter is devoted to the derivation of the DSPdescribing functions for a variety of control laws. The control laws can be implemented with either one of the following: • Constant on time regardless of converter input voltage vI. m Constant on time for a given converter input voltage Vl, with vI Ton being kept constant. • Constant off time. •
Constant on time plus off time, i.e.,
For reasons discussed in detail
constant frequency.
in Reference [3],
the last two control
laws
are preferred by the SCMdue to their more effective peak-stress limiting and source EMI control. Being the more con_nonlyused approach, the constantfrequency DSPwill serve as an illustrative example for the describingfunction derivation. Derived results for other control laws will also be summarized. 7.l
Definition
of Pulse Modulator
In a typical
two-loop
the buck regulator, the converter
a triangular working
the constant
system,
a proper
waveform
across
with the externally
mechanism frequency
the clock initiates
to effect duty cycle
the on-time
as illustrated to sense
dc regulation, the output
ramp vT at the integrator
in unison
the necessary
control
a dc loop is employed
to achieve
sense the switching
Stage
amplifier generated
in Fig. 7.1 for
the output
filter
inductor
output. threshold
This
control
as an example
and the intersection
to provide ramp, when
level,
duty-cycle
-54-
of
and an ac loop is used to
the regulator shown
voltage
produces
control.
Using
in Fig. 7.2,
of the integrator
out°
ILl FZ >. Q J r_ iii r_ Q .J 111 v U
A,,I. Q U I,-,.
W" _m
u
m
o
L_ Ii
-55-
LI.I I.I,J I.II,aJ O Z "::K n,," I,-r,,/')
4-
.-I O
C
Z O (_) I.LJ ,--I (_) >(_)
m
÷ eN
_I--
C O,I
)-
I1,,I ,--_ LI.I m,,,' I.I. A
A
Z
,,_ I,-(,o Z O (,.) I.I.. O
O
I--
f
rO
I.,U LIJ ._1 n
Z
i,,-,,i
N
m
I,J_
A
A
I-
"O
-56- .
put voltage
vT with
TON interval. v T decays
the threshold
During
almost
voltage
the on-time
linearly
with
ET marks
interval,
a slope
the termination
of the
the slope of the ramp voltage
SN approximately
by the following
equation
-n(v I - Vo) SN
where
R4C l
v I -v 0 is the voltage
series
resistor
is determined
interval _ON
across
R_, n is the turns
R4C l is the time constant off time
drop
the energy
storage
inductor
and
ratio of the ac sensing
winding,
and
of the ac loop.
by the next clock
+ TOFF)"
The slope
The length
of the subsequent
signal of the predetermined
S F of vT during
TOF F is approximated
by
nv 0 SF = R4C1 Following
this pattern,
Fig. 7-2.
If the converter
disturbance,
the duty cycle
the votlage
is subjected
waveform
Fig. 7.3, will be modulated. also contains that
a low amplitude
waveform which
output
As a result,
error
voltage
signal
generated
(disturbance)
provides
by the operational
a necessary
ramp
as the solid curve
component.
the following
low-amplitude
error signal and the high amplitude
summing
into a composite
junction.
describing
In order
function,
the low frequency
which
waveform
is a necessary
analog-to-digital
element
conversion.
conversion
pulse modulator.
ramp switching
the composite
to the intended
the switching
waveform
amplifier by a waveform
frequency
pulse modulator
triangular
in the pulse modulator
to implement
It should be noted
in Fig 7.4 that
-57-
The
in Fig. 7.4, one representing
as the input
and the other representing
The latter
the pulse modulator
to separate
as illustrated
error signal
switching
vT by the operational
to characterize
it is necessary
of v T into two components
model,
part of the duty cycle
in Fig. 7.3
both the
for analog-to-digital
as an integral
are integrated
through
integrator.
is considered
d(t)
information:
and a high-amplitude
amplifier
function
in
It is shown
propagated
loop,
in
low frequency
the duty cycle signal
contains
loop and the ac feedback
is illustrated
to a small-signal
vT, shown
a low-frequency-modulation
the integrator
dc feedback
signal d(t)
the
ramp
Z oc oo C_ O C_ t_ ,,,
09 co n_ t_ pn_ > z O "U z ,,I N
C_
N m
LA.
C
N
LIO O0 toO tA. t_ >
m
tJ-
i -58-
MODELING AC
APPROACH
ERROR
SIGNAL
A/V LARGE-AMPL SWITCHING
SMALL
ITUDE HAVE
FORM
AC
AMPLITUDE
ERROR
PULSE
SIGNAL
ERROR
MODULATOR
PROCESSOR i
ERROR DC
SIGNAL
PULSE
ERROR
SIGNAL
MODULATED DUTY-CYCLE SIGNAL
FIG,
7.4
SEPARATION
OF
THE
ANALOG
SMALL-AMPLITUDE
LOW
LARGE-AMPLITUDE
SWITCHING
SIGNAL
FREQUENCY
-59-
RAMP
FROM ERROR
THE SIGNAL
WAVEFORM,
AC
LOOP-
AND
not only are switching intervals, frequency
disturbance,
To characterize disturbance output
TONand
TOF F, modulated
so are the respective
the small-signal
behavior
vX, shown in Figure 7-5,
and the threshold-detector
slopes,
SN and SF.
of the DSP, a low-frequency
is injected
input,
by a low
between
the amplifier
where: (7-I)
vX (t) = A Sin _t
As a result
of the disturbance,
and d(t) can be constructed
Vx(t), waveforms
in Figure
of vT(t),
Vy(t),
7-6, where
(7-2)
vT(t) = Vx(t) + Vy(t) The duty-cycle
signal
d(t) at the DSP output,
pulses of equal amplitude a low-frequency Fourier-series
content
but sinusoidally-varying corresponding
expansions
d(t)
which
contains
a series of
pulse widths,
to the input disturbance
will
have
frequency.
of d(t) and VT(t) become:
= D + a I sin _t + bI cos _t + ..... (7-3)
VT(t ) = VT + cI sin mt + dI cos mt + .... The describing
FM _ ___ Ot
function
(al2 (Cl2 + + bl2)½ d12)½ exp [_ j(tan-I
In the following
presentations,
a constant-frequency involving will
certain
a wider duty-cycle
mentioned
DSP.
derivations
stant-frequency
results
phenomenon
An effective
remedy
for other control
control
as:
function
FM is derived
and an operating
results
laws are summarized;
law.
-60-
range
the stable operation
Finally,
for
subtlety
a stable duty-cycle
to extend
instability
(7-4)
dl )] tan-I _ll
beyond
range is then analyzed.
duty-cycle-related
bI _-
the describing
Analytical
instability
be discussed.
function
FM of the DSP is defined
to
of describing the afore-
is found to be unique
to the con-
55
O O O 0::(,-) l,_
It:C-) Ii {3
0
w_ "-r I--LI.J
li
Z...I LI.I ::3 L61I_. i... Ill i.I.i "r" rml'-
-Ji-Z0..
__z (/)ill I.I.I -r(")I-. Z
.-10::
I_ °I r-,c:,l_
Ie_, _1 i=
o _
I--
v X
-I-
v _.1 e,,-
N
-82-
II
1.6.
Figure
8.2 is a unified
converter control output
types.
loop dependent impedance
Stability. transfer output
This
blockdiagram block
diagram
performance
function
modulator
input,
assuming
of the converter
to examine
including
the
stability,
of the converter.
is investigated
the disturbance
i.e. vi = O. _
for the three
will be employed
and audiosusceptibility
The loop stability
are zero,
representation
= O.
via converter
from both
By opening
the open loop transfer
open-loop
the line and the
the loop at the pulse
function
can be expressed
as
GT(S ) = FM(S)FD(S)Fp(S)FDc(s)
+ FM(S)F3(S)FAc(S)[FI(S
Audiosusceptibility.
The audiosusceptibility
by the closed-loop measure
input-to-output
the rejection
the converter to output
) + F2(S)Fp(S)FD(S)
transfer
rate of a sinusoidal
input to the output.
transfer
function
GA(S)
of a converter function.
disturbance
Assuming
]
(8-I)
is evaluated
It is employed propagated
from
7o = O, the closed-loop
is expressed
to
input
as
A
GA(S)_
Output
Impedance.
at the output
io(S),
The converter
current
characteristic. A
Vo(S) FI(S) s)[l + Fl (s)F3(s )FM(S)] _ _ Fp( )FAc(S vi(s ) 1 + GT(S)
performance
can be investigated
The output
impedance
due to sinusoidal
using
the output
is measured
(8-2)
disturbance
impedance
as the ratio
of
v%(s)/
A
where
The output a switching
io(S) is the sinusoidal
impedance regulator
disturbance
is employed
to measure
subjected
to sinusoidal
-83-
at the converter
dc or dynamic
output.
performance
load variations.
of
Letting
Oi = O, one can express
the output
impedance
as
Oo(S) Zp(S)(I+FM(S)FI(S)F3(S)FAc(S))+FD(S)F_(s)F3(s)F4(S)FAc(S)FM(S) ^ - Zo(S): io(s)
These
1 + GT(S)
control-loop
be examined
dependent
in detail
characteristics
in the following
-84-
of switching
chapters.
regulators
will
(e-3)
CHAPTER 9 ADAPTIVE
_rl
CONTROL -
..AdaptiveControl The control
example,
properly
the complex
power stage [12]. it will
to sense filter cellation.
parameter
changes
the loop is opened
multiple
converter
feedback
terminal
transfer
pole-zero
function.
paths.
Since
one
the
the loop should
be
It is for this reason
of the op-amp
function
loops,
can-
integrator
as shown
GT(S) for the buck converter
can
as
where the term
involving
Substituting
into Equation
FMFD GT(S) -
Fl has been omitted
the circuit
Cl
expression
since,
(9-I)
for the buck converter,
for F's in Table
R4
RL(RcCS+I )
(RL+R C)C +l Ry RL(RcCS+I )
Rx+R 3 g
Let
-85-
Fl=O.
8.1 of the previous
1
R_ + sL + (RL+Rc)CS+ l
Ry =
+ FDC (s))
(9-I),
nLs
where
loop has the ability
provide
paths,
GT(S) : FM(S)FD(S)Fp(S)(_(s)F3(s)FAc(s)
chapter
filter of the
nature of the control transfer
zero to
as an illustrative
that the control
to all the feedback
The open-loop
the complex
by the low-pa_s
and automatically
open-loop
at the output
can provide
a buck
such an adaptive
contains
open at a place common
be expressed
pole presented Employing
the regulator
control
in Fig. 9.1.
designed
be shown mathematically
To examine
can investigate regulator
Basic Concept
loops when
cancel completely converter
BASIC CONCEPT AND IMPLEMENTATION
(9-2)
A
Zp
F! ^
d(S) FD
Fp
F,
F2
1
!
1
!
l
I
I
1
1
i
N
1
I 1
I
I
I I
I
'
I
1
I I
I
I I I I
!
DUTY CYCLE MODULATOR
•,-. ..., l
ANALOG ERROR PROCESSOR FIG,
9.I
OPEN
-86-
LOOP
GAIN,
Equation
(9-2) can be simplified
FMFD
as follows:
_a (RL+Rc)
LCs2 +(_ + RLRcC)
s + RL (9-3)
GT(S) =
if
CiRy
'(RL+Rc)LCs2 + [L + RLRcC
+ Rc(RL+Rc)C]
s + RL + RC
_=I
FMF D GT(S ) =
(RL+Rc)
LCs 2 + (L+RLRcC)
s + RL (9-4)
sCiRy (-RL+Rc)LCs2
The above equation
+ [L + RLRcC + R_(RL_Rc)C]
can be further
simplified
by assuming
s + RL + R_
R L >> R_ and
RL >> RC
FMFD
LCs2 +[R_
+ RcC] s + l
GT(S)
Examining
(9-5) sCiRy LCS2'+[R_
(9-5) it is obvious
provided
by the low-pass
provided
by the two feedback
dc loop resistance
is met,
cal except
filter
in the power
loops.
the numerator
stage and the complex
The control
understanding
damping
constant
of the open-loop
parameters,
namely
such that _ = I.
is
zero
R4, and the turn-ratio
and denominator
lower
+ I
pole in the denominator
transformer, can be designed
for a slightly
a qualitative
that the complex
Ry, the ac loop resistance
the ac loop sensing condition
+ RcC + R_CIs
is
the n of
When
this
of (9-5) are almost
identi-
in the numerator.
To get-
transfer
characteristic,
one
L' can assume later.
that RcC > 1 and RL >> RC and R_ negligibly
(9-15) can be simplified
z (s) :
caused
impedance
Fig. 9.7 with
impedance
tics.
o
in output voltage
to read:
+ I)
(9-16)
LCs 2 + (--_-+ RcC)s
+ 1
L
-98-
o:: 0 I-_1
LI.I
U _D
._1 ._1 0 n_ I-Z 0 I
0
I--
e_ I-U
-r
UJ Z ,
>L/(a_)
1
(9-21)
achieved
term(RcCS+l)/(R5C2s+l)
eq. of
+
in
grossly Using
the
above
(9-20)
design
of
Detailed
then
In
(9-20)
fact
together
the
is not
discussion
assumption
is
stage.
numerator
violated.
the
Equation
in the
effect
significant
is included
with
the
of
if
in Volume
approximation
simplified. 2
FMF D GT(S)
i
= sCiRy
LC s a
2
Figure
loop zeros
9.11(a)
gain
of
are
equation
smaller
complex for
complete
pole
zeros
eventually
next
few
to
can
pass
the
be
chapters,
+
R£C
is
When
reshaped
+
RcC ) s +
1
can
complex
is be
but
desirable
and
separated
by
the
zeros
obtained
to as
Further reasons
to design
the
the
note
increase stated
term
The
is in
that
locus
the
open
complex
poles
loop lines
the
of
loop.
from
heavy
interesting
For
-108-
poles
a R5C 2 compensation
poles.
zeros.
the
R5C 2 compensation
as shown It
real
of
the poles
ratio.
the
to two
locations
complex
cancellation
it
(9-22)
(_
+
without
T z2"
through
result
the
(9-5)
increasing zero
a
(Ry + R5)C 2
damping
zeros
9-11(b)
plex
=
illustrates
adjacent
somewhat the
rz2
+
L
LC s
where
+ a_z2S
by
added, Figur 9
the
of
the
com-
of
Tz2
will
below
a
and
in the
(Ry + Rs)C 2 so
that
II
, #
uJ Z .J O. I t_
I I I I
2, 0
I
--
uJ Z Q. I o3
,--4
c_
_L
-109-
the
second-order
zeros
but
two
terms
in
negative
Equation
(9-22)
real can
KI
the
numerator
can no
longer
produce
complex
zeros.
be
simplified
(s + Sol)(S
using
the
following
notations
+ So2) (9-23)
GT(S ) = -_- (S2
2V I K 1 = -_,
where
_n
Sol
and
+ 2_2mns
_2
are
+ ,,,n 2)
defined
2L----C{C*_z2 + [(_Tz
in
equation
(9-ii),
and
- 4c_LC]½} (9-24)
=
So2
It
is
shown
selected
in (9-24)that
by
asymptotic meter the
varying curves
Sol open
Bear
for
gain that
range
gain
can
be
gain
is
less
when
only
in
open-loop
the
9.13
The
Fig.
except
the
of
third
increasing
the
is
Sol
low
frequency
range
provides
converter
a third
=
can
with
shows
the
control
dotted a
line
equal
improve
gain
in
the
in Fig.
that
shown
the para-
represents
to unity.
to
For Sol
arbitrarily
9.12
is
shown
i0 w n •
of
be
con-
particular
9.12
= _n'
that the
as the
larger
loop
dotted
curve
employed.
operated
loop
The
loop
than
experimental
is
function
and
clearly
zeros Figure
open-loop
employing
were
a
third
by
loops
as
loop
the
It
two
1 - _ _n.
So2
of
the
parameters.
gain
chosen
interest.
feedback
system•
9.5
of
loop
objective
by
obtained
two
Figure
the
the
magnitude
control
without
performances
frequency
the
the of
[(STz2)2 - 4sLC]½}
a arbitrarily
loop
in mind
verter
i 2L----C{_Tz2
at
verification a condition
is employed
-110o
with
of same
R 5 = 500
the as
three that
ohms,
loop
shown
in
C2 = 0.01
uF.
0
o
o
O LU N
'1'I,-U= O 00
.=1 >
C
:3 3
I.-Z 1.1.1 t-,,' I.LI LIU-
>..
#
/
Z L_
O LI-
0
Z O
LL
I'-7
t_ ,,I I.IZ
I-" n O O J
0. O
C'4
I
I
I
o
o
i cslZgl: [sQ]3anJ.n,_v -III-
I o
0-4
LI-
Comparing
Fig.
9.13
with
Fig.
the
loop
gain
reduction
eliminated matched
resonant
zeros
of
the
two-loop
Figure system
Fig. in
at
9.14
above
current
gain
From
the
at
control
a velocity output
the
or
loop Figure
are
peaking
illustrated (9-13)
are
of rate
of
control the
is
has
from
un-
poles
and
as
the
a RC
it
the
is
adverse
often
of
is generally
sufficiently
control-loop
change
the 9.10. to
of
as the
load-transient three-loop
higher
large
of
referred
the
the
for
in Fig.
converter
aspect
converter
effect
reduction
senses
of
the gain
zeros
is
in
demonstrated
open-loop the
three-loop
shown
improves
complex
because
that
a sharp
loop
the
clearly
only
eliminates
important
margin
as
of
as
dependent
than shown
system the
is
two --
in the
performances
optimized. other
shows
regulator
the
into
in
and
the
asymptotic
two
9.6.
performance
impedance
the
observed
in Fig.
loop
complex
been
not
improvement
illustrated
converted
the
converter
frequency
output
also
such
Another
phase
are
Since
effect
the
it also
Therefore
9.15
acteristics.
increasing
crossover
results.
RC
results
same
has
R5C 2 loop
view,
audiosusceptibillty, third
loop
point
the
Improvement
R5C 2
of
system
converter
the
frequency
loop
the
function
condition
resonant
open-loop
of
transfer
sho_
the
the
ratio
operation
that
that
otherwise
current
is expected.
of
damping
The
of
response
previous
of
Therefore,
and
which
operating
operation,
control
voltage.
is shown
open-loop
illustration.
discontinuous
loop
the
advantage
by means
continuous
it
system.
shows
The
performance
for
and
a discontinuos
9.10.
the
frequency
9.5,
loop shown
Employing two
real
transient
response
such
as
employing
the
following. curves
control as
characteristics
of
the
provides
the
dotted
the
R5C 2 loop
poles
as
-112-
audiosusceptibility
complex
curve
shown
the in
of
poles Fig.
two Eq.
in GA(S) , a
9.15(a)
complex (9-25)
char-
and
poles and
also of
Eq.
illustrated
Z 0 In,, 1,4J a.. 0 l-Z uJ
U u) O Z
Z O U l o. O O ,J Z O p--G
,.=,
Z 14J D, S" O U
l--
tJ p-bO
IJJ I-" tJ iv,
(J 0. O O ._J
I.U D.. O h_
I
8
._
I
o
1
._
I
I
I
1
o
o
o
o
0 N I
J($)J'9 j - 3Onll7dlAlV
-113-
='0 m
i
m m
n
=-
J
-114-
rl
g
0 0 .J Z 0
Z n O L_ v
ill "r I-0 I-3;
_J _rj (._
g
r_ IiU I-L) n.,-
0
•_U
..j
>-
0
'-_
I---
•--4
(/)
I--
LIJ Q.
LU (..)
0 U LLI
v
I-0 ::3
Lr_
i, (3
-115-
,--
in
the
dotted
curve
of
Fig.
9.15(b).
RcCS
+ 1
DMs
(9-25)
GA(S) 2Vla
Experimental
diction
of
employed shown
measurement
GA(S)
of
when The
output
approximated
in
Fig.
compared
with
the
impedance
measurement
= LC_ -_
transient
The
two
+
with
much
cases
Significant
are
again
demonstrated
values
same
characteristic
pre-
as
that
is
discussed.
the
three-loop
system
is
of
L RcC ) s +
_
+
the
output
due
to
step
improvement
of
with
the
change
these
two
three-loop
one
can
conclude
in the
two
loop
adaptation
is
be
illustrated
by
the filter
achieved
by
same
zeros
Fig.
as
parameter
changes,
the
amount.
However,
when
a function
of
change (tracking
as of
zeros
with
that
two
two the
the
respect
-116-
illustrated
performance
Control
control
the
are
and
the in
Fig.
9.17
characterisitcs
implementation.
the Three-Loop
9.19(a):
characterisitc
load
Eq.
(9-5),
i
impedance
Examining
adaptation
theoretical
(9-26)
of
the
improved
of
Adaptation
the
the
parameter
previously
Parameter
poles
with
I)
(
response
9.18.
of
9.16
characteristic
+
results
and
9.5
together
by
Zo(S)
outout
Fig.
9.13.
Ls(RcCS
The
s + i
is presented
(9-25)
in measuring
_z2
L--_Cs2+
an
third
control
almost
system.
complex
complex
Regulator perfect This
poles zeros
loop
of
can
are
can
perturbed
the motions
employeed,
parameter
to poles)
adaptation
GT(S)
track
is
parameter
aTz2. remain
the
of
positions
Pole-zero almost
the
linear
-
I
i
i
|
I
I
D.. O O ._I
I
Z -E
OCn
_
(,h
P,u_
-rw
-i- uJ
=w
,
*
.
>-_
I0 ,.
t3:) /
c_ z, ILl
-
=E O U
;0
uJ "r I=-
_I,o ..I I
_
I--
m-
IN :3 O "t" I--
/_
"n-
i...e
-r I--
0i'
i --
3I: f./) U
8
I-.
i.i.I I'l.i.
no (J >I-.J N
I--
Oo\_
_
0\
ILl U
D_
O_
O
,-'t
c_
Z 0
N
(3 u.
I
I
I
I
I
I
I
_
O
_
O
m
O
m
-
-
'
T
Ivy!) °z I _0-I oz, [e0] 30n.Lnd_V -ll7-
T
,,,
O N NO
,
G.. 0 0 .=J Z 0 I-¢.0 Z I.U O ¢J Lid "I" I'-I-_) 0 -r I--
Z "r I--
¢/) ¢J I-_0 n,UJ l*-" L) .¢ ne -r tJ ILl CJ Z UJ
I'=I'0
,--I
D=*e
lJ 0 N
0
Ln
0
_n |
0 _
I
Itmr)0z190n0z--[ea] _an.Lnd_v -1'18-
in
o
I
N I
(1)
WITHOUT
COMPENSATION
LOOP
'i ....-: .__'_
o_=1
.....
cx = 0,355
(2) WITH
COMPENSATION
LOOP
c_ = 0,355
VERTICAL HORIZONTAL
FIG,
9,18
SCALE
:
SCALE'
OUTPUT STEP
0.1 V/DIV, 1 MSEC/DIV,
VOLTAGE LOAD
CHANGE
TRANSIENT RL. =
-I19-
10
RESPONSE
DUE
TO
OHMS
11
OHMS,
A
S
-
PLANE
.,,lip r
COMPLETE
PARAMETER
ADAPTATION
S -
PLANE
v
(a)
PERFORMANCE
OPTIMIZATION
I
JWo/l-_ 2 S C
"
C)
-
PLANE
w
i.._ _
- aW2Tz2
-Tz2 (b)
FIG,
9,19
(a)
COMPLETE
PARAMETER
PARAMETER ADAPTATION
PERFORMANCES,
-120-
ADAPTATION TO
OPTIMIZE
(b)
PARTIAL
REGULATOR
as
long
as
the
zeros
are
sufficiently
close
to the
poles,
that
is,
L as
long
as
It was
=
indicated
desirable
two
_Z2
_
earlier
to have
real
zeros
simplified
to
+ R£C
two
are
+ RcC
that
real
in
for
zeros
sufficiently
the
better
far
of
apart,
equation
(9-22).
performances
a complex
equation
pair.
(9-24)
it
If
can
is
the
be
read:
sOl
_
_Tz2 Wo
So"z
_
1 -Tz2
is shown
of
regulator
instead
2
It
numerator
in
the
2 where
_
1
o
(9-27)
= L--C
(9-28)
above
two
equations
that
s02
is no
longer
a
function
of
2 output
filter
parameters,
yet
So1
is
proportional
to
_o
"
When
the
a function
of
complex
2 poles
vary
proportional
illustrated does the of
not auto
the
increase
in
Fig.
zero
The
imply
a drawback
compensation
the
the
9.19(b).
necessarily
zeros
to Wo,
in many stability
nature. practical margin
As
varies
nonlinear of
the
-121-
is
system.
as
parameter
the
discussed
concerns of
s01
adaptation,
stability later
often
in in
the
i0,
direction
as
however,
characteristic Chapter
_o
or
the to
movement
CHAPTER SCM-CONTROLLED
In this chapter,
Bode
loop gain and phase. should be performed Figure 9.1 that
blocks
detailed
performance
lO.l
By opening transfer
function
is employed control
by X, the open-loop
Using
can then be expressed the detailed
are given
GT(S ) =
FM.
function
ample
from
By opening based
on the
function,
in terms of circuit
the
parameters.
reveal how the various
stability
at the conclusion
margin.
Sample
of the chapter.
Function.
by "X", the open-loop
becomes:
FM[FAc
F3 Fl + FpFD(FDc
+ F3 F2 FAC)]
The transfer
function
is applicable
Substituting
contents
of Table 8-I into(lO-l),
functions
It is clear
this transfer
equations
to achieve
paths.
transfer
the open-
the "loop-opening"
the block
the loop in Figure 9.1 at a place marked
function
to investigate
system,
is the path containing
should be designed
Transfer
ANALYSIS
to all feedback
of Figure 9.1 is obtained.
characteristics
Open-Loop
technique
at a place common
to simplification,
SCM parameters
STABILITY
For a multiple-loop
such a place
transfer
Subsequent
REGULATOR
analysis
the loop at a point marked various
I0
GT(S ) can be derived
to all three
(lO-l)
power stages.
the open-loop
in terms of detailed
circuit
transfer parameters:
For buck power stage:
1 + sC2(Ry VI GT(S ) : FM SClRy
2 (i+
c)
+ R5) sL el+scRL] I+ C2R s +mTL j (I0-2)
s2 + 2_oS
-122-
+ _02
For ,boost power staqe: 2 v]
SLED'
+
GT(S)= _.SCIR(O,)ZmR L
0
s2 + 2_oS
2 (] " +
Req + SLe) RL •
0
{LeOl JSRcC (I0'3)
+
For buck-boost
mR L
+
(Ry + R5)C 2 i + sR5C 2
s + 1 + sR5C 2 1 + SRcC ]
power stage:
2 NS sCIRyVI(D'')2 I sDD'Le GT(S) = FM'N-P-P mRL
_ +_o2_%s + s2
+ _ 2 -(l
- D ReqRL+ SLe) .
0
(I0-4)
Is2D[LeO 1 I1"SC sCRc 1 +
m%
_+ mRL
C2(Ry
+ R5)
1 + sC2R 5
s +
1 + sC2R 5
In these three equations,
R4 m
-
(Io-5)
nRy
b
: (R3 + Rx)/g'
R
: x
g
(Io-6)
R 1R2 R"1 + R2
'
= Rx/R 1
-123-
2_ ° = I/(CR L) + (Re + Rce)/L e
(repeat
of(5-50) )
(repeat
of(5-51))
Re = R_
Le = L
:
buck (repeat
of (5-34))
Rce = Rc
I * Req
Re
Re = R_/(D') 2 Le = L/(D') 2
:
boost
Rce = Rc/D'
(repeat
of (5-35))
(repeat
of(5-36))
* Req : Re + Rc(D/D') Re = Rs/(D') 2
Le = Ls/(D')2
Rce=
:
buck-boost
Rc/D'
* Req : Re + Rc(D/D')
*Equations
for Req are repeat
of
(5-53),
-124-
Notice control
10.2
that FM is left intact
so that eqs. (I0-2) to (I0-4) are applicable
laws.
S.implification of Open-Loop
It can be i_ediately provide
concise
meter.
However,
recognized
analytical
Transfer
Functions
that eqs. (lO-2) to (lO-4) are too complex
comprehension
these equations
to adopt a design
of the effect
can be simplified
of each control
considerably
to
para-
if one chooses
such that:
C2R 5 : CR C
Making
to all
: _Pl
use of the equation
(10-7)
(I0-7), equations
(I0-2) to (I0-4) can be shown
to reduce to the following:
FMV I
ms2 + s_ o 2[ C2R>, + C2R5+ _
Le] + _o 2 m-RL' buck
GT(S) = sC l Ry
s2 + 2_ mo s
+ mo 2
I-
Req + sLe RL
GT(S) =
FM VI SCl(D,)2Ry
I
sD' Le mR L
(lO-3A)
÷
• s2+ 2_moS
l-D NS FM Vl Np SCl( D, 2Ry
) + too21 I
Req + sLe
I sDD'Le RL mRL -- + s2 + 2;=os
D'Le
-125-
boost
+_o 2
s2D D'Le l--i_--+S_o2 (C2R5+ C2Ry+ mR L
GT(s) =
(IO-2A)
(lO-4A)
+ =o 2
1
buck/boost
It will
be
shown in Volume
(lO-2A) through dicting
II that
(lO-4A) still
regulator
apply
small-signal
To search for commonality
if (I0-7) is not grossly to a good approximation
violated, in pre-
performances.
among
these
three
equations,
one notices
that
if one defines
: buck
: m : R4/(nRy)
: boost
: m/D' : R4/(D'nRy)
: m/D'
The three transfer
(Io-8)
: buck boost
: R4/(D'nRy)
functions
become:
FM VI GT(S) - sC 1 Ry I
(I0-2B) :R L
s2+2:moS+mo2
o buck
l-
R
eq
+ sL e
FMV
GT(S),"
ISLe RL I _TL + sC1 (D')2Ry s2+2_'.oS+,,'o 2
[S2+s,_o2(C2Ry+C2R5+
Le)+m 211 _R L o
(IO-3B)
boost
sDL e
l D -
R + sL eq e RL (lO-4B)
GT(S):
NS FMV I Np sCl(D,)2Ry
I:RL
+ s2--+2_oS----+mo---2
buck/boost
-126-
In terms of control-loop analysis, results shown in (IO-2B) to (IO-4B) are sufficient as they express explicitly the open-loop transfer functions for all three regulators. However, an earlier stated objective for this program is that the analytical results are to be used as basis for the generation of concise design guidelines. Such an endeavor can only be achieved if eqs. (lO-3B) and(lO-4B) can be further reduced into the form exhibited by_O-2B), i.e., for all equations to exhibit the following form: 2 GT(S)
where
=
1 1
K2s
s K1
s2 + 2_Wo s + wo2
Kl to K4 are constants.
lines for selecting small-signal
10.2.1
+ K3s + K4
(10-9)
By so doing,
all constants
one can then contemplate
k's to achieve
desired
stability
guideand other
performances.
Open-Log P Transfer
Function
of An SCM-Controlled
Buck Regulator
Defining
"z2 _
C2(Ry + R5) + Le/(DRL)
the buck-regulator
open-loop
_
C2(Ry
transfer
(io-Io)
+ R5)
function
of (IO.2B) takes
the following
form:
i FMVl
s? _-- + SWo2T_2
s CiRy
2
+ _o 2
GT(S ) -
I0.2.2
Open-Loop
By defining
Transfer
the following
(io-II)
+ 2{_o s + Wo2
Function
of An SCM-Controlled
indentities; -127-
Boost
Regulator
l
l
II
"
[eC2 (R5+
_
+ 2_w° RL Le
Ry ) +
_L ]
_LL Le _o 2
Al l
l
(A l - A2eTZ2)
(]o-12)
or :-i
(I0-13)
+ A2 _" _Z2
O{'
(I0-14) Req
2_ o Le
Le _o)2
A1 = 1 -
(io-15) A2=
!
CL
RLC
(lO-16)
C& 7.
A1 -
A2 _TZ2
Leq
Req)
+
functions
for the boost
(lO-17)
Le
._~C2(R 5 + Ry) - _Z2
The open-loop
transfer
to the following
form, assuming
regulator
can be reduced
Req Z
i
tJJ
0i
0 LU -r" F'!
_D
z 0 0c ILl I-.._
>-Z ._.J
tL F"m 0.. Z
(_ r,U_
UJ '-r hc.> U0
j-to
tO n_ U,J uJ L_U_
i
n,UJ -I- "r F'-
f,,,, \\
I
\\ \
u..
,
\
O0"O9-
-195-
O0 "OL'C)
an
input
filter.
Some to
alleviate
regulator
If in
basic
this
design
the
constraints
detrimental
are
effect
of
presented
in Volume
II of
the
filter
switching
input
on
the
report
performances.
the
reader
chapter,
desires consult
further reference
information [17].
-196-
on
the material
contained
MODELING IN
The
mf
models
dwells Fig. circuit
mode
a
of
time
the
power
switch
is
on
the
power
switch
is
off
when
both
restricted
power
to
Tf2
does
the
cycle.
not
exist,
and
by
a
linearized
average
In
5,
employing
the
the
average
the
averaging
The
two-winding
example.
the and
is
diode
2).
of
to
Tf2
are
off.
remains
an
approach in
time
when
time the
time
Mode
i
is
interval
uniform which
canonical
regulators
state-space
were
the
other
is two
the
Mode
throughout is
capable
and
Mode
Mode
are
as
converter
stage
2
by
operation,
derived
topology
chosen
power
i Operation
For
with
converter
for
for
regulators
conjunction
buck/boo_
for
technique.
SCM-controlled in
models
derived
averaging
for
results
circuit
using
manipulation. an
illustrative
types
are
also
summarized.
It are
should
derived
regulator Recall Mode and
here
the
operation
utilization
component
noted to
that
permit
characteristics that
2
be
stress
of
and
the
2
larger
model from
rather output
for
investigation
different is
models
discontinuous
regulator
quite
Mode
average
analytical in
switching are
the
-197-
of
2
operation
the
switching
operation.
characteristics
that
limited. ripples,
of
mode and
Mode
of
Mode
Because the
authors
1
for operation
of
the
feel
when time
converter
the
both
in
certain
the
the
mmf,
system
operating
a
represents
If
and
different
the
and
the
zero
three
represents
inductor
chapters.
demonstrated
exist
on,
presented
regulators
is
represents
continuous
has
It
Tfl
is
continuous
to
corresponding Ton
a
previous
off,
diode
order
in
reduces
there
interval
the
at
(Mode
each
diode
the
mmf
operation,
stage,
the
in
inductor
cycle
time
[i0]
techniques
The
a
operating
model.
the
models
the
of
power
the
Cuk
basic
of
and
switching
Chapter
if
cycle
only
Recently
three
valid
and
representing
the
presented
been
The
of
of
have
switch
operate
OPERATION
I)
interval.
the
MMF
regulators
the
specified
REGULATORS
switching
one
topologies
INDUCTOR
fraction
during
SWITCHING
of
longer
for
that
OF
(Mode
no
zero
3.1
ANALYSIS
models
are
at
14
DISCONTINUOUS
average
inductor The
AND
CHAPTER
higher that
it
2
is impractical to extend the SCMdesign guideline to include Mode2 operation. It is recognized, however, that the regulator performance characteristics and stability margins are usually improved instead of deteriorated in Mode2 comparedover that of ModeI. For design purpose and worst case consideration, the Mode2 operation can be generally ignored. The SCMdesign guidelines to be presented in Volume II of the report are constrained to only Model operation. It is intended that the analytical models presented in this chapter be used only for the purpose of analyzing the regulator characteristics in Mode2 operation. 14.1
Power Stage Model The average
the discontinuous the canonical model
of the Buck/Boost
model for the three
circuit
form
shown
a state variable
The input of Figure
summarized
only.
14.1.
It should
be noted
operating
possesses
reduces
for the canonical basic power
in
circuit
mmf no longer
to zero at the
the free boundary to include
MMF
in
This canonical
The inductor
it always
in Table 14.l for the three
operation. cance
values
Discontinuous
by Cbk (lO), and expressed
14.l has been modified
Parameter
with
power stages
in Figure
since
end of each cycle and no ]onger
input filter.
basic
mmf mode were derived
is seen to be of first order
constitutes
Converter
properties.
the effect of the
circuit stages
that the letter M carries
model
are
in Mode 2 a new signifi-
in this chapter. Since the canonical
model
boost power stage in reference discussed
in chapter
two-winding for elements
was derived
lO, the circuit
13 was used to derive
buck/boost
and a single-winding
topology
manipulation
an equivalence buck/boost.
buck/
between
buck/boost
from the earlier
effort.
through
modeling
power
These
expressions
14.3 along with expressions
-198-
stage were
the
The expressions
Jl' rl' gl' J2' r2' g2' M, and K in the canonical
model for the two-winding
eq.14.1
for a single-winding
readily
circuit obtained
are listed
for Z(s) and H(s).
in
tJ"1--
la;I
la-N
I.L N
N
N
! _',J
I r--"
t'a_" v
DO .--J
tt N
F--
.-J o"
_r I r-"
(_) --J C-)
Z Q P-4
0
tt
i
"¢
I
0 kO -T-
C,J
O O
kl_
I:
ko ..J
_¢
,,¢_II
,,i
_Y
c C_ A
,,(_ II
r-W -J
r-.r--j t'_
tI
_J e-
F--
_0
-199-
b_
Z m
fr bJ i-w
,-I