Implementation and Simulation of IIR Digital Filters in FPGA Using MatLab System Generator Edilberto Carlos Vivas González Departamento de Ingeniería Mecánica Universidad Libre Bogotá, Colombia
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Diego Mauricio Rivera Pinzón
Edwar Jacinto Gómez
Departamento de Tecnología Universidad Pedagógica Nacional Bogotá, Colombia
[email protected]
Departamento de Tecnología en Electrónica Universidad Distrital F. J. C. Bogotá, Colombia
[email protected]
Abstract— This article shows a procedure for IIR digital filters implementation using MatLab System Generator for testing and verification of results. In this particular case, the IIR filters are expressed in a State-Space representation, and the coefficients of the filter matrix are given in a fixed point format. This procedure aims to make implementations on devices with finite accuracy. Thus, the implementation is done using a state equation model with balanced realizations because of its numerical properties. The balanced forms exhibit low sensitivity to parameter variations, and avoid, to some extent, the numeric overflow. A user interface is designed in order to enter the filter transfer function or the filter state equation, and it automatically generates the VHDL language in a standard format compatible with the format used in a Black Box object of the System Generator. In this work, a 4th order lowpass Butterworth filter was implemented as an example of the methodology in a Xilinx FPGA device. The practical results obtained are shown. Keywords: FPGA, State-Space representation, Fixed-Point notation, digital filters, MatLab System Generator
I.
INTRODUCTION
A Field Programmable Gate Array (FPGA) is a device with appropriate characteristics for the implementation of digital filters due to the fact that the basic logic cells allow the implementation of adders and therefore, multipliers in a reduced way. Furthermore, the compilers and synthesizers optimize the implementation of multiplications by constants both in size and in speed [6][11][12]. Due to the high density of the hatches with which a FPGA consists of, it is possible to implement very complex digital systems, among which the digital filtering and the fact that when working with programmable logic, it is possible to make modifications in anytime without this implying great alterations in the hardware system [8]. These programmable logic devices allow the execution of mathematic operations in a parallel form; most of the implementations are made in a direct form II-T or another similar methodology, which can be either using a MAC type architecture or simply by using the LUTs in order to make multiplications and distributed additions; thanks to its parallelism the matrix implementations can be made in the same clock cycle in a distributed way [4]. This paper presents an equation to estimate the number of bits of the registers of the equation of state without generating a numerical overflow. Additionally, this work lets easily implement multivariable digital controllers and filters such as 978‐1‐4799‐6839‐8/14/$31.00 ©2014 IEEE
[15] [16] [17] [18], because it automatically generate VHDL code usable in a Black Box block of the system generator toolbox, which enables simulations in MatLab and implementations in programmable logic devices. The whole process is automatic and scalable to more complex designs. This paper is organized as follows: Initially, the representation of the IIR filters in state-variable is shown, the representation allows balanced realizations. Its advantage is to produce coefficient values near to each other, which reduces the errors of numeric representation when working with a fixedpoint notation. Next, the necessary steps for filters subsequent implementation are shown, in terms of the system numeric representation, the quantity of used bits in the truncation, and rounding algorithms appropriate to minimize possible numeric errors. Finally, the implementation is shown using MatLab’s System Generator tool and the verification of the benefits of implementation in state equation. II.
DIGITTAL FILTER IMPLEMENTATION
A. IIR Filters An IIR filter is defined through the equation 1. Where the constants ak y bk are the filter coefficients [1][2]. y (n) b0 x(n) b1 x(n 1) b2 x(n 2) ...bM x(n M ) a1 y (n 1) a2 y (n 2) ....a N y (n N ) ,
(1)
The implementation of IIR filters can be made in different ways; for example, the Direct Form I and Direct Form II. However, a better performance is obtained by carrying the transfer function to a State Equation Representation, because this allows to minimize the errors by numeric representation of the coefficients when making balanced executions. Nevertheless, the coefficients of the realization are generally not zero, which implies an increase in the number of operations, and therefore, the use of resources in the digital device [11] [12] [13] [14]. A system has infinite representations by choosing a different set of state variables; Fig. 1 shows the implementation of IIR filters based in the equation (2). X ( K 1) A. X ( K ) B.U ( K ) Y ( K ) C. X ( K ) D.U ( K )
(2)
The choice of the number of bits of the integer part (m bits) is obtained from the magnitude of the integer part of the larger coefficient (|𝑐𝑜𝑒𝑓|) of all the matrices of the state equation where 𝑚 bits is equal to (𝑙𝑜𝑔2 (|𝑐𝑜𝑒𝑓|) + 1), and 𝑙𝑜𝑔2 (|𝑐𝑜𝑒𝑓|) is round to nearest integer. D. size of the registers in IIR filters Figure 1. Implementation of IIR filters by state equation using Simulink.
B. Balanced Realizations Balanced forms are useful because of their low sensitivity in implementations in finite precision devices [1] [2] [3]. Calculating the balanced form is as follows: a system K = [A, B, C, D], Wc the Controllability Gramian and WO the Observability Gramian, also if A is stable, there is a solution to equation 3 and equation 4 if and only if K is controllable and observable. 𝐴𝑊𝑐 + 𝑊𝑐 𝐴′ = −𝐵. 𝐵′
(3)
𝐴′𝑊𝑜 + 𝑊𝑜 𝐴 = −𝐶. 𝐶 ′
(4)
And there is a transformation T such that WO= Wc the observability and Controllability Gramian are equal and is given by equations 5 and equation 6. 𝑊𝑐 = ∑ = ∑−1/2 𝑈′(𝑅′)−1 𝑊𝑐 𝑅−1 𝑈∑1/2 (5) 𝑊𝑜 = ∑ = ∑1/2 𝑈′𝑅𝑊𝑜 𝑅′𝑈∑−1/2
When digital filters are implemented, is necessary to determine the number of bits of the analog-digital and digitalanalog converters, based on the required resolution and the reference voltages (Vref) of the converters. Normally, the converters work with a single source, through which a signal condition the circuit that is in charge of mounting the input signal over a level DC = Vref /2 [1] [4] [5]. The number of bits N of the analog-digital converter is necessary to determine the minimum size of the registers that the state variables X (K ) save and the output Y (K ) . The main problem in the filter implementing is when numeric overflow occurs, because some results are larger than the maximum value that can be represented. Then it is necessary to ensure that any operation must be representable with the number of bits available to represent the state vector X (K ) and output Y (K). For a normalized input in the range [-1 1] the H infinity norm is higher than the absolute value of the sum of the respective channel gains. Using the H infinity norm of the system matrix equations 7, the size of the registers X (K) and Y (k) is determined using equation 8.
(6) 𝛾𝐷 = ‖𝐷‖∞
𝛾𝐶 = ‖𝐶‖∞
𝛾𝐴 = ‖𝐴‖∞ 𝛾𝐵 = ‖𝐵‖∞
(7)
C. Fixed-Point Representation 𝑠𝑖𝑧𝑒𝑋,𝑌 = 𝑙𝑜𝑔2 ((𝛾𝐶 . (𝛾𝐴 . (𝛾𝐴 + 𝛾𝐵 ) + 𝛾𝐵 ) + 𝛾𝐷 )(2𝑁 )(𝑛 + 𝑛𝑢 )) (8)
For the representation of numbers in fixed-point, “m” number of bits of a binary word for magnitude (whole part) are taken, and “f” number of bits for the fractional part; the bit MSB is the sign bit and the number is found in complement to two [1] [4] [5]. For example: 110 01,000000 Fixed po int 2 6 binary 64binary
Notice that in the fixed-point representation what is actually done is multiplying the decimal number for 2f; then once the arithmetic operations have been made, it is necessary to divide the result into 2f, which is simply to move the word 𝑓 bits to the right, or to move the least significant 𝑓 bits. The coefficients are represented in fixed-point notation. Figure 2 shows the representation in fixed-point.
m bits
Where N is the number of bits of the A / D input signal, n is the order of the filter and 𝑛𝑢 is the number of input signals of the filter if there is multiple inputs. The result is round to nearest integer.
Stacking of the input register.
The input signal to the filter is N bits (output of the analogdigital converter), but it must have the same size of the registers of the state variables X (K ) in order to add AX(K)+BU(K), because each product should give the same number of bits in order to be added; then the input signal is stacked with a certain number of bits to the left in order for it to stay in M bits (the same as the size of X (K ) ) and in that way be able to form the register U (K ) [3]. Figure 3 shows the organization of U(K).
f bits
Figure 2. Representation in a fixed-point
Stacked bits.
0
0
N bits of ADC
1
0
0
0
Figure 3. Register U(K)
0
0
E. Truncation of the registers
III.
COMPARISON OF PROGRAMMING FORMS OF DIGITAL FILTERS
In the representation of a state equation, the coefficients of the matrices are multiplied for X(K) and U(K). The coefficients are represented in fixed-point notation with a certain number of bits (Q) in accordance with the required accuracy. When making multiplications among binary numbers, the size of the register that stores the result of the operation must be the same as the addition of the number of bits of the coefficients and the number of bits of the registers for X(K) [1] [4] [5]. In order to obtain X(K) and X(K+1), the delay is created with a shift register (D Flip Flop), it is, the size of the registers in the input and the output of the shift register must be the same; then, the truncation consists of taking the result of the operation X(K+1) = AX(K)+BU(K) and discarding the least significant bits of the word.
The result of the simulation of a 4th order low-pass Butterworth filter is shown, the specifications of the filter are: Sample rate = 5000Hz, Cutoff frequency = 500Hz and Gain = 2. Unit step response of the deployed filter in direct form I, form II and in direct state equation with a balanced realization was simulated. The filter coefficients are represented in fixedpoint numbers with a word-length of 8-bits, 6 fractional bits, 1 integer bit and 1 sign bit. Fig 5 shows that the direct form I and direct form II implementations have a gain error of 37.5%, due to numerical error committed, while the state equation implementation has a gain error of 2.5% (Fig 5).
As in the representation in a fixed-point, it is necessary to multiply the coefficients for 2𝑓 , the result must be divided into 2𝑓 ; it is, the bits that have to be discarded are the least significant 𝑓 bits of the word, which is equivalent to dividing into 2𝑓 ; these bits can be discarding or make a displacement to the right of 𝑓 bits (Fig. 4).
Figure 4. Truncation of the registers.
The output 𝑌[𝐾] = 𝐶. 𝑋[𝐾] + 𝐷. 𝑈[𝐾] also needs to be truncated, the least significant 𝑓 bits of the word are also discarded, and the result is the next M bits. Figure 5. Step Response of 4th order low-pass Butterworth filter with fixed point coefficients.
F. Rounding When truncating, what is being done is a division; for instance when 1 is divided into 2 the theoretical result is 0.5. We already know that in order to divide into two we move a place to the right, which makes that when moving the “1” in its binary form the result is zero, but actually its necessary to approximate the result to one, because the theoretical result is 0.5 and in digital, when it is over 0.5, it is approximated to the closest greater whole number, and under 0.5 it is approximated to the closest lower whole number.
In fig 6 frequency response of each form of programming is shown; note that programming in state equation is the one with the lowest error of magnitude with respect to the ideal frequency response, because the matrices coefficients are close to each other, and therefore, more accuracy is obtained in the numerical representation.
The rounding technique is used to the nearest, which consists in examining the discarded 𝑓 bits, and if their equivalent in decimal is greater than No / 2 (where No is the divisor), it is necessary to add 1 to the obtained result. If when examining the discarded 𝑓 bits their equivalent in decimal is No / 2 the LSB (least significant bit) of the result (number to the left of the decimal mark) must be analyzed, and if it is “1”, it is necessary to add 1, otherwise it is added 0. When the equivalent in decimal of the discarded 𝑓 bits is lower than No / 2 , the result is correct [1] [4] [5].
Figure 6. Frequency response of 4th order low-pass Butterworth filter with fixed point coefficients.
IV.
FILTER ARCHITECTURE
A. General Block Diagram In the figures 7 and 8, all the operations made and the truncation are shown. Normally, the analog-digital converters generate a binary code without a sign, then it is necessary to N 1 subtract the equivalent in binary to Vref / 2 2 in order to the word to become a format with sign. In the figure 8 the operations in the output stage are shown.
Figure 9. Implementation and simulation of the filter using MatLab System Generator.
A user interface is designed in order to enter the transfer function or the filter state equation and automatically generate the VHDL language in a standard format compatible with the format used in a Black Box object of the system generator. Figure 7. Input Stage of the IIR filter.
Once we already have the Black Box with our filter and its sampled input, a signal is injected in order to make a frequency sweep, in this case from 500 Hz until 2500 Hz, and the answer is verified for an interval of determined time, the tool allows to make simulations, either with the generic oscilloscope from Simulink or with the own oscilloscopes of System Generator, the results obtained with this tool is shown in fig. 10.
Figure 8. IIR filter output stage.
The control of saturation verifies if the output “Truncated Y” is greater than (2 N 1 1) or lower than 2 N 1 , because the output to the digital-analog converter (DAC) is of N bits and those values are the maximum allowed with N bits with sign; then the equivalent value in binary is added to equation Vref / 2 2N 1 in order for the output to be mounted again on the DC level if the DAC works with a binary input without a sign. B. Implementaton with System Generator At this point, we should already have many elements defined, such as all the parameters of the filter completely established, the calculus of all the coefficients of the filter, the respective balance, the way in which the truncation and rounding processes must be done. With this done, we proceed to make a description in a high level in a hardware description language, in this case VHDL. This code needs to be done with specific parameters for it to be completely compatible with what is established by MatLab’s System Generator. When verifying the syntax and the correct functioning of this description, the next procedure is to make the import of the code by the Black Box block of the System Generator. For that purpose, it is necessary to take into account that the description made has an input called CLK and another one called CE. Additionally, the device to be used must me set up, the pins of the clock and the frequency of sampling depending on the needs of the filter. Next, in figure 9, a block diagram of the implementation made is shown [1][2][3].
Figure 10. Response of the filter with frequency sweeping from 50 to 2500 HZ in a time of 500 milliseconds.
Figure 10 shows how the result has the behavior of a 4th order Butterworth filter, before the cutting frequency of the response is almost flat, in the cutting frequency the reduction of 3dB is perceived because of the representation of a fixed-point, and how the signal reduces in the higher frequencies to the cutting frequency. Additionally, it is important to highlight the easiness of using the tool in this kind of simulations, because working in the standard simulators for language of descriptions of hardware requires a lot of time and effort. C. Practical Results A Butterworth IIR filter was implemented of order 2 and gain 2, with frequency of sampling of 5KHz and a frequency of cutting of 500 Hz. The filter was implemented in a Spartan 3E Xilinx developing system.
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[2]
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[4] Figure 11. Picture of response of the filter with an input signal at 500 Hz.
Figure 11 shows the response of the filter in the cutting frequency; the input signal is 1 volt amplitude and it is observed that the output is 1.4 volt amplitude, which is equivalent to 3db (1/ 2)Vp . CONCLUSIONS Using state spaces representation in the implementation of filters allows a balanced execution, which showed closer magnitude value coefficients, reducing the number of errors because of the notation of a fixed point, and allowed the reduction of the quantity of bits necessary to represent the coefficients of the filter. It was evident that the frequency response of the filter implemented in state equations is much closer to the ideal response compared with other forms of programming. In the hardware development in FPGA’s a key point is the task of simulation and verification of the models or results, these simulations can be completely tiresome or long, because they require the creation of a test-file “Bench” with determined structure and syntax. In other words, the user must have certain grade of experience to execute these tasks, in this case any person that has had any minimum experience with MatLab’s Simulink can make complex simulations, in a fast way, also, the most interesting issue is that this kind of implementations can be used in projects of a higher complexity. In this work, a graphic interface was made, which allows the user to introduce either its transfer functions or the representations of itself as a state variable, and shows a code in VHDL that is importable from the Black Box block from the System Generator, ready for making the respective simulations in MatLab and their respective implementation in the programmable logic device, all this in an automatic and scalable way in designs of a higher complexity.
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