www.ietdl.org Published in IET Power Electronics Received on 15th August 2012 Revised on 21st October 2012 Accepted on 22nd November 2012 doi: 10.1049/iet-pel.2012.0425

ISSN 1755-4535

Implementation of a soft switching DC/DC converter without reverse recovery loss for rectifier diodes Bor-Ren Lin, Jian-Yo Jhong Department of Electrical Engineering, National Yunlin University of Science and Technology, Taiwan, R.O.C. E-mail: [email protected]

Abstract: This study presents an interleaved soft switching converter to achieve ripple current reduction, zero-voltage switching (ZVS) turn-on for MOSFETs and zero-current switching (ZCS) turn-off for fast recovery diodes. Active snubber circuit is used in the proposed circuit to absorb the energy stored in the leakage inductor and to achieve ZVS turn-on for power switches. The resonant tank composed of the leakage inductor and the resonant capacitor at the secondary side is used to achieve ZCS turnoff for all rectiﬁer diodes. The reverse recovery loss on rectiﬁer diodes can be eliminated. Thus, the low-cost fast recovery diodes can be used at the secondary side. The interleaved pulse-width modulation scheme is used to control two converter cells in order to achieve load sharing and input ripple current reduction. Experiments with a 400 W prototype, verifying the effectiveness of the proposed converter, are described.

1

Introduction

Power converters with high-power density, high conversion efﬁciency and low electromagnetic interference (EMI) have been demanded in order to meet efﬁciency requirements of the Environment Protection Agency (EPA) or Climate Saver Computing Initiative (CSCI). Conventional ﬂyback and forward converters cannot meet the efﬁciency demands because of the large switching losses on power semiconductors. To solve these problems, zero-voltage switching (ZVS) and zero-current switching (ZCS) technique have been proposed to increase the circuit efﬁciency. Active-clamping converters [1–5], asymmetric half-bridge converters [6, 7] and phase-shift pulse-width modulation (PWM) converters [8, 9] have been presented to achieve ZVS and to reduce switching losses. These techniques have been used in the power supply units for server systems, data storage systems, photovoltaic solar systems and telecommunication systems. Resonant converters in [10–18] have the advantages of high-frequency operation, ZVS or ZCS and high-circuit efﬁciency. A half-bridge or full-bridge converter is normally adopted at the primary side in order to realise ZVS turn-on for all power switches. However, the operating switching frequency is depended on load conditions and input voltage level. Thus, it is difﬁcult to design the resonant converter at wide input voltages and load ranges with the limited switching frequency. This paper presents an interleaved PWM converter for high output voltage application. The proposed converter includes two converter cells with interleaved PWM operation. Thus, the input ripple current in the adopted circuit is less than the ripple current in the conventional DC/DC converters. The current stresses of passive and active components are 108 & The Institution of Engineering and Technology 2013

also reduced. In order to reduce the switching losses at high switching frequency operation, active snubber circuit is connected in parallel with transformer in order to limit the voltage spike on MOSFETs and to achieve transformer ﬂux reset. Therefore power switches can be turned on at ZVS. If the output resonant capacitors are properly selected, the secondary leakage inductors and resonant capacitors are resonant to meet the ZCS condition of fast recovery diodes. Thus, there is no reverse recovery loss on the rectiﬁer diodes. Finally, experiments based on a 400 W laboratory prototype were provided to verify the effectiveness of the adopted converter.

2 Circuit configuration and principles of operation Fig. 1 gives the circuit conﬁguration of the proposed converter. In converter cell 1, switches S1 and S2 are operated by an asymmetrical PWM scheme with a short dead time td. Active snubber by switch S2 and capacitor Cc1 is connected in parallel with transformer T1 to reset the energy stored in the leakage inductor of transformer T1 and to limit the voltage stresses of S1 and S2. At the secondary side, the leakage inductors Llk1 and Llk2 and capacitors C1 and C2 are resonant to achieve ZCS turn-off for rectiﬁer diodes D1 and D2. Thus, the reverse recovery losses on rectiﬁer diodes are eliminated. The converter cell 2 includes S3, S4, Cc2, T2, Llk1, Llk2, C1, C2, D1 and D2. The PWM signals of S3 and S4 are phase-shifted by one-half of switching cycle with respective to the PWM signals of S1 and S2. Therefore the input currents i1 and i2 are phase-shifted 180° each other. Switches S3 and S4 are also turned on at ZVS. The secondary windings of T1 and T2 are IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 108–116 doi: 10.1049/iet-pel.2012.0425

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Fig. 1 Circuit conﬁguration of the proposed converter

connected in series so that the ideal primary winding currents of T1 and T2 are identical. In the following, some assumptions are made in order to simplify the system analysis. The transformers T1 and T2 are represented by ideal transformers with the magnetising inductances Lm1 and Lm2 in primary side and the leakage inductances Llk1 and Llk2 in the secondary side. Power switches are ideal expect for their anti-parallel diodes and output capacitances. Voltage drop on rectiﬁer diode is neglected. We assumed that the capacitor voltages VCc1 and VCc2 are constant. Magnetising inductances Lm1 = Lm2 = Lm are larger than leakage inductances Llk1 = Llk2 = Llk. Fig. 2 shows the key waveforms of the proposed converter during one switching cycle. Fig. 3 illustrates the equivalent circuit for each operating mode. Based on on/off states of switches S1–S4 and diodes D1 and D2, there are 12 operation modes in the proposed converter for one switching cycle. Prior to mode 1, switches S2 and S4 are in the on-state. The voltage across primary side of transformers T1 and T2 equal −VCc1 and − VCc2 , respectively. Both magnetising currents iLm1 and iLm2 are decreasing. Rectiﬁer diodes D1 and D2 are reverse biased. Mode 1 [t0 ≤ t < t1, S1 off, S2 off, S3 off, S4 on]: Fig. 3a gives the equivalent circuit of mode 1. At time t0, S2 is turned off. Capacitor CS2 is charged from zero voltage and CS1 is discharged from voltage Vin +VCc1 in this mode. Both diodes D1 and D2 are still reverse biased. At time t1, CS1 is discharged to Vin +VCc2 −vC1 /n. Then rectiﬁer diode D1 is forward biased. Mode 2 [t1 ≤ t < t2, S1 off, S2 off, S3 off, S4 on]: Fig. 3b gives the equivalent circuit of mode 2. This mode begins at t1 when vCS = Vin +VCc2 − vC1 /n. CS2 is still charged and 1 CS1 is discharged in this mode. Diode D2 remains reverse biased and diode D1 is forward biased. The time interval in this mode is very brief because of small output capacitances CS1 and CS2 . Thus the magnetising currents iLm1 and iLm2 maintain constant. This modes ends at time t2 when voltage vCS = 0. 1 Mode 3 [t2 ≤ t < t3, S1 on, S2 off, S3 off, S4 on]: Fig. 3c gives the equivalent circuit of this mode. At time t2, capacitor voltage vCS is decreasing to zero voltage. Thus 1 the anti-parallel diode of S1 is conducting. Since iS1 is negative at time t2, switch S1 can be turned on at this moment to achieve ZVS. In this mode, magnetising inductor current iLm1 increases linearly with the current slope of Vin/Lm. On the other hand, magnetising current iLm2 IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 108–116 doi: 10.1049/iet-pel.2012.0425

Fig. 2 Key waveforms of the proposed converter during one switching cycle

decreases linearly with the current slope of −VCc2 /Lm . Diode D1 is forward biased. The leakage inductance Llk1 and the capacitances C1 and C2 begin to resonate. C1 is charging and C2 is discharging in this operating mode. Thus, the secondary current isec can be deﬁned as ⎡ isec (t) = −⎣C1

⎤ d Vo − vC1 ⎦ − C2 dt dt

dvC1

(1)

If the output capacitance Co is large enough, the ripple component of output voltage Vo can be neglected. The secondary current isec can be further rewritten as dvC1 dvC1 + C2 isec (t) = − C1 dt dt

(2)

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Fig. 3 Operation modes of the proposed converter a Mode 1 b Mode 2 c Mode 3 d Mode 4 e Mode 5 f Mode 6 g Mode 7 h Mode 8 i Mode 9 j Mode 10 k Mode 11 l Mode 12

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Fig. 3

Continued

Diode current iD1 and capacitor voltages vC1 and vC2 are expressed as

iD1 (t) =

n Vin + VCc2 − vC1 t2 Zr

sin vr t − t2

vC1 (t) = n Vin + VCc2 − n Vin + VCc2 − vC1 t2

cos vr t − t2

IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 108–116 doi: 10.1049/iet-pel.2012.0425

(3)

(4)

vC2 (t) = Vo − n Vin + VCc2

+ n Vin + VCc2 − vC1 t2 cos vr t − t2

(5)

and Zr = where n = ns/np, vr = 1/ Llk C1 + C2

Llk / C1 + C2 . Switch current iS1 = iLm1 + niD1 and is expressed in the following equation

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V

iS1 (t) = iLm1 t2 + in t − t2 Lm

n2 Vin + VCc2 − nvC1 t2

sin vr t − t2 + Zr

(6)

In the same manner, the switch current iS4 is expressed in the following equation

iS4 (t) =

n2 Vin + VCc2 − nvC1 t2 Zr

VC

sin vr t − t2 − iLm2 t2 + c2 t − t2 Lm

(7)

n Vin + VCc1 − vC2 t8

sin vr t − t8

(8)

vC1 (t) = Vo − n Vin + VCc1

+ n Vin + VCc1 − vC2 t8 cos vr t − t8

(9)

iD2 (t) =

This mode ends at time t3 when diode current iD1 is decreased to zero. At this moment, capacitor voltage vC1 (t3 ) = 2n(Vin + VCc2 ) − vC1 (t2 ). Mode 4 [t3 ≤ t < t4, S1 on, S2 off, S3 off, S4 on]: The equivalent circuit of this mode is shown in Fig. 3d. At time t3, diode current iD1 = 0. The secondary winding currents are all zero. Since magnetising voltages vLm1 and vLm2 are positive and negative, respectively, magnetising currents iLm1 and iLm2 are linearly increasing and decreasing, respectively. This mode ends at time t4 when switch S1 is turned off. Mode 5 [t4 ≤ t < t5, S1 off, S2 off, S3 off, S4 on]: The equivalent circuit of this mode is shown in Fig. 3e. At time t4, S1 is turned off. Since iLm1 (t4 ) is positive, CS1 is charged from zero voltage to Vin + VCc1 and CS2 is discharged from Vin + VCc1 to zero voltage in this mode. The time interval in this mode is very brief because of small output capacitances CS1 and CS2 . Thus the magnetising currents iLm1 and iLm2 maintain constant. This mode ends at time t5 when voltage vCS2 = 0. Mode 6 [t5 ≤ t < t6, S1 off, S2 on, S3 off, S4 on]: The equivalent circuit of this mode is shown in Fig. 3f. At time t5, capacitor voltage vCS2 reaches zero and the anti-parallel diode of S2 is conducting. Since iS2 (t5 ) is negative, switch S2 can be turned on at this moment to achieve ZVS. The magnetising voltages vLm1 = − VCc1 and vLm2 = −VCc2 and the magnetising currents iLm1 and iLm2 both decrease. Both rectiﬁer diodes D1 and D2 are reverse biased. This mode ends at time t6 when switch S4 is turned off. Mode 7 [t6 ≤ t < t7, S1 off, S2 on, S3 off, S4 off]: Fig. 3g gives the equivalent circuit of mode 7. At time t6, S4 is turned off. Capacitor CS4 4 is charged from zero voltage and CS3 is discharged from voltage Vin + VCc2 2 in this mode. Both diodes D1 and D2 are still reverse biased. At time t7, CS3 is discharged to Vin + VCc1 − vC2 /n. Then rectiﬁer diode D2 is forward biased. Mode 8 [t7 ≤ t < t8, S1 off, S2 on, S3 off, S4 off]: Fig. 3h gives the equivalent circuit of mode 8. At time t7, capacitor voltage vCS3 = Vin + VCc1 − vC2 /n. Diode D2 is forward biased. CS4 is still charged and CS3 is discharged. The time interval in this mode is very brief because of small output capacitances CS3 and CS4 . Thus the magnetising currents iLm1 and iLm2 maintain constant. This modes ends at time t8 when voltage vC3 = 0. Mode 9 [t8 ≤ t < t9, S1 off, S2 on, S3 on, S4 off]: Fig. 3i gives the equivalent circuit of mode 9. At time t8, capacitor voltage vCS3 is decreasing to zero voltage. The anti-parallel diode of S3 is conducting. Since iS3 (t8 ) is negative, switch S3 can be turned on at this moment to achieve ZVS. 112 & The Institution of Engineering and Technology 2013

Magnetising inductor current iLm1 decreases linearly with the current slope of −VCc1 /Lm . On the other hand, magnetising current iLm2 increases linearly with the current slope of Vin/Lm. Diode D2 is forward biased. The leakage inductance Llk2 and the capacitances C1 and C2 are resonant. C1 is discharged and C2 is charged in this mode. The diode current iD2 and capacitor voltages vC1 and vC2 are expressed as:

Zr

vC2 (t) = n Vin + VCc1

− n Vin + VCc1 − vC2 t8 cos vr t − t8

(10)

Switch currents iS2 = −iLm1 1 + niD2 and iS3 = iLm2 + niD2 iS2 (t) =

n2 Vin + VCc1 − nvC2 t8 Zr

VC

sin vr t − t8 − iLm1 t8 + c1 t − t8 Lm

V

iS3 (t) = iLm2 t8 + in t − t8 Lm

n2 Vin + VCc1 − nvC2 t8

sin vr t − t8 + Zr

(11)

(12)

This mode ends at time t9 when diode current iD2 is decreased to zero. At this moment, capacitor voltage vC2 (t9 ) = 2n(Vin + VCc1 ) − vC2 (t8 ). Mode 10 [t9 ≤ t < t10, S1 off, S2 on, S3 on, S4 off]: The equivalent circuit of this mode is shown in Fig. 3j. At time t9, diode current iD2 = 0 = 0. Magnetising voltages vLm1 and vLm2 are negative and positive respectively in this mode such that the magnetising currents iLm1 and iLm2 are linearly decreasing and increasing respectively. This mode ends at time t10 when switch S3 is turned off. Mode 11 [t10 ≤ t < t11, S1 off, S2 on, S3 off, S4 off]: The equivalent circuit of this mode is shown in Fig. 3k. At time t10, S3 is turned off. Since iLm2 (t10 ) is positive, CS3 is charged from zero voltage to Vin + VCc2 and CS4 is discharged from Vin + VCc2 to zero voltage in this mode. The time interval in this mode is very brief such that the magnetising currents iLm1 and iLm2 are almost constant. This modes ends at time t11 when voltage vCS4 = 0. Mode 12 [t11 ≤ t < T + t0, S1 off, S2 on, S3 off, S4 on]: The equivalent circuit of this mode is shown in Fig. 3l. At time t11, capacitor voltage vCS4 is decreased to zero voltage and the anti-parallel diode of S4 is conducting. Since iS4(t11) is negative, switch S4 can be turned on at this moment to achieve ZVS. The magnetising voltages vLm1 = −VCc1 and vLm2 = −VCc2 and iLm1 and iLm2 both decrease. Both rectiﬁer diodes D1 and D2 are reverse biased. This mode ends at time T + t0 when switch S2 is turned off. Then the IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 108–116 doi: 10.1049/iet-pel.2012.0425

www.ietdl.org operating modes of the proposed converter in a switching cycle are completed.

3 3.1

expressed as Io T iD1 ,peak = iD2 ,peak ≃

2 Llk C1 + C2

Design guidelines Capacitor voltages and voltage gain M

Since the time durations of t0–t2, t4–t5 and t6–t8 are much smaller than the switching period T, time intervals in these modes can be neglected. Based on the volt–second balance rule on T1 and T2, the average capacitor voltages VCc1 and VCc2 can be obtained as: VCc1 = VCc2 = dVin /(1 − d)

(13)

iD1 ,rms

VD1 ,peak = VD2 ,peak ≃ Vo =

3.4 (14)

Since duty cycles of S1 and S3 are identical and phase-shifted by one-half of switching cycle, the average output capacitor voltages VC1 and VC2 are balanced and equal to Vo/2. 3.2

ZCS condition for rectiﬁer diodes

In mode 3, input power is delivered to output terminal through T1, S1, Llk1, D1, C1 and C2. The series resonant phenomenon occurs in the secondary side by C1, C2 and Llk1. To achieve the ZCS condition of D1 and D2, one half of the resonant period must be less than the turn-on time of S1 and S3 when δ < 0.5. On the other hand, one half of the resonant period must be greater than the turn-on time of S1 and S3 when δ > 0.5. ⎧ 1 ⎪ ⎨ fr . , 2dT p ⎪ ⎩ fr . , 2(1 − d)T

if d , 0.5 if d . 0.5

(15)

VC (1 − d)T

nIo iLm1 t0 ≃ iLm2 t6 ≃ − c1 ,0 1−d 2Lm

if d . 0.5

d(1 − d)Vin T 2nIo

(21)

Selection of power switches

In the proposed converter, S1 and S2 are operated with the complementary PWM scheme. In the same manner, S3 and S4 are also operated with the asymmetrical PWM. Therefore the voltage stresses of S1–S4 are given as vS1 ,stress = vS2 ,stress = vS3 ,stress = vS4 ,stress =

3.3

Selection for diodes D1 and D2

Based on the current waveforms in Fig. 2, the waveforms of diode currents are only the positive sinusoidal waveforms. Therefore the peak currents and root-mean-square (rms) currents of diodes D1 and D2 can be approximately IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 108–116 doi: 10.1049/iet-pel.2012.0425

(20)

From (20), we can obtain the necessary magnetising inductances Lm1 = Lm2 = Lm.

3.5

(16)

(19)

Based on the discussion in previous section, magnetising currents iLm1 and iLm2 are increasing linearly when S1 and S3 are turned on, respectively. Thus the switch currents iS1 and iS3 are positive and equal to the magnetising current and the diode current reﬂected to primary side. When S1 and S3 are turned off, the positive switch currents iS1 and iS3 will discharge output capacitances of S2 and S4 to zero voltage. Therefore the ZVS operation of switches S2 and S4 are easily achieved. The magnetising currents iLm1 and iLm2 are negative at the moment of turning off switches S2 and S4. Since the average currents of the capacitors Cc1 and Cc2 are zero, the average magnetising currents iLm1,av and iLm2,av equal nIo/(1–δ). To achieve the ZVS conditions of S1 and S3, the magnetising current iLm1 (t0 ) and iLm2 (t6 ) must be negative.

The sum of capacitances C1 and C2 must satisfy the following relations to achieve the ZCS condition of both diodes: if d , 0.5

2nVin 1−d

ZVS condition for switches

Lm ,

⎧

⎪ d2 T 2 ⎪ ⎪ ⎨ C1 + C2 , p2 L , lk ⎪

(1 − d)2 T 2 ⎪ ⎪ , ⎩ C1 + C2 , p2 Llk

(18)

The voltage stresses of diodes D1 and D2 can be expressed as

where δ is the duty ratio of switches S1 and S3. From Fig. 2, it is clear that vC1 (t2 ) = vC2 (t8 ) = vC2 (t3 ) = Vo − 2n(Vin + VCc2 ) + vC1 (t2 ) in steady state. Thus, we can obtain the DC voltage conversion ratio M. 2n M = Vo /Vin = 1−d

iD1 ,peak 2p Llk C1 + C2 = iD2 ,rms ≃ 2 T pT = Io

8 Llk C1 + C2

(17)

Vin 1−d

(22)

The average switches currents are expressed as iS2 ,av = iS4 ,av = 0, iS1 ,av = iS3 ,av =

Po 2hVin

(23)

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Realisation and experimental results

Table 1 Parameters and components of the prototype circuit

The ZVS/ZCS features in the proposed converter are realised with the active snubber circuits in the primary side and resonant circuit in the secondary side. To verify the effectiveness of the proposed converter, a 400 W laboratory prototype is presented. The typical input terminal voltage is 48 V and the output voltage is 400 V. We also assumed that the minimum input voltage is 40 V. The selected switching frequency is 100 kHz and maximum duty cycle is 0.4. The core size of T1 and T2 is EER-42 with Ae = 194 mm2 and ΔB = 2000 G. From (14), we can obtain that the turns ratio of T1 and T2 is given as

n = Vo 1 − dmax / 2Vin, min = 400(1 − 0.4)/(2 × 40) = 3

input voltage output voltage output power switching frequency transformer

capacitors switches diodes

Vin = 48 VDC; Vo = 400 VDC; Po = 400 W; f = 100 kHz; EER-42 core; Ae = 194 mm2; Primary winding: 12 turns of litz wire 6 × 0.6 mm2; Secondary 36 turns of litz wire 1 × winding: 0.7 mm2; Lm1 = Lm2 = 15 μH; Llk1 = Llk2 = 4.2 μH; Cin = 470 μF/100 V; Co = 330 μF/450 V; C1 = C2 = 0.1 μF; CC1 = CC2 = 3 μF; S1 – S4: IRFP264 (250 V/38 A/0.075 Ω); D1, D2: ER506(600 V/5 A);

(23)

The minimum primary turns of T1 and T2 are expressed as

Np, min = Vin, min dmax / Ae DBf

= 40 × 0.4/ 194 × 10−6 × 0.2 × 100 × 103 = 4.1 (24) The actually primary and secondary turns of T1 and T2 are Np = 12 turns and Ns = 36 turns. In order to achieve ZVS turn-on for S1 and S3, the maximum inductance Lm in (21) can be obtained as Lm, max ,

dmax Vin, min 0.4 × 40 = 2nIo f 2 × 3 × 1 × 100 × 103

= 26.7mH

(25)

The magnetising inductance of the prototype circuit is Lm1 = Lm2 = 15 μH. The measured leakage inductances Llk1 = Llk2 = 4.2 μH. In order to achieve ZCS turn-off for diodes D1 and D2, the capacitances C1 + C2 in the prototype circuit can be obtained as

d2 C1 + C2 , 2 max 2 p Llk f =

Fig. 4 Circuit diagram of the prototype circuit in the laboratory tests

0.42

2 = 0.386 mF 3.141592 × 4.2 × 10−6 × 100 × 103 (26)

The resonant capacitances in the prototype circuit are C1 = C2 = 0.1 μF. Table 1 gives the circuit parameters and the components of the prototype circuit. Fig. 4 gives the circuit diagram of the prototype circuit in the laboratory tests. Fig. 5 gives the experimental waveforms of gate voltages, drain voltages and switch currents of S1 and S2 at full load condition. Before switches S1 and S2 are turned on, switch currents are negative to discharge the output capacitance. Thus the drain voltages are decreased to zero and the anti-parallel diodes of S1 and S2 are conducting. Therefore both switches S1 and S2 are turned on at ZVS. In the same manner the measured gate voltages, drain voltages and switch currents of S3 and S4 at full load case are illustrated in Fig. 6. Both switches S3 and S4 are also turned on at ZVS. The measured gate voltage vS1,gs, input terminal current iin and the input currents of two converter cells i1 and i2 at half and full load conditions are shown in Fig. 7. Since the interleaved PWM operation is adopted to control two converter cells, the switching frequency of input 114 & The Institution of Engineering and Technology 2013

Fig. 5 Experimental waveforms of gate voltages, drain voltages and switch currents of S1 and S2 at full-load condition [vS1 ,gs, vS2 ,gs : 20 V/div; vS1 ,ds, vS2 ,ds : 100 V/div; iS1 , iS2 : 20 A/div; time: 2 μs] IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 108–116 doi: 10.1049/iet-pel.2012.0425

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Fig. 6 Experimental waveforms of gate voltages, drain voltages and switch currents of S3 and S4 at full-load condition [vS3 ,gs, vS4 ,gs : 20 V/div; vS3 ,ds, vS4 ,ds : 100 V/div; iS3 , iS4 : 20 A/div; time: 2 μs]

Fig. 8 Experimental waveforms of the gate voltages vS1, gs and vS3, and the transformer primary currents ip1 and ip2 at full load [vS1 ,gs , vS3 ,gs : 20 V/div; ip1, ip2: 20 A/div; time: 2 μs]

gs

terminal current iin is higher than the frequency of two input currents i1 and i2. Thus the input terminal capacitance can be reduced. Fig. 8 shows the experimental waveforms of the gate voltages vS1,gs and vS3,gs and the transformer primary currents ip1 and ip2 at full load condition. Two primary currents ip1 and ip2 are balanced and phase-shifted one half of switching cycle. Therefore each converter cell delivers half rated power to output load. Fig. 9 shows the measured waveforms of gate voltages vS1, gs and vS3, gs and the secondary side currents and voltages at full load condition. Before switches S1 and S3 are turned off, diode currents iD1 and iD2 are decreasing to zero current respectively. Thus both diodes D1 and D2 are turned off ZCS. The reverse recovery problems of D1

Fig. 7 Measured gate voltage vS1,gs, input terminal current iin and the input currents of two converter cells i1 and i2 at a Half load condition b Full-load condition [vS1,gs : 20 V/div; iin, i1, i2: 10 A/div; time: 4 μs] IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 108–116 doi: 10.1049/iet-pel.2012.0425

Fig. 9 Measured waveforms of gate voltages vS1 ,gs and vS3 ,gs and the secondary side currents and voltages at full-load condition [vS1 ,gs , vS3 ,gs : 20 V/div; vC1 , vC2 : 200 V/div; iD1 , iD2 , iC1 , iC2 , io: 5 A/div; time: 2 μs] 115

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www.ietdl.org system like PV MPPT DC/DC converter in PV inverter system. Laboratory experiments with a 400 W prototype, verifying the effectiveness of the proposed converter, are described.

6

Fig. 10 Measured efﬁciency of the proposed converter at different load conditions

and D2 are removed. When diode D1 is conducting, capacitor currents iC1 and iC2 are positive and negative respectively. Thus capacitor voltages vC1 and vC2 increase and decrease, respectively. If both diodes are off, capacitor voltages vC1 and vC2 keep the voltage constant. If the diode D2 is conducting, capacitor currents iC1 and iC2 are negative and positive, respectively, such that capacitor voltage vC1 decreases and capacitor voltage vC2 increases. Fig. 10 shows the measured efﬁciency of the proposed converter in different load conditions. Since power switches are turned on at ZVS and diodes are turned off at ZCS, the maximum efﬁciency of the circuit is about 92.4%.

5

Conclusion

An interleaved PWM DC/DC converter has been presented to achieve ripple current reduction at input side. Two transformers connected in series in the secondary side in order to balance two converter input currents. Active snubber circuits are used to limit the voltage stresses of power switches and to achieve ZVS turn-on feature. In the secondary side of transformers, the leakage inductances Llk1 and Llk2 and output capacitances C1 and C2 are resonant during turn-on time of switch S1 or S3. Since the half of resonant period is designed to be less than the turn-on time of switch S1 and S3, both rectiﬁer diodes are turned off at ZCS. The switching losses of power switches and reverse recovery losses of rectiﬁer diodes are reduced. The proposed converter can be used in the low-voltage input and high-output voltage applications such as battery discharger in personal UPS system and renewable energy

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References

1 Das, P., Laan, B., Mousavi, S.A., Moschopoulos, G.: ‘A nonisolated bidirectional ZVS-PWM active clamped DC–DC converter’, IEEE Trans. Power Electron., 2009, 24, (2), pp. 553–558 2 Lee, J.-J., Kwon, B.-H.: ‘Active-clamped ripple-free DC/DC converter using an input–output coupled inductor’, IEEE Trans. Ind. Electron., 2008, 55, (4), pp. 1842–1854 3 Lin, B.-R., Huang, C.-L.: ‘Analysis and implementation of a novel soft-switching pulse-width modulation converter’, IET Proc. – Power Electron., 2009, 2, (1), pp. 90–101 4 Lin, B.-R., Dong, J.-Y., Chen, J.-J.: ‘Analysis and Implementation of a ZVS/ZCS DC–DC switching converter with voltage step-up’, IEEE Trans. Ind. Electron., 2011, 58, (7), pp. 2962–2971 5 Lee, J.J., Kwon, J.M., Kim, E.H., Kwon, B.H.: ‘Dual series-resonant active-clamp converter’, IEEE Trans. Ind. Electron., 2008, 55, (2), pp. 699–710 6 Lin, B.-R., Tseng, C.H.: ‘Analysis of parallel-connected asymmetrical soft-switching converter’, IEEE Trans. Ind. Electron., 2009, 54, (3), pp. 1642–1653 7 Liu, J.C.P., Poon, N.K., Pong, B.M.H., Tse, C.K.: ‘Low output ripple dc-dc converter based on an overlapping dual asymmetric half-bridge topology’, IEEE Trans. Power Electron., 2007, 22, (5), pp. 1956–1963 8 Koo, G.B., Moon, G.W., Youn, M.J.: ‘New zero-voltage-switching phase-shift full-bridge converter with low conduction losses’, IEEE Trans. Ind. Electron., 2005, 52, (1), pp. 28–235 9 Lin, B.R., Huang, K., Wang, D.: ‘Analysis and implementation of full-bridge converter with current doubler rectiﬁer’, IEE Proc., Electr. Power Appl., 2005, 152, (5), pp. 1193–1202 10 Steigerwald, R.: ‘A comparison of half bridge resonant converter topologies’. Proc., of IEEE IAS, 1987, pp. 135–144 11 Xie, X., Zhang, J., Chen, Z., Zhao, Z., Qian, Z.: ‘Analysis and optimization of LLC resonant converter with a novel over-current protection circuit’, IEEE Trans. Power Electron., 2007, 22, (2), pp. 435–443 12 Yi, K.H., Moon, G.W.: ‘Novel two-phase interleaved LLC series-resonant converter using a phase of the resonant capacitor’, IEEE Trans. Ind. Electron., 2009, 56, (5), pp. 1815–1819 13 Fu, D., Liu, Y., Lee, F.C., Xu, M.: ‘A novel driving scheme for synchronous rectiﬁers in LLC resonant converters’, IEEE Trans. Power Electron., 2009, 24, (5), pp. 1321–1329 14 Jin, K., Ruan, X.: ‘Hybrid full-bridge three-level LLC resonant converter - a novel DC-DC converter suitable for fuel-cell power system’, IEEE Trans. Ind. Electron., 2006, 53, (5), pp. 1492–1503 15 Yang, B., Lee, F.C., Zhang, A.J., Huang, G.: ‘LLC resonant converter for front end DC/DC conversion’. Proc. IEEE APEC, 2002, vol. 2, pp. 1108–1112 16 Lin, B.R., Wu, S.F.: ‘Implementation of a series resonant converter with series–parallel transformers’, IET Proc. – Power Electron., 2011, 4, (8), pp. 919–926 17 Lin, B.R., Wu, S.F.: ‘ZVS resonant converter with series-connected transformers’, IEEE Trans., Ind. Electron., 2011, 58, (8), pp. 3547–3554 18 Gu, Y., Lu, Z., Hang, L., Qian, Z., Huang, G.: ‘Three-level LLC series resonant DC/DC converter’, IEEE Trans. Power Electron., 2005, 20, (4), pp. 781–789

IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 108–116 doi: 10.1049/iet-pel.2012.0425

ISSN 1755-4535

Implementation of a soft switching DC/DC converter without reverse recovery loss for rectifier diodes Bor-Ren Lin, Jian-Yo Jhong Department of Electrical Engineering, National Yunlin University of Science and Technology, Taiwan, R.O.C. E-mail: [email protected]

Abstract: This study presents an interleaved soft switching converter to achieve ripple current reduction, zero-voltage switching (ZVS) turn-on for MOSFETs and zero-current switching (ZCS) turn-off for fast recovery diodes. Active snubber circuit is used in the proposed circuit to absorb the energy stored in the leakage inductor and to achieve ZVS turn-on for power switches. The resonant tank composed of the leakage inductor and the resonant capacitor at the secondary side is used to achieve ZCS turnoff for all rectiﬁer diodes. The reverse recovery loss on rectiﬁer diodes can be eliminated. Thus, the low-cost fast recovery diodes can be used at the secondary side. The interleaved pulse-width modulation scheme is used to control two converter cells in order to achieve load sharing and input ripple current reduction. Experiments with a 400 W prototype, verifying the effectiveness of the proposed converter, are described.

1

Introduction

Power converters with high-power density, high conversion efﬁciency and low electromagnetic interference (EMI) have been demanded in order to meet efﬁciency requirements of the Environment Protection Agency (EPA) or Climate Saver Computing Initiative (CSCI). Conventional ﬂyback and forward converters cannot meet the efﬁciency demands because of the large switching losses on power semiconductors. To solve these problems, zero-voltage switching (ZVS) and zero-current switching (ZCS) technique have been proposed to increase the circuit efﬁciency. Active-clamping converters [1–5], asymmetric half-bridge converters [6, 7] and phase-shift pulse-width modulation (PWM) converters [8, 9] have been presented to achieve ZVS and to reduce switching losses. These techniques have been used in the power supply units for server systems, data storage systems, photovoltaic solar systems and telecommunication systems. Resonant converters in [10–18] have the advantages of high-frequency operation, ZVS or ZCS and high-circuit efﬁciency. A half-bridge or full-bridge converter is normally adopted at the primary side in order to realise ZVS turn-on for all power switches. However, the operating switching frequency is depended on load conditions and input voltage level. Thus, it is difﬁcult to design the resonant converter at wide input voltages and load ranges with the limited switching frequency. This paper presents an interleaved PWM converter for high output voltage application. The proposed converter includes two converter cells with interleaved PWM operation. Thus, the input ripple current in the adopted circuit is less than the ripple current in the conventional DC/DC converters. The current stresses of passive and active components are 108 & The Institution of Engineering and Technology 2013

also reduced. In order to reduce the switching losses at high switching frequency operation, active snubber circuit is connected in parallel with transformer in order to limit the voltage spike on MOSFETs and to achieve transformer ﬂux reset. Therefore power switches can be turned on at ZVS. If the output resonant capacitors are properly selected, the secondary leakage inductors and resonant capacitors are resonant to meet the ZCS condition of fast recovery diodes. Thus, there is no reverse recovery loss on the rectiﬁer diodes. Finally, experiments based on a 400 W laboratory prototype were provided to verify the effectiveness of the adopted converter.

2 Circuit configuration and principles of operation Fig. 1 gives the circuit conﬁguration of the proposed converter. In converter cell 1, switches S1 and S2 are operated by an asymmetrical PWM scheme with a short dead time td. Active snubber by switch S2 and capacitor Cc1 is connected in parallel with transformer T1 to reset the energy stored in the leakage inductor of transformer T1 and to limit the voltage stresses of S1 and S2. At the secondary side, the leakage inductors Llk1 and Llk2 and capacitors C1 and C2 are resonant to achieve ZCS turn-off for rectiﬁer diodes D1 and D2. Thus, the reverse recovery losses on rectiﬁer diodes are eliminated. The converter cell 2 includes S3, S4, Cc2, T2, Llk1, Llk2, C1, C2, D1 and D2. The PWM signals of S3 and S4 are phase-shifted by one-half of switching cycle with respective to the PWM signals of S1 and S2. Therefore the input currents i1 and i2 are phase-shifted 180° each other. Switches S3 and S4 are also turned on at ZVS. The secondary windings of T1 and T2 are IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 108–116 doi: 10.1049/iet-pel.2012.0425

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Fig. 1 Circuit conﬁguration of the proposed converter

connected in series so that the ideal primary winding currents of T1 and T2 are identical. In the following, some assumptions are made in order to simplify the system analysis. The transformers T1 and T2 are represented by ideal transformers with the magnetising inductances Lm1 and Lm2 in primary side and the leakage inductances Llk1 and Llk2 in the secondary side. Power switches are ideal expect for their anti-parallel diodes and output capacitances. Voltage drop on rectiﬁer diode is neglected. We assumed that the capacitor voltages VCc1 and VCc2 are constant. Magnetising inductances Lm1 = Lm2 = Lm are larger than leakage inductances Llk1 = Llk2 = Llk. Fig. 2 shows the key waveforms of the proposed converter during one switching cycle. Fig. 3 illustrates the equivalent circuit for each operating mode. Based on on/off states of switches S1–S4 and diodes D1 and D2, there are 12 operation modes in the proposed converter for one switching cycle. Prior to mode 1, switches S2 and S4 are in the on-state. The voltage across primary side of transformers T1 and T2 equal −VCc1 and − VCc2 , respectively. Both magnetising currents iLm1 and iLm2 are decreasing. Rectiﬁer diodes D1 and D2 are reverse biased. Mode 1 [t0 ≤ t < t1, S1 off, S2 off, S3 off, S4 on]: Fig. 3a gives the equivalent circuit of mode 1. At time t0, S2 is turned off. Capacitor CS2 is charged from zero voltage and CS1 is discharged from voltage Vin +VCc1 in this mode. Both diodes D1 and D2 are still reverse biased. At time t1, CS1 is discharged to Vin +VCc2 −vC1 /n. Then rectiﬁer diode D1 is forward biased. Mode 2 [t1 ≤ t < t2, S1 off, S2 off, S3 off, S4 on]: Fig. 3b gives the equivalent circuit of mode 2. This mode begins at t1 when vCS = Vin +VCc2 − vC1 /n. CS2 is still charged and 1 CS1 is discharged in this mode. Diode D2 remains reverse biased and diode D1 is forward biased. The time interval in this mode is very brief because of small output capacitances CS1 and CS2 . Thus the magnetising currents iLm1 and iLm2 maintain constant. This modes ends at time t2 when voltage vCS = 0. 1 Mode 3 [t2 ≤ t < t3, S1 on, S2 off, S3 off, S4 on]: Fig. 3c gives the equivalent circuit of this mode. At time t2, capacitor voltage vCS is decreasing to zero voltage. Thus 1 the anti-parallel diode of S1 is conducting. Since iS1 is negative at time t2, switch S1 can be turned on at this moment to achieve ZVS. In this mode, magnetising inductor current iLm1 increases linearly with the current slope of Vin/Lm. On the other hand, magnetising current iLm2 IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 108–116 doi: 10.1049/iet-pel.2012.0425

Fig. 2 Key waveforms of the proposed converter during one switching cycle

decreases linearly with the current slope of −VCc2 /Lm . Diode D1 is forward biased. The leakage inductance Llk1 and the capacitances C1 and C2 begin to resonate. C1 is charging and C2 is discharging in this operating mode. Thus, the secondary current isec can be deﬁned as ⎡ isec (t) = −⎣C1

⎤ d Vo − vC1 ⎦ − C2 dt dt

dvC1

(1)

If the output capacitance Co is large enough, the ripple component of output voltage Vo can be neglected. The secondary current isec can be further rewritten as dvC1 dvC1 + C2 isec (t) = − C1 dt dt

(2)

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Fig. 3 Operation modes of the proposed converter a Mode 1 b Mode 2 c Mode 3 d Mode 4 e Mode 5 f Mode 6 g Mode 7 h Mode 8 i Mode 9 j Mode 10 k Mode 11 l Mode 12

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Fig. 3

Continued

Diode current iD1 and capacitor voltages vC1 and vC2 are expressed as

iD1 (t) =

n Vin + VCc2 − vC1 t2 Zr

sin vr t − t2

vC1 (t) = n Vin + VCc2 − n Vin + VCc2 − vC1 t2

cos vr t − t2

IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 108–116 doi: 10.1049/iet-pel.2012.0425

(3)

(4)

vC2 (t) = Vo − n Vin + VCc2

+ n Vin + VCc2 − vC1 t2 cos vr t − t2

(5)

and Zr = where n = ns/np, vr = 1/ Llk C1 + C2

Llk / C1 + C2 . Switch current iS1 = iLm1 + niD1 and is expressed in the following equation

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V

iS1 (t) = iLm1 t2 + in t − t2 Lm

n2 Vin + VCc2 − nvC1 t2

sin vr t − t2 + Zr

(6)

In the same manner, the switch current iS4 is expressed in the following equation

iS4 (t) =

n2 Vin + VCc2 − nvC1 t2 Zr

VC

sin vr t − t2 − iLm2 t2 + c2 t − t2 Lm

(7)

n Vin + VCc1 − vC2 t8

sin vr t − t8

(8)

vC1 (t) = Vo − n Vin + VCc1

+ n Vin + VCc1 − vC2 t8 cos vr t − t8

(9)

iD2 (t) =

This mode ends at time t3 when diode current iD1 is decreased to zero. At this moment, capacitor voltage vC1 (t3 ) = 2n(Vin + VCc2 ) − vC1 (t2 ). Mode 4 [t3 ≤ t < t4, S1 on, S2 off, S3 off, S4 on]: The equivalent circuit of this mode is shown in Fig. 3d. At time t3, diode current iD1 = 0. The secondary winding currents are all zero. Since magnetising voltages vLm1 and vLm2 are positive and negative, respectively, magnetising currents iLm1 and iLm2 are linearly increasing and decreasing, respectively. This mode ends at time t4 when switch S1 is turned off. Mode 5 [t4 ≤ t < t5, S1 off, S2 off, S3 off, S4 on]: The equivalent circuit of this mode is shown in Fig. 3e. At time t4, S1 is turned off. Since iLm1 (t4 ) is positive, CS1 is charged from zero voltage to Vin + VCc1 and CS2 is discharged from Vin + VCc1 to zero voltage in this mode. The time interval in this mode is very brief because of small output capacitances CS1 and CS2 . Thus the magnetising currents iLm1 and iLm2 maintain constant. This mode ends at time t5 when voltage vCS2 = 0. Mode 6 [t5 ≤ t < t6, S1 off, S2 on, S3 off, S4 on]: The equivalent circuit of this mode is shown in Fig. 3f. At time t5, capacitor voltage vCS2 reaches zero and the anti-parallel diode of S2 is conducting. Since iS2 (t5 ) is negative, switch S2 can be turned on at this moment to achieve ZVS. The magnetising voltages vLm1 = − VCc1 and vLm2 = −VCc2 and the magnetising currents iLm1 and iLm2 both decrease. Both rectiﬁer diodes D1 and D2 are reverse biased. This mode ends at time t6 when switch S4 is turned off. Mode 7 [t6 ≤ t < t7, S1 off, S2 on, S3 off, S4 off]: Fig. 3g gives the equivalent circuit of mode 7. At time t6, S4 is turned off. Capacitor CS4 4 is charged from zero voltage and CS3 is discharged from voltage Vin + VCc2 2 in this mode. Both diodes D1 and D2 are still reverse biased. At time t7, CS3 is discharged to Vin + VCc1 − vC2 /n. Then rectiﬁer diode D2 is forward biased. Mode 8 [t7 ≤ t < t8, S1 off, S2 on, S3 off, S4 off]: Fig. 3h gives the equivalent circuit of mode 8. At time t7, capacitor voltage vCS3 = Vin + VCc1 − vC2 /n. Diode D2 is forward biased. CS4 is still charged and CS3 is discharged. The time interval in this mode is very brief because of small output capacitances CS3 and CS4 . Thus the magnetising currents iLm1 and iLm2 maintain constant. This modes ends at time t8 when voltage vC3 = 0. Mode 9 [t8 ≤ t < t9, S1 off, S2 on, S3 on, S4 off]: Fig. 3i gives the equivalent circuit of mode 9. At time t8, capacitor voltage vCS3 is decreasing to zero voltage. The anti-parallel diode of S3 is conducting. Since iS3 (t8 ) is negative, switch S3 can be turned on at this moment to achieve ZVS. 112 & The Institution of Engineering and Technology 2013

Magnetising inductor current iLm1 decreases linearly with the current slope of −VCc1 /Lm . On the other hand, magnetising current iLm2 increases linearly with the current slope of Vin/Lm. Diode D2 is forward biased. The leakage inductance Llk2 and the capacitances C1 and C2 are resonant. C1 is discharged and C2 is charged in this mode. The diode current iD2 and capacitor voltages vC1 and vC2 are expressed as:

Zr

vC2 (t) = n Vin + VCc1

− n Vin + VCc1 − vC2 t8 cos vr t − t8

(10)

Switch currents iS2 = −iLm1 1 + niD2 and iS3 = iLm2 + niD2 iS2 (t) =

n2 Vin + VCc1 − nvC2 t8 Zr

VC

sin vr t − t8 − iLm1 t8 + c1 t − t8 Lm

V

iS3 (t) = iLm2 t8 + in t − t8 Lm

n2 Vin + VCc1 − nvC2 t8

sin vr t − t8 + Zr

(11)

(12)

This mode ends at time t9 when diode current iD2 is decreased to zero. At this moment, capacitor voltage vC2 (t9 ) = 2n(Vin + VCc1 ) − vC2 (t8 ). Mode 10 [t9 ≤ t < t10, S1 off, S2 on, S3 on, S4 off]: The equivalent circuit of this mode is shown in Fig. 3j. At time t9, diode current iD2 = 0 = 0. Magnetising voltages vLm1 and vLm2 are negative and positive respectively in this mode such that the magnetising currents iLm1 and iLm2 are linearly decreasing and increasing respectively. This mode ends at time t10 when switch S3 is turned off. Mode 11 [t10 ≤ t < t11, S1 off, S2 on, S3 off, S4 off]: The equivalent circuit of this mode is shown in Fig. 3k. At time t10, S3 is turned off. Since iLm2 (t10 ) is positive, CS3 is charged from zero voltage to Vin + VCc2 and CS4 is discharged from Vin + VCc2 to zero voltage in this mode. The time interval in this mode is very brief such that the magnetising currents iLm1 and iLm2 are almost constant. This modes ends at time t11 when voltage vCS4 = 0. Mode 12 [t11 ≤ t < T + t0, S1 off, S2 on, S3 off, S4 on]: The equivalent circuit of this mode is shown in Fig. 3l. At time t11, capacitor voltage vCS4 is decreased to zero voltage and the anti-parallel diode of S4 is conducting. Since iS4(t11) is negative, switch S4 can be turned on at this moment to achieve ZVS. The magnetising voltages vLm1 = −VCc1 and vLm2 = −VCc2 and iLm1 and iLm2 both decrease. Both rectiﬁer diodes D1 and D2 are reverse biased. This mode ends at time T + t0 when switch S2 is turned off. Then the IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 108–116 doi: 10.1049/iet-pel.2012.0425

www.ietdl.org operating modes of the proposed converter in a switching cycle are completed.

3 3.1

expressed as Io T iD1 ,peak = iD2 ,peak ≃

2 Llk C1 + C2

Design guidelines Capacitor voltages and voltage gain M

Since the time durations of t0–t2, t4–t5 and t6–t8 are much smaller than the switching period T, time intervals in these modes can be neglected. Based on the volt–second balance rule on T1 and T2, the average capacitor voltages VCc1 and VCc2 can be obtained as: VCc1 = VCc2 = dVin /(1 − d)

(13)

iD1 ,rms

VD1 ,peak = VD2 ,peak ≃ Vo =

3.4 (14)

Since duty cycles of S1 and S3 are identical and phase-shifted by one-half of switching cycle, the average output capacitor voltages VC1 and VC2 are balanced and equal to Vo/2. 3.2

ZCS condition for rectiﬁer diodes

In mode 3, input power is delivered to output terminal through T1, S1, Llk1, D1, C1 and C2. The series resonant phenomenon occurs in the secondary side by C1, C2 and Llk1. To achieve the ZCS condition of D1 and D2, one half of the resonant period must be less than the turn-on time of S1 and S3 when δ < 0.5. On the other hand, one half of the resonant period must be greater than the turn-on time of S1 and S3 when δ > 0.5. ⎧ 1 ⎪ ⎨ fr . , 2dT p ⎪ ⎩ fr . , 2(1 − d)T

if d , 0.5 if d . 0.5

(15)

VC (1 − d)T

nIo iLm1 t0 ≃ iLm2 t6 ≃ − c1 ,0 1−d 2Lm

if d . 0.5

d(1 − d)Vin T 2nIo

(21)

Selection of power switches

In the proposed converter, S1 and S2 are operated with the complementary PWM scheme. In the same manner, S3 and S4 are also operated with the asymmetrical PWM. Therefore the voltage stresses of S1–S4 are given as vS1 ,stress = vS2 ,stress = vS3 ,stress = vS4 ,stress =

3.3

Selection for diodes D1 and D2

Based on the current waveforms in Fig. 2, the waveforms of diode currents are only the positive sinusoidal waveforms. Therefore the peak currents and root-mean-square (rms) currents of diodes D1 and D2 can be approximately IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 108–116 doi: 10.1049/iet-pel.2012.0425

(20)

From (20), we can obtain the necessary magnetising inductances Lm1 = Lm2 = Lm.

3.5

(16)

(19)

Based on the discussion in previous section, magnetising currents iLm1 and iLm2 are increasing linearly when S1 and S3 are turned on, respectively. Thus the switch currents iS1 and iS3 are positive and equal to the magnetising current and the diode current reﬂected to primary side. When S1 and S3 are turned off, the positive switch currents iS1 and iS3 will discharge output capacitances of S2 and S4 to zero voltage. Therefore the ZVS operation of switches S2 and S4 are easily achieved. The magnetising currents iLm1 and iLm2 are negative at the moment of turning off switches S2 and S4. Since the average currents of the capacitors Cc1 and Cc2 are zero, the average magnetising currents iLm1,av and iLm2,av equal nIo/(1–δ). To achieve the ZVS conditions of S1 and S3, the magnetising current iLm1 (t0 ) and iLm2 (t6 ) must be negative.

The sum of capacitances C1 and C2 must satisfy the following relations to achieve the ZCS condition of both diodes: if d , 0.5

2nVin 1−d

ZVS condition for switches

Lm ,

⎧

⎪ d2 T 2 ⎪ ⎪ ⎨ C1 + C2 , p2 L , lk ⎪

(1 − d)2 T 2 ⎪ ⎪ , ⎩ C1 + C2 , p2 Llk

(18)

The voltage stresses of diodes D1 and D2 can be expressed as

where δ is the duty ratio of switches S1 and S3. From Fig. 2, it is clear that vC1 (t2 ) = vC2 (t8 ) = vC2 (t3 ) = Vo − 2n(Vin + VCc2 ) + vC1 (t2 ) in steady state. Thus, we can obtain the DC voltage conversion ratio M. 2n M = Vo /Vin = 1−d

iD1 ,peak 2p Llk C1 + C2 = iD2 ,rms ≃ 2 T pT = Io

8 Llk C1 + C2

(17)

Vin 1−d

(22)

The average switches currents are expressed as iS2 ,av = iS4 ,av = 0, iS1 ,av = iS3 ,av =

Po 2hVin

(23)

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Realisation and experimental results

Table 1 Parameters and components of the prototype circuit

The ZVS/ZCS features in the proposed converter are realised with the active snubber circuits in the primary side and resonant circuit in the secondary side. To verify the effectiveness of the proposed converter, a 400 W laboratory prototype is presented. The typical input terminal voltage is 48 V and the output voltage is 400 V. We also assumed that the minimum input voltage is 40 V. The selected switching frequency is 100 kHz and maximum duty cycle is 0.4. The core size of T1 and T2 is EER-42 with Ae = 194 mm2 and ΔB = 2000 G. From (14), we can obtain that the turns ratio of T1 and T2 is given as

n = Vo 1 − dmax / 2Vin, min = 400(1 − 0.4)/(2 × 40) = 3

input voltage output voltage output power switching frequency transformer

capacitors switches diodes

Vin = 48 VDC; Vo = 400 VDC; Po = 400 W; f = 100 kHz; EER-42 core; Ae = 194 mm2; Primary winding: 12 turns of litz wire 6 × 0.6 mm2; Secondary 36 turns of litz wire 1 × winding: 0.7 mm2; Lm1 = Lm2 = 15 μH; Llk1 = Llk2 = 4.2 μH; Cin = 470 μF/100 V; Co = 330 μF/450 V; C1 = C2 = 0.1 μF; CC1 = CC2 = 3 μF; S1 – S4: IRFP264 (250 V/38 A/0.075 Ω); D1, D2: ER506(600 V/5 A);

(23)

The minimum primary turns of T1 and T2 are expressed as

Np, min = Vin, min dmax / Ae DBf

= 40 × 0.4/ 194 × 10−6 × 0.2 × 100 × 103 = 4.1 (24) The actually primary and secondary turns of T1 and T2 are Np = 12 turns and Ns = 36 turns. In order to achieve ZVS turn-on for S1 and S3, the maximum inductance Lm in (21) can be obtained as Lm, max ,

dmax Vin, min 0.4 × 40 = 2nIo f 2 × 3 × 1 × 100 × 103

= 26.7mH

(25)

The magnetising inductance of the prototype circuit is Lm1 = Lm2 = 15 μH. The measured leakage inductances Llk1 = Llk2 = 4.2 μH. In order to achieve ZCS turn-off for diodes D1 and D2, the capacitances C1 + C2 in the prototype circuit can be obtained as

d2 C1 + C2 , 2 max 2 p Llk f =

Fig. 4 Circuit diagram of the prototype circuit in the laboratory tests

0.42

2 = 0.386 mF 3.141592 × 4.2 × 10−6 × 100 × 103 (26)

The resonant capacitances in the prototype circuit are C1 = C2 = 0.1 μF. Table 1 gives the circuit parameters and the components of the prototype circuit. Fig. 4 gives the circuit diagram of the prototype circuit in the laboratory tests. Fig. 5 gives the experimental waveforms of gate voltages, drain voltages and switch currents of S1 and S2 at full load condition. Before switches S1 and S2 are turned on, switch currents are negative to discharge the output capacitance. Thus the drain voltages are decreased to zero and the anti-parallel diodes of S1 and S2 are conducting. Therefore both switches S1 and S2 are turned on at ZVS. In the same manner the measured gate voltages, drain voltages and switch currents of S3 and S4 at full load case are illustrated in Fig. 6. Both switches S3 and S4 are also turned on at ZVS. The measured gate voltage vS1,gs, input terminal current iin and the input currents of two converter cells i1 and i2 at half and full load conditions are shown in Fig. 7. Since the interleaved PWM operation is adopted to control two converter cells, the switching frequency of input 114 & The Institution of Engineering and Technology 2013

Fig. 5 Experimental waveforms of gate voltages, drain voltages and switch currents of S1 and S2 at full-load condition [vS1 ,gs, vS2 ,gs : 20 V/div; vS1 ,ds, vS2 ,ds : 100 V/div; iS1 , iS2 : 20 A/div; time: 2 μs] IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 108–116 doi: 10.1049/iet-pel.2012.0425

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Fig. 6 Experimental waveforms of gate voltages, drain voltages and switch currents of S3 and S4 at full-load condition [vS3 ,gs, vS4 ,gs : 20 V/div; vS3 ,ds, vS4 ,ds : 100 V/div; iS3 , iS4 : 20 A/div; time: 2 μs]

Fig. 8 Experimental waveforms of the gate voltages vS1, gs and vS3, and the transformer primary currents ip1 and ip2 at full load [vS1 ,gs , vS3 ,gs : 20 V/div; ip1, ip2: 20 A/div; time: 2 μs]

gs

terminal current iin is higher than the frequency of two input currents i1 and i2. Thus the input terminal capacitance can be reduced. Fig. 8 shows the experimental waveforms of the gate voltages vS1,gs and vS3,gs and the transformer primary currents ip1 and ip2 at full load condition. Two primary currents ip1 and ip2 are balanced and phase-shifted one half of switching cycle. Therefore each converter cell delivers half rated power to output load. Fig. 9 shows the measured waveforms of gate voltages vS1, gs and vS3, gs and the secondary side currents and voltages at full load condition. Before switches S1 and S3 are turned off, diode currents iD1 and iD2 are decreasing to zero current respectively. Thus both diodes D1 and D2 are turned off ZCS. The reverse recovery problems of D1

Fig. 7 Measured gate voltage vS1,gs, input terminal current iin and the input currents of two converter cells i1 and i2 at a Half load condition b Full-load condition [vS1,gs : 20 V/div; iin, i1, i2: 10 A/div; time: 4 μs] IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 108–116 doi: 10.1049/iet-pel.2012.0425

Fig. 9 Measured waveforms of gate voltages vS1 ,gs and vS3 ,gs and the secondary side currents and voltages at full-load condition [vS1 ,gs , vS3 ,gs : 20 V/div; vC1 , vC2 : 200 V/div; iD1 , iD2 , iC1 , iC2 , io: 5 A/div; time: 2 μs] 115

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www.ietdl.org system like PV MPPT DC/DC converter in PV inverter system. Laboratory experiments with a 400 W prototype, verifying the effectiveness of the proposed converter, are described.

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Fig. 10 Measured efﬁciency of the proposed converter at different load conditions

and D2 are removed. When diode D1 is conducting, capacitor currents iC1 and iC2 are positive and negative respectively. Thus capacitor voltages vC1 and vC2 increase and decrease, respectively. If both diodes are off, capacitor voltages vC1 and vC2 keep the voltage constant. If the diode D2 is conducting, capacitor currents iC1 and iC2 are negative and positive, respectively, such that capacitor voltage vC1 decreases and capacitor voltage vC2 increases. Fig. 10 shows the measured efﬁciency of the proposed converter in different load conditions. Since power switches are turned on at ZVS and diodes are turned off at ZCS, the maximum efﬁciency of the circuit is about 92.4%.

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Conclusion

An interleaved PWM DC/DC converter has been presented to achieve ripple current reduction at input side. Two transformers connected in series in the secondary side in order to balance two converter input currents. Active snubber circuits are used to limit the voltage stresses of power switches and to achieve ZVS turn-on feature. In the secondary side of transformers, the leakage inductances Llk1 and Llk2 and output capacitances C1 and C2 are resonant during turn-on time of switch S1 or S3. Since the half of resonant period is designed to be less than the turn-on time of switch S1 and S3, both rectiﬁer diodes are turned off at ZCS. The switching losses of power switches and reverse recovery losses of rectiﬁer diodes are reduced. The proposed converter can be used in the low-voltage input and high-output voltage applications such as battery discharger in personal UPS system and renewable energy

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IET Power Electron., 2013, Vol. 6, Iss. 1, pp. 108–116 doi: 10.1049/iet-pel.2012.0425