Implementation of Digital IQ Imbalance Compensation in OFDM WLAN Receivers Kuang-Hao Lin, Hsin-Lei Lin, Shih-Ming Wang, and Robert C. Chang Department of Electrical Engineering National Chung-Hsing University Taichung, Taiwan Email:
[email protected] Abstract—Although the maximum transmission speed in IEEE 802.11a WLAN is 54Mbps, the real throughput is actually limited to 20~30Mbps. Except for the main effect from multipath, we should also consider some non-ideal effects from imperfect hardware design, such as the IQ imbalance from direct conversion in RF front-end. IQ imbalance is not apparent in lower-order QAM modulation. However, in higher-order QAM modulation, it will become serious interference. In this paper, an IQ imbalance compensation circuit in IEEE802.11a baseband receiver is proposed. A low complexity time-domain compensation algorithm is used to replace the traditional high- order equalizer. MATLAB is used to simulate the whole transceiver including the channel model. After system verification, we use Verilog to implement the IQ imbalance compensation circuit with UMC 0.18um COMS 1p6m technology. Post-layout simulation results show that this scheme contributes to a very robust and easily implemented OFDM WLAN receiver.
I. INTRODUCTION Because the required transmission of the wireless local area networks (WLANs) becomes faster, a higher-order modulation of quadrature amplitude modulation (QAM) to improve data rate is needed. Thus, the IQ imbalance will cause a severe degradation of demodulation performance. We usually adopt an equalizer to implement the IQ imbalance compensation circuit. However, the equalizer is so complex that it is difficult to be implemented into hardware. In addition, lots of efforts are spent on developing inexpensive orthogonal frequency division multiplex (OFDM) receivers. Particularly, zero intermediate frequency (Zero-IF) receivers are very interesting, because they avoid costly IF components. However, zero-IF front-ends also introduce additional severe front-end distortion, such as IQ imbalance. Unfortunately, OFDM using higher order modulation is very sensitive to the nonidealities of the receiver front-end. Thus, we employ a very low complexity scheme to estimate and correct IQ imbalance [1,2]. The disadvantageous impact of IQ imbalance on demodulation performance is a traditional problem. IQ imbalance results from a nonideal front-end component due to the power imbalance or the non-orthogonality between
inphase (I) and quadrature (Q) branches. Particularly for increasingly popular zero-IF or direct conversion receiver architectures, analog IQ separation is performed and IQ imbalance is almost unavoidable. Due to higher-order modulation in the OFDM WLAN receiver, even manufacturing inaccuracies of analog front-end components will cause severe degradation of demodulation accuracy. Therefore, to avoid expensive devices for front-end requirements, digital algorithms and implementations must be introduced to compensate IQ imbalance and to improve demodulation accuracy. Several methods for compensating IQ imbalance in OFDM transmission were proposed [3-5]. Reference [3] targets OFDM WLAN receivers with a non-adaptive timedomain scheme for estimation and correction of IQ imbalance. In [4], the compensation scheme eliminates the IQ imbalance based on one OFDM symbol and performs well in the presence of phase noise. Reference [5] applies frequency-domain method and targets DVB with an adaptive equalizer. In this paper, we implement a low complexity digital IQ imbalance compensation scheme for OFDM receivers to remove distortions from IQ imbalance in time domain. This paper is organized as follows. In section II, a model for IQ imbalance is described. The effects of IQ imbalance on OFDM are shown. Section III discusses IQ imbalance structure of the correction scheme and the simulation results. The hardware implementation is given in section IV. Finally, section V concludes this paper. II.
EFFECTS OF IQ IMBALANCE
A. Effect A low-cost implementation of OFDM physical layers is challenging for taking account of impairments associated with the analog components. There are mainly two different receiver architectures utilized when the received radiofrequency (RF) signal is down-converted to baseband. One is the direct conversion RF receiver with its potential for low-cost and low-power implementation on silicon, and the other one is the super-heterodyne receiver. The direct
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0-7803-9390-2/06/$20.00 ©2006 IEEE
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conversion structure is introduced by popular zero intermediate frequency (zero-IF). Although the structure dispenses with expensive external IF filter and the imagerejection filter, disadvantages are accompanied such as DC offset, IQ imbalance, etc. The direct down-conversion to baseband is implemented by what is known as complex down-conversion, as shown in Fig. 1. It is an attractive scheme, since it avoids costly IF filters and allows for easier integration than the superheterodyne structure. A complex down-converter basically multiplies the RF signal by the complex waveform VLO = exp(− j 2π f LO ) , where f LO is the local oscillator frequency at the receiver. To perform the complex downconversion, both of the sine and cosine waveforms are required. As seen in Fig. 1, in-phase Kcos, quadrature-phase Ksin, and two multipliers are required to perform the complex down-conversion, where K is the amplitude parameter of amplitude imbalance. Furthermore, the receiver is divided into I and Q branches. The key is that the effective sine and cosine waveforms at the receiver performing the down-conversion need to be orthogonal, i.e., exactly with 90° phase difference and with the same amplitude. Any mismatch between the processing performed on the I and Q branches after down-conversion will contribute to the overall IQ imbalance in the system and can significantly affect the system performance.
K
I
S′ I
S
I
Cross talk sin
+
S′ Q
S Q
Phase imbalance cos
K Q
Figure 2. The channel model of IQ imbalance.
The impact of IQ imbalance on the received OFDM signal is hardly visible, since there is no actual signal constellation in the time-domain. In the frequency-domain, however, IQ imbalance can be easily recognized as demonstrated in Fig. 3 for 64-QAM with an amplitude imbalance of KI =1, KQ=1.2 and a phase imbalance of ijerr =10°. However, the received signal of Fig. 3 had been corrected by IQ imbalance compensation is shown in Fig. 4. 1.5
1
LPF 0.5 Quadrature
I K cos
V VRF
0
LO -0.5
90
o -1
− K sin
Q
-1.5 -2
LPF
⎤ ⎡ s 'I [ k ]⎤ •⎢ ⎥ K Q • cosϕerr ⎥⎦ ⎣⎢sQ' [k ]⎦⎥
-0.5
0 Inphase
0.5
1
1.5
2
(1)
1.5
1
0.5 Quadrature
B. Model IQ imbalance can be characterized by 2 parameters: the amplitude imbalance K as a power mismatch between I and Q branches, and the phase imbalance ijerr yielding an orthogonality mismatch between I and Q branches. A popular model for an IQ imbalance impaired signal s = sI + j sQ is given by 0
-1
Figure 3. 64-QAM constellation impaired by amplitude and phase imbalance.
Figure 1. Zero-IF receiver structure.
KI ⎡ sI [k ] ⎤ ⎡ ⎢s [k ]⎥ = ⎢ − K • sin ϕ err ⎣Q ⎦ ⎣ Q
-1.5
0
-0.5
-1
where s’I and s’Q denote the components of the unimpaired signal. The amplitude imbalance K is represented by the two symmetrical factors KI and KQ while the phase imbalance is captured in ijerr yielding cross talk of I branch to Q branch as shown in Fig. 2.
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-1.5 -2
-1.5
-1
-0.5
0 Inphase
0.5
1
1.5
2
Figure 4. 64-QAM constellation compensatory by IQ imbalance compensation.
III. ESTIMATION AND COMPANSTION OF IQ IMBALANCE Traditionally, the IQ imbalance compensation circuit is designed by an equalizer, which corrects degradation of demodulation performance. The advantage of using an equalizer is that increasing the tap order of the equalizer can improve the correction. However, the disadvantage is that the equalizer may not be converged when the training symbols are not enough or the front-end channel variability increases. Therefore, it needs a higher complex digital equalizer circuit to perform degradation correction for improving the demodulation performance. Since the implementation of a high complex equalizer hardware was very difficult, this paper uses a time-domain compensation algorithm to avoid complexity and retain fixed performance [3]. We employ long preamble of L=64 estimated IQ imbalance compensation parameter. Equations (2) and (3) can find out IQ imbalance parameters amplitude (Kest,b) and phase (Pest), respectively.
IV. HARDWARE IMPLEMENTATION This section contains three parts, i.e., hardware description, simulation, and implementation. We proposed a method to implement hardware easily for IQ imbalance compensation. A. Hardware Description Figure 6 shows the function blocks of the OFDM system. We employed this architecture to simulate and implement IQ imbalance compensation. The blocks with dotted line are the channel effects including AWGN, multipath fading, and IQ imbalance. The IQ imbalance compensation block is implemented in time-domain to increase demodulation performance. Data(t)
802.11a Transmitter
S(t)
Exponential ly Decaying Rayleigh Fading channel
IQ Imbalance Effect
W(t)
L
K est .b =
∑s
2 Q
[k ]
k =1 L
∑s
R(t)
(2) 2 I
Timing Estim ation
IQ Imbalance Compensation
FFT
Frequency Equalizer
802.11a Receiver
R_Data(t)
[k ]
k =1
BER(PER)
∑ (s [k ] ⋅ s L
I
Pest =
Q
k =1
[k ])
(3)
Figure 6. Function blocks of the OFDM system.
L
∑ s [k ] 2 I
k =1
Equations (4) and (5) are used to compensate amplitude and phase imbalances, respectively [3]. ⎧ wI [ k ] = S I [ k ] / K est .b ⎨ ⎩ wQ [ k ] = S Q [ k ]
⎧ wI [ k ] = S I [ k ] ⎪ 1 ⎨ w [k ] = × [SQ [ k ] − Pest ⋅ S I [ k ]] ⎪ Q 1 − Pest2 ⎩
(4)
(5)
In Fig. 5, the reference BER demodulating an unimpaired signal without IQ imbalance correction is compared to the BER demodulating a signal in the AWGN and multipath fading conditions with IQ imbalance compensation.
A received OFDM signal impaired by both of amplitude and phase imbalance is compensated in two phases: first performing amplitude imbalance estimation and compensation according to equations (2) and (4); second performing phase imbalance estimation and compensation as given in equations (3) and (5). Figure 7 illustrates the foregoing correction method of hardware structure for IQ imbalance compensation. In the beginning, we must wait for the start trigger from the front-end signal when long preamble symbol is detected. Then, calculate the parameter Kest,b according to amplitude estimation equation and attain amplitude compensation (I_A_ok and Q_A_ok) by Amplitude Corrector (A.C.). The parameter Pest can be calculated according to the phase estimation equation and the phase compensation and the unimpaired signal (I_ ok and Q_ ok) can be attained through the Phase Corrector (P.C.). The shaded calculation circuit block in Fig. 7 can be reused by hardware combination for low cost. Thus, Fig. 8 shows a control block that must be introduced for the hardware combination.
Figure 5. Performance comparision for IQ imbalance with and without compensation.
Figure 7. The block diagram of IQ imbalance compensation circuit.
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Figure 8 shows the flowchart of the control block. There are four states (S0…S3). The initial state is in S0 waiting for the long preamble start trigger. In S1, the length of long preamble is counted to apply Kest calculation after S0 is triggered. Amplitude estimation finish signal, which waits for A.C. process to accomplish correction, is introduced in S2. Finally, in S3 long preamble length is counted again for Pest calculation. Long not start
count_fin = 0
S0
S1 Long start
count_en=0
count _en=1
Figure 11. Layout view on cadence. count _fin = 1
S3
count_fin = 1
TABLE I.
Amplitude Estimation finish
count_en=1
count _fin = 0
S2
SPECIFICATION OF IMPLEMENTATION
Process Operation frequency Gate count Power Area
count _en=0 Amplitude Estimation not finish
Figure 8. The flowchart of control block.
B. Simulation Figures 9 and 10 show the pre-simulation and postsimulation results of IQ compensation, respectively, with amplitude imbalance of KI =1 and KQ=1.2, phase imbalance of ijerr =10°, SNR=25dB, and multipath=11. We can find I_ok and Q_ok in pre-simulation with comparison to postsimulation accordingly.
UMC.18 1p6m 20MHz 59768 10mW 1.0581.865 mm2
V. CONCLUSION This paper presented the IQ imbalance compensation circuit in IEEE802.11a baseband receiver. We have employed a low complexity time-domain compensation algorithm to replace the traditional high-order equalizer. In system simulation, the AWGN and multipath fading channel is adopted. Here, we use MATLAB to produce the test signals and verify the effectiveness of the compensation circuit through the cell-based design process. Post-layout simulation results show that this scheme contributes to a very robust and easily implemented OFDM WLAN receiver. ACKNOWLEDGMENT The authors would like to thank National Chip Implementation Center (CIC) of Taiwan for technical support.
Figure 9. Pre-simulation of IQ compensation.
REFERENCES [1] [2]
[3] Figure 10. Post-simulation of IQ compensation. [4]
C. Implementation Figure 11 shows the layout diagram of the IQ imbalance compensation circuit, the five functional blocks of the proposed circuit are integrated in this chip. Specification of the implementation results are given in Table 1.
[5]
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J. Heiskala and J. Terry, OFDM Wireless LANs: A Theoretical and Practical Guide, SAMS Publishing, 2002. Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High-Speed Physical Layer in the 5 GHz Band, IEEE Standard 802.11a-1999ಧPart II, Sep.1999. I. Held, O. Klein, A. Chen and V. Ma, ಯ Low complexity digital IQ imbalance correction in OFDM WLAN receivers,ರin IEEE Vehicular Technology Conf., vol. 2, pp. 1172-1176, May 2004,. J. Tubbax, B. Come, L. VanderPerre, S. Donnay, M. Engels, H. and DeMan M. Moonen, “Compensation of IQ Imbalance and Phase Noise in OFDM Systems,” IEEE Transactions on Wireless Communications, vol. 4, pp. 872-877, May 2005. A Schuchert, R. Hasholzner and P. Antoine, “A novel IQ imbalance compensation scheme for the reception of OFDM signals,” IEEE Transactions on Consumer Electronics, vol. 47, pp. 313-318, Aug. 2001.
