Improved active input current shapers for converters with ... - IEEE Xplore

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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 37, NO. 2, MARCH/APRIL 2001

Improved Active Input Current Shapers for Converters with Symmetrically Driven Transformer Javier Sebastián, Member, IEEE, Arturo Fernández, Member, IEEE, Pedro José Villegas, Member, IEEE, Marta María Hernando, Member, IEEE, and Juan Manuel Lopera, Member, IEEE

Abstract—This paper deals with the analysis of new implementations of the recently proposed active input current shaper (AICS). Using these implementations, the size of the AICS inductors used in ac-to-dc converters based on “symmetrically driven” dc-to-dc topologies (e.g., half bridge, push–pull, or full bridge) can be reduced and even integrated in only one magnetic core. As in the case of other converters with the AICS, the new implementations allow us to reduce the line current harmonics in order to comply with the IEC 1000-3-2 specifications, maintaining all the features of the standard dc-to-dc converters (e.g., fast transient response). Finally, the four proposed implementations of the AICS have been experimentally tested. Index Terms—IEC 1000-3-2 specifications, power-factor correction, power supplies.

I. INTRODUCTION

I

N SEARCH OF low-cost high-performance ac-to-dc power converters complying with IEC 1000-3-2 specifications, many power topologies have been proposed and investigated [1]–[6]. Some of them are based on the idea of using standard topologies (such as flyback, forward, SEPIC, Cuk and zeta) with only small modifications (additional diodes and inductors) in order to comply with the above mentioned specifications. Three of these converters are shown in Fig. 1(a)–(c) [3]–[6]. All these converters become the same topology in special design conditions. Thus, regarding Fig. 1(a) [3], [4], by setting , by designing in the continuous conduction mode (CCM) and by taking into account the leakage inductance, this topology becomes the one shown in Fig. 2(a). The same occurs with the topology given in Fig. 1(b) [5] if the “network” is chosen as shown in the same figure, or if some topological transformations are made in Fig. 1(c) and [6]. The final converter obtained in the three cases is shown in Fig. 2(a), where the main part of the topology is a flyback dc-to-dc converter. Other topologies in which the main transformer is “asymmetrically driven” are also possible (see Fig. 2(b), where the main part of the topology is a forward dc-to-dc converter). “Asymmetrically driven” means that the Paper IPCSD 00–068, presented at the 2000 IEEE Applied Power Electronics Conference and Exposition, New Orleans, LA, February 6–10, and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Industrial Power Converter Committee of the IEEE Industry Applications Society. Manuscript submitted for review December 15, 1999 and released for publication December 12, 2000. The authors are with the Departamento de Ingeniería Eléctrica, Electrónica, de Computadores y Sistemas, Universidad de Oviedo, 33204 Gijón, Spain (e-mail: [email protected]; [email protected]; [email protected]; [email protected];[email protected]). Publisher Item Identifier S 0093-9994(01)02097-7.

Fig. 1. Three different types of ac-to-dc converters which can be designed to comply with the IEC 1000-3-2 regulations. (a) Converter proposed in [3]. (b) Converter proposed in [5]. (c) Converter proposed in [6].

voltage applied to the transformer windings is an asymmetrical waveform [see Fig. 2(c) and (d)] whose average value is, of course, zero. The objective of this paper is to present new topologies of ac-to-dc converters based on "symmetrically driven" dc-to-dc topologies. This means topologies in which the voltage across the transformer windings is symmetrical. Examples of this type of topologies are half bridge, push–pull, and full bridge, which are topologies suitable for power ranges higher than the above mentioned. II. REVIEW OF THE AICS As in the case of the topologies presented in [6], the new topologies can be derived from the concept of the AICS. The AICS is based on the connection of one additional output of the converter [obtained from the converter’s transformer; see

0093–9994/01$10.00 ©2001 IEEE

SEBASTIÁN et al.: IMPROVED ACTIVE INPUT CURRENT SHAPERS

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Fig. 2. Two implementations which can be easily obtained as particular cases of the converter proposed in [3]–[6]. (a) Flyback-type converter. (b) Forward-type converter. (c) Voltage across the transformer windings in the case of a flyback-type converter in CCM. (d) Voltage across the transformer windings in the case of a forward-type converter.

Fig. 3. (a) General scheme for an ac-to-dc converter with the AICS proposed in [6]. (b) Main waveforms.

Fig. 3(a)] between the input rectifier and the low-frequency filter ). In appearance, the additional capacitor (bulk capacitor, output is similar to the main output of a forward converter. Howhas been connected in series with the ever, an extra inductor . high-frequency rectifier diode stops conDue to this inductor, the freewheeling diode ducting later than in a forward converter without the additional , as can easily be deduced from Fig. 3(b). Thus, inductor this inductor is called a “delaying inductor” and the additional can be output a “delayed forward output.” The delay time easily computed from Faraday’s Law [see Fig. 3(b)]

The effective duty cycle

at the input of the output filter will

be (2) is the switching frequency. Therefore, newhere glecting the current ripple through inductor (that is, and, therefore, ), the output voltage will be (3) This equation can be rewritten as follows: (4)

(1)

has an open-control-loop Therefore, the output voltage equivalent circuit that consists of a voltage source

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Fig. 4. Equivalent circuit for any ac-to-dc converter with reduction of the low-frequency harmonics, based on the use of AICS.

and a loss-free resistor (LFR) . It should be noted that no energy is dissipated in the output (and, therefore, in the equivalent LFR) if all the components are ideal. It should also is transferred to the same be noted that the energy stored in place as the energy stored in the transformer magnetizing inductance (e.g., the output if the dc-to-dc converter is a flyback one or the bulk capacitor if it is a forward one). The energy stored in the delaying inductor is

(5) In summary, the Thévenin equivalent of the additional output and with the output inductor operwith this extra inductor plus an LFR ating in the CCM, consists of a voltage source (see Fig. 4 and [6]). These elements connected in series between the line rectifier and the bulk capacitor help the line rectifier to start conducting. In fact, it starts conducting when , being the the input voltage reaches the value (see Fig. 4). When the line voltage across the bulk capacitor ), the current passing rectifier is conducting (that is, during and consists of pieces of positive sinusoids, through , two dc voltage sources since a sinusoidal voltage source ) and a resistor are the only elements in the ( and path in which it is circulating. Therefore, the line current waveform consists of pieces of positive and negative sinusoids (see must be chosen larger than Fig. 4), whose conduction angle 67.5 in order to comply with the IEC 1000-3-2 regulations in at 230 V. class at 220 V [6] and larger than This type of solution to reduce the harmonic content belongs to the family of “single-stage power-factor-corrector (PFC) circuits.” As in the case of other single-stage PFC circuits, the main objective is not to obtain a sinusoidal (or almost sinusoidal) line current, but to obtain a line current with a harmonic content that meets the regulations. Due to its inherent simplicity, the voltage across the bulk capacitor is not maintained constant in single-stage PFC circuits, at least if they are operating at constant switching frequency. This is the main drawback of these circuits, in comparison to the two-stage approach based on a resistor emulator plus a dc-to-dc converter. If we compare the AICS solution (which is based on two additional inductors) with other single-stage PFC circuits based on

Fig. 5.

General scheme for the new proposed type of AICS.

the use of only one additional inductor operating in the discontinuous conduction mode (DCM), the former exhibits the following advantages. • Less energy is recycled from the transformer and injected between the line rectifier and the bulk capacitor [7]. This is because this solution can be designed to minimize the voltage connected between the line rectifier and the bulk capacitor. This voltage can even be zero at the peak value of the minimum line voltage at full load. • The peak value of the current passing through all the electronic devices is lower in the case of the AICS solution due to the fact that the additional output operates in the CCM instead of in the DCM. Its main disadvantage is that two inductors must be used. However, the size of these inductors can be reduced in the case of topologies of ac-to-dc converters based on “symmetrically driven” dc-to-dc topologies by using the new AICS proposed in this paper.

III. NEW AICS FOR CONVERTERS WITH SYMMETRICALLY DRIVEN TRANSFORMER The AICS concept can also be applied to converters with a symmetrically driven transformer (e.g., half bridge, full bridge, and push-pull). In these cases, the delayed output can be implemented based on a full-wave rectifier (see Fig. 5). Four different implementations of this type of rectifier are shown in Fig. 6(a)–(d), one based on a single-phase bridge rectifier [Fig. 6(a)] and three based on a full-wave, center-tapped rectifier [Fig. 6(b)–(d)]. In all these cases, the value of output inductor is at least twice lower than in the case of the delayed output based on a half-wave rectifier, due to the fact that the switching frequency and the duty cycle at the input of the output filter are twice higher. In practice, this inductor is around three times lower. Case A): Delayed Output Based on a Single-Phase Bridge Rectifier [Fig. 6(a)]: In this case, four fast diodes and two inductors are used. The maximum reverse voltage across these , whereas the average current is . diodes is can be easily computed from Faraday’s The delay time Law, taking into account that the variation of the current passing


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It should be noted that, to obtain the same value of the LFR , the value of the delaying inductor must be 4 times lower in this case than in the case of using a delayed output based on a half-wave rectifier. The energy stored in the delaying inductor can be calculated by (5). Due to the fact that the value of the current is the same as in the case of the half-wave rectifier and, however, the inductance is four times lower, then the energy stored will also be four times lower and the size will be four times smaller. Case B): Delayed Output Based on a Full-Wave, Center-tapped Rectifier With Two Delaying Inductors [Fig. 6(b)]: This topology is directly derived from the parallel connection of two delayed outputs based on half-wave rectifiers. As a consequence of its symmetrical structure, the can be removed with no theoretical freewheeling diode influence on the converter operation. In this case, only two fast diodes and three inductors are used. The maximum reverse , whereas the average voltage across these diodes is . current is and that the current ripple Assuming that is negligible (see Fig. 7(b)), we obtain (9) Therefore, the output voltage will be (10) and, hence, (11)

Fig. 6. Four basic implementations of the new type of delayed output, based on full-wave rectifiers. (a) Delayed output based on a single-phase bridge rectifier. (b) Delayed output based on a center-tapped rectifier with two delaying inductors. (c) Delayed output based on a center-tapped rectifier with one delaying inductor with a center tap. (d) Delayed output based on a center-tapped rectifier with only one magnetic core.

through during is twice [assuming that the current ripple is negligible; see Fig. 7(a)]

, the Therefore, to obtain a specific value of the LFR and must be 2 lower value of the delaying inductors in this case than in the case of using a delayed output based on a half-wave rectifier. However, two delaying inductors (instead of one) must be used. The total energy stored in them will be the same as in the case of using a half-wave rectifier and, therefore, the total size will be the same too. Case C): Delayed Output Based on a Full-Wave, Centertapped Rectifier with One Delaying Inductor with Center Tap and of the [Fig. 6(c)]: The two delaying inductors previous delayed output can be coupled into only one magnetic core. Its magnetizing inductance, referred to one of the two windings, will be (12)

(6) Taking into account that the rectifier is a full-wave one and (2), the output voltage will be

is the inductance of the total winding. Taking into where , the account that the variation of magnetizing current is delay time will be

(7)

(13)

and, hence,

Therefore, the output voltage will be (8)

(14)

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Fig. 7. Main waveforms for the two basic types of delayed outputs with full-wave rectifier. (a) Single-phase rectifier [Fig. 6(a)]. (b) Center-tapped rectifier [Fig. 6(b)–(d)].

and, hence, (15) , the Therefore, to obtain a specific value of the LFR in this case is the same as in value of the delaying inductor the case of a delayed output based on a half-wave rectifier. However, the energy stored (and, therefore, the size) is not the same, at because current is not passing through all the inductor is divided into two the same time. In fact, the total current and ) which circulate through the two parts currents ( . The energy stored in has a maximum value when of all the current passes through only one of the two halves of , that is, through an inductance whose value is . Thus, the energy stored will be four times lower than in the case of a delaying inductor based on a half-wave rectifier (and, therefore, the size will be four times smaller). Case D): Delayed Output Based on a Full-Wave, Center-tapped Rectifier with Only One Magnetic Core and and [Fig. 6(d)]: The two delaying inductors can be built using only one magnetic the output inductor core, according to the process shown in Fig. 8. The magnetic device consists of only one magnetic core with two windings with the same number of turns. The coupling between both winding must not be very tight, in order to have the value of the two leakage inductances equal to the desired value of the delayed inductance, obtained from (11). Details about how a two-winding top–bottom arrangement must be designed to have a specific leakage inductance can be found in [8]. Magnetic design tools (such as UO-M [9], PEmag [10], etc.) can also be useful for this purpose.

Finally, the use of the four types of delayed output for an ac-to-dc converter in which the dc-to-dc part is a half-bridge topology is shown in Fig. 9. IV. EQUATIONS TO DESIGN THE NEW TYPE OF AICS The equations to design this new topology can be easily derived from the ones given in [6] for the flyback. In this case, the is constant (it does not only difference is that the value of depend on the input voltage ). The total set of equations is as follows. • Geometrical considerations from Fig. 4: (16) • If • If

, (17) (18)

• DC-to-DC voltage conversion ratio: If the dc-to-dc converter is a half bridge, (19) If the dc-to-dc converter is a full bridge or push–pull, (20) • Value of

: (21)


Fig. 8.

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Process to integrate all magnetic devices of a delayed output based on a center-tapped rectifier, into only one magnetic core.

(a)

(b)

(c)

(d)

Fig. 9. The four implementations of delayed output applied to an ac-to-dc converter in which the dc-to-dc converter is a half-bridge one. (a) Delayed output based on a single-phase bridge rectifier. (b) Delayed output based on a center-tapped rectifier with two delaying inductors. (c) Delayed output based on a center-tapped rectifier with one delaying inductor with a center tap. (d) Delayed output based on a center-tapped rectifier with only one magnetic core.

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• Power balance:

(22) is the input power and the rest of the quantities where are shown in Fig. 9 for the particular case of converters in which the dc-to-dc converter is a half-bridge one. Fig. 10 shows the voltage across the bulk capacitor obtained by solving the above-mentioned equations for a specific design. The design procedure of this new type of AICS is very similar to the procedure shown in [7] to design converters with the previous type of AICS (delayed output with half-wave recti, the fier). The inputs of this design are the output voltage , and the maximum and minimum maximum input power and . values of the peak value of the input voltage, The steps can be summarized as follows. (the value of the conduction angle Step 1) Choose at the input voltage specified in the regulations), according to a tradeoff between harmonics reduction and recycled energy. In every case, this conduction angle must be higher than 67.44 at 220 V and 64.47 at 230 V. (the maximum value of the conStep 2) Calculate ), by solving the following equaduction angle tion, obtained from (22): (23) being the peak value of the input voltage specified in the regulations. from (24) Step 3) Calculate (24) This equation has been obtained from (18), by taking into account that the optimum design of any AICS is achieved by setting the value of the voltage across the bulk capacitor equal to the peak value of the line voltage, when this line voltage is minimum and the input power is maximum. Step 4) Choose either the maximum value of the duty cycle, , or the ratio of turns of the transformer. Both quantities are related by ((19) and (20)) and, therefore, one of them can be obtained from this equation if the other is known. It should be noted in these equations must be its that the value of . minimum value, by using (22) for a particular case Step 5) Calculate , and or , (e.g., either and ). The value of the delaying inductor will be calculated from either (8) or (11) or (15), depending on the type of delayed output. The input inductor must be chosen several times calculated in Case "A" higher than the value of (for example, 3–6 higher).

Fig. 10. Voltage across the bulk capacitor in a specific design of converter with AICS, designed for the European range of input voltage.

Step 6) Solve the set of (18) and (22) to calculate the evoluacross the bulk capacitor when tion of the voltage and the input power change. the input voltage V. EXPERIMENTAL RESULTS A prototype of a half-bridge converter with the four types of new AICS has been built and tested. The main parameters of this converter are as follows: – V rms V kHz turns turns in cases B–D F V H

– A turns F

transistors: Cool MOS SPP11N60S5 (Siemens) main output rectifier diodes: BYW51 (ST) delayed output rectifier diodes: MUR 160 (Motorola). • Delayed output based on a single-phase bridge rectifier [Fig. 9(a)] H E

core

H E

core.

• Delayed output based on a center-tapped rectifier with two delaying inductors [Fig. 9(b)] H E

core

H E

core.

• Delayed output based on a center-tapped rectifier with one delaying inductor with center tap [Fig. 9(c)] H E

core

H E

core.

• Delayed output based on a center-tapped rectifier with only one magnetic core [Fig. 9(d)] two windings of 108 turns in top–bottom arrangement H, mH. in an E30 core. Fig. 11 shows the line current waveforms at 230 V [Fig. 11(a)] and at 190 V [Fig. 11(b)]. The harmonic content of the line current at 230-V rms is given in Fig. 12. The efficiency of the power stage (excluding control circuitry) of this prototype operating as a dc-to-dc converter (a dc input voltage source has been conand, therefore, the input bridge diodes nected in parallel with are not conducting) is shown in Fig. 13(a), whereas its efficiency operating as an ac-to-dc converter is depicted in Fig. 13(b) (only 2%–3% lower). All these results have been obtained with the implementation shown in Fig. 9(b). However, these results are


Fig. 11. Input current waveform obtained in the prototype with the type of delayed output shown in Fig. 9(b). (a) At 230-V rms. (b) At 190-V rms.

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Fig. 14.

Voltage across the bulk capacitor.

Finally, the variations of the voltage across the bulk capacitor are shown in Fig. 14. As this figure shows, both experimental and theoretical results coincide while the output inductor is working in the CCM, whereas the experimental values are lower than the theoretical values when this inductor is working in the DCM. As this figure also shows, this voltage is always lower than 450 V, even when the converter has no load. In fact the maximum value of this voltage was 420 V, obtained at 30 W and 265-V rms. VI. CONCLUSIONS Fig. 12.

Harmonic content measured in the prototype at 230-V rms.

Fig. 13. Efficiency measured in the prototype. (a) Operating as a dc-to-dc converter. (b) Operating as an ac-to-dc converter.

almost the same when the other implementations of delayed output have been tested. Only a slight reduction in converter efficiency was measured when the implementation shown in Fig. 9(d) was tested (1–2 points lower). It should be noted that the efficiency obtained is very high, due to the fact that the new type of Siemens MOSFETs (Cool MOS transistors) has been used in the half-bridge topology.

Four implementations of AICSs suitable to be used with converters in which the transformer is driven by symmetrical voltage waveforms have been presented in this paper. These new implementations conserve the same features as the previous implementations of AICSs, that is: • only a few elements are added to the classical dc-to-dc converters; • fast response when the load changes (as in standard dc-to-dc converters); • low efficiency penalty to comply with the IEC-1000-3-2; • low variation in the voltage across the bulk capacitor if the converter is operating from a specific range of input voltage (either European or American). Moreover, the new implementations allow a considerable reduction in the size of the magnetic elements. Thus, the input inductor is at least twice smaller than in the previous implementations and they also allow either a reduction of the delaying inductor size by four times or the integration of all AICS inducand ) into only one magnetic core. tors ( , REFERENCES [1] F. Tsai, P. Markowski, and E. Whitcomb, “Off-line flyback converter with input harmonic current correction,” in Proc. IEEE Int. Telecommunications Energy Conf., 1996, pp. 120–124.

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[2] M. Daniele, P. Jain, and G. Jóos, “A single stage power factor corrected ac/dc converter,” in Proc. IEEE Int. Telecommunications Energy Conf., 1996, pp. 256–262. [3] L. Huber and M. Jovanovic, “Single-stage, single-switch, isolated power supply technique with input-current shaping and fast output-voltage regulation for universal input-voltage-range applications,” in Proc. IEEE APEC’97, 1997, pp. 272–280. , “Design optimization of single-stage, single-switch input-current [4] shapers,” in Proc. IEEE PESC’97, 1997, pp. 519–526. [5] G. Hua, “Consolidated soft-switching ac/dc converters,” U.S. Patent 5 790 389, Aug. 4, 1998. [6] J. Sebastián, M. M. Hernando, P. Villegas, J. Díaz, and A. Fontán, “Input current shaper based on the series connection of a voltage source and a loss-free resistor,” IEEE Trans. Ind. Applicat., vol. 37, pp. 583–591, Mar./Apr. 2001. , “A new input current shaping technique using converters operating [7] in continuous conduction mode,” in Proc. IEEE PESC’98, 1998, pp. 1330–1336. [8] A. Dauhajre and R. D. Middlebrook, “Modeling and estimation of leakage phenomena in magnetic circuits,” in Proc. IEEE PESC’86, 1986, pp. 213–226. [9] UO-M2T reference guide (1999). [Online]. Available: http://www.ate.uniovi.es/investigaciones/patentes_es.html [10] PEmag Reference Guide, UPM-Ansoft Corp., Pittsburgh, PA, 1998.

Arturo Fernández (M’98) was born in Oviedo, Spain, in 1972. He received the M.Sc. and Ph.D. degrees in electrical engineering from the University of Oviedo, Gijón, Spain, in 1997 and 2000, respectively. Since 1998, he has been an Assistant Professor at the University of Oviedo. His research interests are switching-mode power supplies, converter modeling, and high-power-factor rectifiers.

Pedro José Villegas (M’96) was born in Suances, Spain, in 1965. He received the M.Sc. and Ph.D. degrees in electrical engineering from the University of Oviedo, Gijón, Spain, in 1991 and 2000, respectively. Since 1994, he has been an Assistant Professor at the University of Oviedo. His research interests are switching-mode power supplies, converter modeling, and high-power-factor rectifiers.

Marta María Hernando (M’95) was born in Gijón, Spain, in 1964. She received the M.Sc. and Ph.D. degrees in electrical engineering from the University of Oviedo, Gijón, Spain, in 1988 and 1992, respectively. She is currently an Associate Professor at the University of Oviedo. Her main interests are switching-mode power supplies and high-power-factor rectifiers. Javier Sebastián (M’86) was born in Madrid, Spain, in 1958. He received the M.Sc. degree from the Polytechnic University of Madrid, Madrid, Spain, and the Ph.D. degree from the University of Oviedo, Gijón, Spain, in 1981 and 1985, respectively. He was an Assistant Professor and an Associate Professor at the Polytechnic University of Madrid and at the University of Oviedo. Since 1992, he has been with the University of Oviedo, where he is currently a Professor. His research interests are switching-mode power supplies, modeling of dc-to-dc converters, low-output-voltage dc-to-dc converters, and high-power-factor rectifiers. Prof. Sebastián has been an Associate Editor of the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS since 1997.

Juan Manuel Lopera (M’98) was born in Avilés, Spain, in 1966. He received the M.Sc. and Ph.D. degrees in electrical engineering from the University of Oviedo, Gijón, Spain, in 1990 and 1994, respectively. Since 1990, he has been with the Department of Electrical and Electronic Engineering, University of Oviedo, where he is currently an Associate Professor. His research interests include dc-to-dc switching converters, modeling of magnetic devices for high-frequency switching converters, and industrial control systems.