Improved Power Performance for a Recessed-Gate ... - IEEE Xplore

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 52, NO. 11, NOVEMBER 2004

Improved Power Performance for a Recessed-Gate AlGaN–GaN Heterojunction FET With a Field-Modulating Plate Yasuhiro Okamoto, Member, IEEE, Yuji Ando, Member, IEEE, Koji Hataya, Tatsuo Nakayama, Hironobu Miyamoto, Takashi Inoue, Member, IEEE, Masanobu Senda, Koji Hirata, Masayoshi Kosaki, Naoki Shibata, and Masaaki Kuzuhara, Senior Member, IEEE

Abstract—A recessed-gate AlGaN–GaN field-modulating plate (FP) field-effect transistor (FET) was successfully fabricated on an SiC substrate. By employing a recessed-gate structure on an FP FET, the transconductance was increased from 150 to 270 mS/mm, leading to an improvement in gain characteristics, and current collapse was minimized. At 2 GHz, a 48-mm-wide recessed FP FET exhibited a record output power of 230 W (4.8 W/mm) with 67% power-added efficiency and 9.5-dB linear gain with a drain bias of 53 V. Index Terms—Field-effect transistor (FET), field-modulating plate (FP), GaN, recess. Fig. 1. Schematic of fabricated AlGaN–GaN FP FET with recessed-gate structure.

I. INTRODUCTION

T

HE AlGaN-based field-effect transistor (FET) is attracting increased attention because of its great potential for high-voltage microwave power applications [1]–[6]. It is widely recognized that power performance of GaN-based microwave FETs operated under high-voltage and large-signal conditions is limited by an undesirable effect of current collapse, which accompanies drain current reduction resulting from electron trapping at the surface states [1], [2]. SiN was found to be a good surface passivation film to mitigate this undesirable effect [1], [2]. The collapse-free FET with SiN passivation, however, exhibited significant degradation in the gate–drain breakdown voltage [1]. This tradeoff relation between current collapse and breakdown characteristics has been known as a main difficulty for realizing high-voltage operation

with a GaN-based FET. To improve this tradeoff relation, we have introduced a field-modulating plate (FP) technology [7] to power AlGaN–GaN FETs [8], [9]. Although suppressed current collapse and high breakdown voltage exceeding 150 V have been achieved with an FP structure, the increased feedback capacitance of an FP resulted in relatively low-gain characteristics. In this study, a recessed-gate structure [10]–[13] was applied to improve transconductance and gain characteristics in an AlGaN–GaN FP FET. The developed FP FET with a recessed-gate structure demonstrated a record total output power of 230 W. II. DEVICE STRUCTURE AND FABRICATION

Manuscript received April 21, 2004; revised June 16, 2004. This work was supported by the New Energy and Industrial Technology Development Organization under the High-Power, High-Frequency Gallium Nitride Device Project. Y. Okamoto, Y. Ando, T. Nakayama, H. Miyamoto, and T. Inoue are with the Advanced High Frequency (HF) Device Research and Development (R&D) Center, R&D Association for Future Electron Devices, System Devices Research Laboratories, NEC Corporation, Shiga 520-0833, Japan. K. Hataya was with the Advanced HF Device R&D Center, R&D Association for Future Electron Devices, System Devices Research Laboratories, NEC Corporation, Shiga 520-0833, Japan. He is now with The Furukawa Electric Company Ltd., Yokohama 220-0073, Japan. M. Senda, K. Hirata, M. Kosaki, and N. Shibata are with the Advanced HF Device R&D Center, R&D Association for Future Electron Devices, Optoelectronics Technical Division, Toyoda Gosei Company Ltd., Aichi 490-1312, Japan. M. Kuzuhara was with the Advanced HF Device R&D Center, R&D Association for Future Electron Devices, System Devices Research Laboratories, NEC Corporation, Shiga 520-0833, Japan. He is now with the Department of Electrical and Electronics Engineering, University of Fukui, Fukui 910-8507, Japan. Digital Object Identifier 10.1109/TMTT.2004.837159

The AlGaN–GaN heterojunction FET developed in this study is schematically shown in Fig. 1. An undoped AlGaN–GaN heterostructure was grown on an SiC substrate using metal–organic chemical vapor deposition. Source and drain ohmic electrodes were formed by evaporating Ti–Al–Mo–Au [14], which was then alloyed using rapid thermal annealing at 850 C. The contact resistance evaluated by transmission-line mm. matrix (TLM) measurements was in the range of 1–1.5 A good isolation resistance of over 10 square was achieved by nitrogen ion implantation. SiN was then deposited using plasma-enhanced chemical vapor deposition. After a gate footprint was opened through the SiN film, gate recess etching was performed using BCl plasma. – measurements performed on Schottky diodes with various etching times showed that an etching time of 60 s resulted in a threshold voltage shift of approximately 2 V, corresponding to an etching rate of

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OKAMOTO et al.: IMPROVED POWER PERFORMANCE FOR RECESSED-GATE AlGaN–GaN HETEROJUNCTION FET

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Fig. 3. Schematic drain I –V characteristics with a drain bias sweeping (10 V) range of: (a) 10 and (b) 80 V. The CF is defined as (I I (80 V))= (10 V).

0

Fig. 2. Transconductance as a function of gate voltage for a recessed FP FET with various recess depth.

TABLE I RELATION BETWEEN DEVICE STRUCTURE AND CF VALUE

14 nm/min. A recess depth of 21 nm was selected, while FETs with recess depths of 0 (without recess etching), 14, and 28 nm were fabricated for comparison. Ni–Au was used as a gate electrode material and its gate length was chosen to be 1.0 m. The drain-side edge of the gate electrode overlaps the SiN film, which operates as an FP. After completing gate metallization, the device was passivated with an SiN film and provided with a standard Au-plated air-bridge process to complete a multifingered FET. For high-power evaluation, the substrate was thinned to 50 m by mechanical polishing and its backside was coated with Ti–Pt–Au. III. DC AND SMALL-SIGNAL CHARACTERISTICS Fig. 2 shows transfer characteristics for recessed FP FETs with three recess depths. Maximum transconductance for recessed FP FETs, which tended to increase with increasing etching times, was 240, 270, and 350 mS/mm for recess depths of 14, 21, and 28 nm, respectively. Remarkable improvement in transconductance was realized for each of the recessed FP FETs, as compared to that of 150 mS/mm for a planar FP FET. On the other hand, maximum drain current for the recess depths of 14 and 21 nm remained as large as that for the planar FP FET (0.8 A/mm), while 30% reduction in maximum drain current was observed for a recess depth of 28 nm. Maximum drain current is fundamentally independent of AlGaN thickness under the gate because it is determined by a conduction band offset between AlGaN and GaN. For a recess depth of 28 nm, however, enough positive voltage cannot be applied to obtain possible maximum drain current. A recess depth of 21 nm was chosen as an optimum value that maintained maximum drain current with highest transconductance. Due to one-order reduction in the reverse gate leakage by applying a recessed-gate structure, the gate–drain breakdown voltage defined at 1 mA/mm was improved from 160 V for the planar FP FET to 200 V for the recessed FP FET. To investigate the effect of gate recessing and the FP on current collapse, we have compared – characteristics measured at a gate voltage of 2 V using a 60-Hz curve tracer with two different drain bias sweeping ranges, i.e., one from 0 to 10 V and the other from 0 to 80 V, as shown in Fig. 3. The collapse factor

Fig. 4. Dependence of MSG on drain bias for recessed FP FET with various recess depths.

10 V 80 V 10 V , (CF) was defined by 10 V and 80 V are the maximum drain curwhere rent value for the 10- and 80-V swing, respectively. The relation between the device structure and CF value was summarized in Table I. The CF value was reduced from 22% to 4% by applying an FP structure and to 1% by adding a recessed-gate structure. These experimental results indicate that the use of an FP electrode is of primary importance in suppressing a major part of current collapse and the additional gate recess is effective in further minimizing the residual current collapse. Small-signal characteristics for a 100- m-wide recessed FP FET were determined by on-wafer -parameter measurements. The maximum stable gain (MSG) evaluated at 2 GHz improved with increasing recess etching time due to an increase in transconductance, as shown in Fig. 4. An appreciable increase in the MSG was also observed with an increase in the drain bias because the additional gate feedback capacitance associated with the FP electrode was reduced at high drain-bias voltages [13].

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Fig. 5. Output power, gain, and PAE for 4-mm-wide recessed FP FET as a function of input power.

Fig. 7. Improvement in IMD3 characteristics by optimization of matching condition.

Fig. 6. Third-order intermodulation and PAE for 4-mm-wide recessed FP FET as a function of backoff value from saturated output power at drain-bias voltages of 25, 35, and 48 V.

Fig. 8. Output power, linear gain, and PAE for 48-mm-wide FP FET as a function of input power at a drain-bias voltage of 53 V.

IV. POWER PERFORMANCE A unit-cell recessed FP FET with a total gatewidth of 4 mm was mounted on a ceramic carrier and its power performance was evaluated at 2 GHz with external input and output matching circuits. The source impedance was adjusted to maximize the linear gain and the load impedance was matched to maximize the output power. Fig. 5 shows output power, gain, and poweradded efficiency (PAE) as a function of input power. At a drainbias voltage of 48 V, the 4-mm-wide recessed FP FET exhibited an output power of 28.4 W (7.1 W/mm) with a linear gain of 16.1 dB and PAE of 76%. Linearity was tested using two-tone signals with a frequency spacing of 1 MHz. Fig. 6 shows thirdorder intermodulation distortion (IMD3) and PAE as a func) at tion of backoff value from the saturated output power ( drain-bias voltages of 25, 35, and 48 V. IMD3 tends to decrease with an increase in the drain-bias voltage at a backoff value larger than 10 dB, while PAE depends slightly on drain-bias voltages. For further improvement in IMD3, external matching circuits were optimized at a drain bias of 48 V. Fig. 7 shows IMD3 and PAE as a function of the backoff value from with matching conditions of maximized output power and minimized IMD3. By optimizing the matching condition, IMD3 was drastically improved and exhibited a monotonic decrease with , linear gain, increasing backoff value, while degradation in and maximum PAE was 0.4 and 1 dB and two percentage points,

respectively. IMD3 of 35 dBc was obtained with a PAE of 30% . at 8-dB backoff from To demonstrate much higher absolute output power, power measurements were performed on a multicell recessed FP FET. Fig. 8 presents the output power, gain, and PAE as a function of input power for a 48-mm-wide recessed FP FET biased at a drain voltage of 53 V. An output power of 230 W (4.8 W/mm) was obtained with a linear gain of 9.5 dB and PAE of 67%. To the best of our knowledge, 230-W output power is the highest ever achieved for any single-chip FET device. Note that the power density of 4.8 W/mm for the multicell FET is much lower than that for the unit-cell FET. These results suggest that much higher absolute output power would be obtained by improving the uniformity of device parameters over the chip area and providing adequate thermal managements. V. CONCLUSION A recessed-gate AlGaN–GaN FP FET has been successfully fabricated on an SiC substrate. By employing a recessed-gate structure on the FP FET, the transconductance was increased from 150 to 270 mS/mm, leading to an improvement in linear gain. A recess depth of 21 nm was chosen as an optimum value that maintained maximum drain current with highest transconductance. The gate breakdown voltage was improved from 160 V for the planar FP FET to 200 V for the recessed FP FET, resulting from one-order reduction in reverse gate

OKAMOTO et al.: IMPROVED POWER PERFORMANCE FOR RECESSED-GATE AlGaN–GaN HETEROJUNCTION FET

leakage. In addition, current collapse was minimized by introducing the recessed-gate structure. An IMD3 of 35 dBc was obtained with a PAE of 30% at 8-dB backoff from saturated output power for a 4-mm-wide recessed FP FET. At 2 GHz, a 48-mm-wide recessed FP FET exhibited an output power of 230 W (4.8 W/mm) with a 67% PAE and a 9.5-dB linear gain with a drain bias of 53 V. To the best of our knowledge, the saturated output power of 230 W is the highest ever achieved for any single-chip FET device.

ACKNOWLEDGMENT The authors would like to thank Prof. Y. Nanishi, Ritsumeikan University, Kusatsu, Japan, Dr. M. Mizuta, NEC Corporation, Kawasaki, Japan, and Dr. H. Okumura, AIST, Tsukuba, Japan, for their support. The authors also thank Prof. A. Suzuki, Ritsumeikan University, for valuable discussions.

REFERENCES [1] Y. Ando, Y. Okamoto, H. Miyamoto, N. Hayama, T. Nakayama, K. Kasahara, and M. Kuzuhara, “A110-W AlGaN/GaN heterojunction FET on thinned sapphire substrate,” in Int. Electron Devices Meeting Tech. Dig., Dec. 2001, pp. 381–384. [2] U. K. Mishra, P. Parikh, and Y.-F. Wu, “AlGaN/GaN HEMTs—An overview of device operation and application,” Proc. IEEE, vol. 90, pp. 1022–1031, June 2002. [3] W. L. Pribble, J. W. Palmour, S. T. Sheppard, R. P. Smith, S. T. Allen, T. J. Smith, Z. Ring, J. J. Sumakeris, A. W. Saxler, and J. W. Milligan, “Application of SiC MESFET’s and GaN HEMT’s in power amplifier design,” in IEEE MTT-S Int. Microwave Symp. Dig., June 2002, pp. 1819–1822. [4] L. F. Eastman, “Experimental power-frequency limits of AlGaN/GaN HEMT’s,” in IEEE MTT-S Int. Microwave Symp. Dig., June 2002, pp. 2273–2275. [5] K. Joshin, T. Kikkawa, H. Hayashi, T. Maniwa, S. Yokokawa, M. Yokokawa, N. Adachi, and M. Takikawa, “A 174 W high-efficiency GaN HEMT power amplifier for W-CDMA base station applications,” in Int. Electron Devices Meeting Tech. Dig., Dec. 2003, pp. 983–985. [6] Y.-F. Wu, P. M. Chavarkar, M. Moore, P. Parikh, and U. K. Mishra, “Bias-dependent performance of high-power AlGaN/GaN HEMTs,” in Int. Electron Devices Meeting Tech. Dig., Dec. 2001, pp. 375–377. [7] K. Asano, Y. Miyoshi, K. Ishikura, Y. Nashimoto, M. Kuzuhara, and M. Mizuta, “Novel high power AlGaAs/GaAs HFET with a field-modulating plate operated at 35 V drain voltage,” in Int. Electron Devices Meeting Tech. Dig., Dec. 1998, pp. 59–62. [8] Y. Ando, Y. Okamoto, H. Miyamoto, T. Nakayama, T. Inoue, and M. Kuzuhara, “10-W/mm AlGaN/GaN HFET with a field modulating plate,” IEEE Electron Device Lett., vol. 24, pp. 289–291, May 2003. [9] Y. Okamoto, Y. Ando, K. Hataya, H. Miyamoto, T. Nakayama, T. Inoue, and M. Kuzuhara, “A 96 W AlGaN/GaN heterojunction FET with a field-modulating plate,” Electron. Lett., vol. 39, pp. 1474–1475, 2003. [10] I. Adesida, “High performance recessed gate AlGaN/GaN HEMT’s on sapphire,” Heterostructure Materials Topical Workshop Abstracts, pp. 102–103, Jan. 2003. [11] Y. Ando, Y. Okamoto, K. Hataya, T. Nakayama, H. Miyamoto, T. Inoue, and M. Kuzuhara, “12 W/mm recessed-gate AlGaN/GaN heterojunction field-plate FET,” in Int. Electron Devices Meeting Tech. Dig., Dec. 2003, pp. 563–566. [12] Y. Okamoto, Y. Ando, K. Hataya, T. Nakayama, H. Miyamoto, T. Inoue, M. Senda, K. Hirata, M. Kosaki, N. Shibata, and M. Kuzuhara, “A 149 W recessed-gate AlGaN/GaN FP-FET,” in IEEE MTT-S Int. Microwave Symp. Dig., June 2004, pp. 1351–1354. [13] Y. Okamoto, Y. Ando, T. Nakayama, K. Hataya, H. Miyamoto, T. Inoue, M. Senda, K. Hirata, M. Kosaki, N. Shibata, and M. Kuzuhara, “High-power recessed-gate AlGaN/GaN heterojunction FET with a field-modulating plate,” IEEE Trans. Electron Devices, submitted for publication.

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[14] V. Kumar, L. Zhou, D. Selvanathan, and I. Adesida, “Thermally-stable low-resistance Ti/Al/Mo/Au multilayer ohmic contacts on n-GaN,” J. Appl. Phys., vol. 92, pp. 1712–1714, 2002.

Yasuhiro Okamoto (M’02) received the B.S. and M.S. degrees in geology and mineralogy from Kyoto University, Kyoto, Japan, in 1989 and 1991, respectively. In 1991, he joined the NEC Corporation, Kawasaki, Japan. From 1991 to 2000, he was engaged in the research and development of GaAs power amplifiers. Since 2000, he has been engaged in the research and development of GaN-based FETs with the Photonic and Wireless Devices Research Laboratories, NEC Corporation. He is currently with the Research and Development (R&D) Association for Future Electron Devices, Shiga, Japan. Mr. Okamoto is a member of the IEEE Electron Devices Society.

Yuji Ando (M’99) received the B.S. degree in applied physics from the University of Tokyo, Tokyo, Japan, in 1985. In 1985, he joined the NEC Corporation, Kawasaki, Japan, where he has been engaged in the research and development of III–V compound semiconductor devices. From September 1991 to September 1992, he was a Visiting Researcher with the Institut d’electronique et de microelectronique du nord, Universite de Lille I, Villeneuve d’Ascq, France. He is currently with the Research and Development (R&D) Association for Future Electron Devices, Shiga, Japan. His research interests are modeling and characterization of heterojunction devices for application in the microwave and millimeter-wave range. Mr. Ando is a member of the IEEE Electron Devices Society, the IEEE Microwave Theory and Techniques Society (IEEE MTT-S), and the Japan Society of Applied Physics.

Koji Hataya received the B.E. degree in applied chemistry from Keio University, Tokyo, Japan, in 1991, and the M.S. degree in electronic chemistry from the Tokyo Institute of Technology, Tokyo, Japan, in 1993. In 1993, he joined the Yokohama Research and Development (R&D) Laboratories, The Furukawa Electric Company Ltd., Yokohama, Japan. In 2002, he was engaged in research and development for GaN-based FETs with the R&D Association for Future Electron Devices, Shiga, Japan. He is currently with The Furukawa Electric Company Ltd., Yokohama, Japan.

Tatsuo Nakayama received the B.S. degree in physics from Nagoya University, Aichi, Japan, in 1991. In 1991, he joined the NEC Corporation, Kawasaki, Japan, where he was engaged in the research and development (R&D) of GaAs and GaN FETs with the Photonic and Wireless Devices Research Laboratories. He is currently with the R&D Association for Future Electron Devices, Shiga, Japan. Mr. Nakayama is a member of the Japan Society of Applied Physics and the Japanese Association for Crystal Growth.

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Hironobu Miyamoto received the B.E. and M.E. degrees in electrical engineering from Hiroshima University, Hiroshima, Japan, in 1981 and 1983, respectively. In 1983, he joined the Central Research Laboratories, NEC Corporation, Kawasaki, Japan, where he has been engaged in research and development on III–V compound semiconductor devices. He is currently with the Research and Development (R&D) Association for Future Electron Devices, Shiga, Japan. His current research interests include epitaxial growth, processing, and fabrication of GaN FETs. Mr. Miyamoto is a member of the Japan Society of Applied Physics and the Japanese Association for Crystal Growth.

Takashi Inoue (M’04) received the B.S. degree in synthetic chemistry, B.E. degree in applied mathematics and physics, and M.E. degree in molecular engineering from Kyoto University, Kyoto, Japan, in 1983, 1985, and 1987, respectively. In 1987, he joined the NEC Corporation, Kawasaki, Japan, where he has been engaged in the research and development of magnetic random access memories (RAMs), superconductive integrated circuits (ICs), and monolithic microwave integrated circuits (MMICs) using III–V compound semiconductors. He is currently a Senior Researcher with the Advanced High-Frequency Device Research and Development (R&D) Center, R&D Association for Future Electron Devices, Shiga, Japan. His current interests include the research of gallium–nitride devices for use in millimeter-wave power applications. Mr. Inoue is a member of the Institute of Electronics, Information and Communication Engineers (IEICE), Japan.

Masanobu Senda received the B.E. and M.E. degrees in electronic engineering from Shizuoka University, Shizuoka, Japan, in 1985 and 1987, respectively. In 1987, he joined the Toyoda Gosei Company Ltd., Aichi, Japan, where he was engaged in the development of organic and inorganic thin films using the physical vapor deposition (PVD) method. Since 1999, he has been involved with light-emitting devices using GaN and related materials. He also develops epitaxial growth technology of GaN for electronic devices.

Koji Hirata graduated from the Nippon Engineering College, Tokyo, Japan, in 1989. In 1989, he joined Hitachi ULSI Engineering (currently Hitachi ULSI Systems). From 1989 to 1991, he was engaged in the process development of FETs. From 1992 to 2002, he was engaged in the development and characterization of GaAs HBTs. In 2002, he joined the Toyoda Gosei Company Ltd., Aichi, Japan, where he currently develops epitaxial growth technology of GaN and related materials.

Masayoshi Kosaki received the B.E. and M.E. degrees in electrical and electronic engineering from Meijo University, Nagoya, Japan, in 2000 and 2002, respectively. His research project concerned GaN material using MOVPE. In 2002, he joined the Toyoda Gosei Company Ltd., Aichi, Japan, where he has been engaged in the development of epitaxial growth technology of GaN and related materials.

Naoki Shibata received the B.S. degree in physics, and the M.E. and Ph.D. degrees in engineering from the Tokyo Institute of Technology, Tokyo, Japan, in 1983, 1985, and 1988, respectively. From 1988 to 1993, he was a Research Scientist with the Eastman Kodak Japan Research and Development (R&D) Center, Yokohama, Japan. His research was focused on the development of a light source of an LED printhead using AlGaAs. In 1993, he joined the Toyoda Gosei Company Ltd., Aichi, Japan, where he is currently a General Manager of the Optoelectronics Technical Department. His current research concerns the development of high-quality LED chips and lamps with a range from purple to blue to green using GaN and its related materials, and the development of applications using the LED such as a white LED, air purifier, illumination, and LCD backlight. He is also involved with the development of epitaxial growth technology of GaN for electronic devices.

Masaaki Kuzuhara (M’82–SM’01) received the B.E., M.E., and Ph.D. degrees in electrical engineering from Kyoto University, Kyoto, Japan, in 1979, 1981, and 1991, respectively. From 1981 to 2004, he was with the Central Research Laboratories, NEC Corporation, Kawasaki, Japan, where he was involved with GaAs ion-implantation processes, high-speed III–V heterojunction devices and their integrated circuits, and GaN-based high-frequency devices. From 1987 to 1988, he was a Visiting Researcher with the University of Illinois at Urbana-Champaign, where he was involved with the modeling and simulation of heterojunction devices using the Monte Carlo approach. Since 2004, he has been with the Department of Electrical and Electronics Engineering, University of Fukui, Fukui, Japan, where he is currently a Professor. Dr. Kuzuhara is a member of the Institute of Electronics, Information and Communication Engineers (IEICE), Japan, and the Japan Society of Applied Physics. He was the recipient of the 2002 Ichimura Prize presented by the New Technology Development Foundation.