Impulse Signal Generation and Measurement Technique for Cost-Effective Built-In Self Test in Analog Mixed-Signal Systems Wimol San-Um and Tachibana Masayoshi Kochi University of Technology, Tosayamada, Kami-City, Kochi, 782-8502, Japan, Tel: +81-887-57-2212, E-Mail Adress:
[email protected],
[email protected] Abstract This paper presents an impulse signal generation and measurement technique for cost-effective Built-In Self Test (BIST) in analog mixed-signal systems. The testing technique is based on a single effective sampling point of impulse responses. This technique offers high fault coverage and a high speed testing process, and eliminates the need for high-precision analog stimuli and complicated fault characterization algorithms. The BIST is relatively compact, implemented by a delay line and a track-andhold circuit with window comparator. No fault-free bit streams and digital processing units are required. Trails of the BIST system for the 8th-order Sallen-Key lowpass filter using 0.18-μm CMOS technology show a low area overhead of 11.19%. High fault coverage of 98.24% for both catastrophic faults and parameter variations was achieved.
1. Introduction Built-In Self Test (BIST), in which both stimulus generation and response analysis are accomplished entirely on-chip, has received considerable attention as a means of reducing testing time and eliminating the necessity for external test equipment. Several early BIST techniques have been applied successfully in digital circuits through stuck-at fault models and test pattern analysis. However, BIST techniques for analog circuit testing are costly and complicated owing to indecipherable fault models and vulnerability to performance degradation. Accordingly, BIST designs for analog circuits have recently attracted research activity. Fig.1 shows a generalised analog mixed-signal BIST block diagram with two essential test functions: (a) test stimulus generation and (b) output response analysis. As depicted in Fig.1 (a), the type of test stimulus generally determines fault detection strategy and hence the overall circuit design. A sinusoidal stimulus has been utilized extensively as fault signatures can be monitored effectively through circuit functions such as AC gain and frequency responses. However, the generation of high precision sinusoidal stimuli on chip, for example linear feedback shift registers (LFSR) [1] and stored bit streams with lowpass filtering [2], is relatively complicated and required much hardware. An impulse test stimulus, such as pseudo-random pulse sequence [3] and step-response based impulse generator [4], has been proposed as an alternative to the sinusoidal test stimulus. The impulse stimulus eliminates the need for high-precision sinusoidal stimulus generation and is suitable for linear Time Invariant (LTI) circuits. Nonetheless, fault extraction by means of de-convolution [5], cross-correlation [6] and linear regression [4] techniques necessitates specific frequency domain algorithms and consequently requires complex built-in hardware unless external DSP is exploited. As shown in Fig.1 (b), the response analysis process initially captures fault signatures, which are subsequently employed for fault detection. This response analysis process can be considered in two aspects, i.e. time-based and voltage-based fault analysis techniques.
978-1-4244-4480-9/09/$25.00 ©2009 IEEE
1195
(a) Stimulus Generation
(b) Output Response Characterization
Waveform Generator
Analog CUT
Input Control Circuits
Synchronizations
Output Capturing Circuit
Fault Detection Circuit
P/F Test Output
Output Control Circuits and Stored Fault-Free Bit Stream
(c) Control Circuitry
Figure 1. Generalized scheme of BIST for the testing of analog circuits embedded in mixed-signal systems. On the one hand, time-based techniques convert instantaneous analog signals into digital signals using a 1-bit digitiser [7] or ΣΔ A/D converter [8], and subsequently detect faults by means of digital counters or digital comparators, incorporating stored faultfree bit streams. Despite the fact that these time-based techniques offer expedience in the comparison process and storage of fault signatures in the digital domain, the implementation of A/D converters and digital counters is relatively complicated, resulting in hardware overhead and ultimately necessitating fault testing. On the other hand, voltage-based techniques [9] capture voltage samples through sampling process and detect faults by means of voltage comparison through specification tolerance margins. These voltage-based techniques have been realized extensively in most cost-effective BIST systems, as faults can be detected instantaneously and effectively, yielding low area overhead, especially in LSI or ASIC applications. However, effective sampling methods of specific input test stimuli types are difficult to achieve due to complexities such as the realization of a phaselocked or delay-locked loops. It can also be seen from Fig.1 (c) that test control circuitry with test instruction signals is required in order to facilitate execution of self-testing feature, and is generally accomplished in existing digital portions of mixed-signal system. Synchronization of input and output control circuits and a fault-free bit stream stored in system memory unit are necessary in most BIST techniques. Giving consideration to this generalized BIST scheme, this paper presents an impulse signal generation and measurement technique. The testing technique is based on the sampling of impulse response at a single effective point, offering high fault coverage and eliminating the need for high-precision analog stimuli with complicated fault characterization algorithms. The BIST implementation is the early setting of both pulse generation and sampling clock signals and therefore fault-free bit streams, synchronization process and digital processing units are not required. This paper is organized as follows: Section II shows the details of the proposed impulse response sampling technique using defect-oriented fault evaluations. Section III describes the BIST system implementation and design considerations. Physical level implementations and simulation results are demonstrated in Section IV. Finally, discussion and conclusion are provided in Section V.
2. Impulse Response Sampling Technique
Linear RC Network
In order to investigate the fault impacts on impulse response characteristics and to evaluate that the impulse response can provide sufficient information for fault detection process, defect-oriented simulations were primarily conducted. Fig.2 shows the circuit configuration of a 2nd-order Sallen-Key lowpass filter, employed as a Circuit-Under-Test (CUT). This CUT was designed for a cut-off frequency of 500kHz and a unity quality. The resistors R1 and R2 were equally set at 80 kΩ, and the capacitors C1 and C2 are equal to 8pF and 2pF, respectively. The width of a rectangular input impulse was set at 0.5μs such that the impulse response possesses a narrow and symmetric shape. Fault injection of each single catastrophic and parametric fault was performed at one time using the resistor insertion technique. In the case of catastrophic faults, shorts were modelled by inserting a small 1-Ω resistor in parallel between each pair of component terminals while opens were modelled by inserting a large 10-MΩ resistor in series between two disconnecting terminals. In the case of parametric faults, the variation of 10% in resistor and capacitor values was realized. Consequently, the total number of 57 faults was investigated, including 19 faults in the RC network and 38 faults in the unitygain buffer. The discrimination of detected and undetected faults was accomplished by means of window criterion, i.e. the number of detected faults was counted as when the voltage at any measuring points exceeds window criterion margins. The entire propagation time of impulse responses was divided into six partitions in order to investigate five approximate measuring points, involving points p1 and p2 on the rising period, the maximum point p3, and points p4 and p5 on the decreasing period. Consequently, five window criterions denoted as W1 to W5 were realized for measuring the respective voltages v1 to v5. These window criterion margins were determined by a general consideration of ±5% tolerance, involving the variation of linear components R1, R2, C1, C2 and transistor threshold voltage. In order to cover all types of existing faults, minimum and maximum margins of each window criterion were obtained by the worse-case boundary method, i.e. the smallest intervals of minimum and maximum tolerances obtained from all associated component variations. Fig. 3 shows five particular examples of deformed impulse responses caused by fault influences. The variation of 10% in C1 and R1 results in small changes of impulse response shapes by introducing the decrease in the maximum value and the dispersion of discharging period. Drain open (DO) at M2, Gate-Drain Short (GDS) at M3 and potential open at C1 result in stuck-at-VDD, stuckat-GND, and distorted impulse responses, respectively. As expected, parametric faults cause small deviation on impulse responses whereas catastrophic faults cause circuit function failures as reflected by tremendous changes on impulse responses. Fig. 3 also demonstrates the Venn diagram on five sets of detected faults at window criterions W1 to W5 as a summary of a complete fault injection process. It is seen from the Venn diagram that all 57 faults were detected, revealing that the use of the impulse signal as an input test stimulus provide sufficient information for fault detection. In addition, the number of 50 faults was detected at the five measuring points, indicating that random fault detection at these five points can achieve the minimum fault coverage of 87.72%. Importantly, all 57 faults were detected at the point p5, providing the fault coverage of 100%. Thus, monitoring and capturing fault signatures at only the point p5 is sufficient and effective, leading to simple circuit designs and implementations. The point p5 is effective for fault monitoring since the discharging period dispersion is a response to a finite-width rectangular input impulse signal determined by the variation in resistors and
1196
Unity-Gain Buffer VDD M5
VB
vi
R1
R2
C1
M1
C2
M6
vo
M2
M3
M4
M7
Figure 2. Circuit configuration of a second-order Sallen-Key low-pass filter. 2.0V Input Impulse Normal Response R1 : -10% Var. C1 : +10% Var. C1 : Open M2 : DO M3 : GDS
1.6V
1.2V
1
W3 p3(t3,v3) W2 p2(t2,v2)
0V
0.5us
1.0us
W4 W5
2 1 1
1 1
W3
Discharging Period Dispersion
W1 p1(t1,v1)
0s
50
U = 57 W4 p4(t4,v4)
0.8V
0.4V
W2
W1
W5 p5(t5,v5)
1.5us
2.0us
2.5us
3.0us
3.5us
4.0us
Time (us)
Figure 3. Normal impulse response and five examples of fault signatures presented and Venn diagram of detected faults in those five sets of W1 to W5. capacitors. These characteristics are also common in most analog circuit types, depending on actual values of time constants. With the support of these defect-oriented evaluation results, the test strategy of this work is the monitoring of a voltage level at a single point on the impulse response during the discharging period. With reference to Fig.3, the voltage v5 can be measured at time t5, suggesting that the voltage can be captured through sampling process at the height of approximately h/4 where h is the maximum point of normal impulse response. In addition, all faulty impulse responses measured vertically at time t5 show evidence of significant differences in voltage values, suggesting that the widow criterion can be utilized for fault discriminations. As a result of this test strategy, the testing technique is the sampling of a voltage at the effective point on the impulse response and employs this sampled voltage for fault detection through the comparison with allowable tolerances.
3. Proposed BIST System Architecture Based on the generalised BIST scheme shown in Fig.1 and the proposed testing technique in Section II, Fig.4 depicts the block diagram of the proposed BIST system and timing waveforms. The targeting CUTs of this BIST system are analog portions in mixedsignal systems such as amplifiers and filters. It is primarily assumed that digital portions sufficiently provide memory units for the registration of control signals. Compact analog and digital circuits were utilized in the design of BIST building blocks in order to achieve low complexity and adequate area overhead. As can be seen from the block diagram shown in Fig.4, the test stimulus generation process was implemented by the impulse signal generator, and the output response characterization process was implemented by a track-and-hold (T/H) circuit with a window comparator. For the test stimulus generation process, Fig.5 demonstrates the circuit diagram of the rectangular impulse signal generator, implemented based on the delay time propagation of an input clock through a delay line. The phase detection circuit was realised for
(a) Stimulus Generation
vSPi
vSP Track-and-Hold
enb
Vmax Impulse Signal Generator
vIP
vIR
vSH
vCP
CH ck enb
Di
Dn
a0a1...an b0b1...bm
vIR
itda
VBP jtdb
vSP Vmin
vSH ck
tIRD tCKH
Da1
Da2
Dan
Db1
Db2
Dbn
b2
DLa
MP1
MP2
MN1
MN2
VBP
DLb bn
CG1
VBN
vSP
VBN2
vPF
VDD
R1
an
a2
b1
Dj
(b) Output Response Characterization
System Clock And Memory
a1
ck enb
vIP Analog CUTs
vIP
VBN1
To Scan Chain vPF
Window Comparator
Delay Element
vSH (Vmin,Vmax)
Figure 5. Block diagram of the rectangular impulse generation circuit and a circuit configuration of an active resistor based delay element.
tCKL
(c) Control Circuitry
Figure 4. Block diagram of the BIST system and timing waveforms.
VDD
generating small impulse signals through the comparison of low-tohigh state transition time using XOR gates. The circuit exploits the clock ck with a duty cycle of 0.5 as an input resource, and provides two signals vIR and vSP for use as the input stimulus and the sampling clock, respectively. The delay line path DLa, consisting of delay elements Da1 to Dan, provides the impulse signal vIP with controllable impulse width through the setting of the bias voltage VBN1 and the switches a1 to an. Similarly, the delay line DLb, consisting of delay elements Db1 to Dbn, provides the sampling clock vSP with controllable width through the setting of the bias voltage VBN2 and the switches b1 to bn. Despite the fact that these delay elements can generally be implemented using a threshold voltage of digital logic gates, the delay time of each logic gate is relatively small in the range of Picosecond. Consequently, the generation of microsecond-width rectangular impulses necessitates a vast number of delay stages, resulting in high power consumption and large area overhead. As demonstrated in Fig.5, the insertion of an active resistor at the input terminal of each delay stage was realized. The resistor R1 was implemented by a complementary switch, biased in linear region through bias voltages. This resistor R1 develops an inherent lowpass filter with the gate capacitance CG1 of the first inverter formed by transistors MN1 and MP1. This lowpass filter provides a large rising time of the input signal during low-to-high state transition, which is subsequently triggered by the second inverter formed by transistors MN2 and MP2. As a result of inserting R1, each delay stage of DLa and DLb provide sufficient delay time denoted as tDa and tDb , respectively, in the range of Microsecond. For the output response characterization process, Fig.6. shows the configurations of T/H and window comparator circuits. The T/H circuit was designed based on a unity-gain sampler, consisting of a sampling switch, a holding capacitor and a buffer amplifier. The sampling switch was implemented by a complementary switch in order to reduce on-resistance and clock-feedthrough errors. The holding capacitor CH was implemented by available on-chip linear capacitors. The optimised size of this CH for a reasonable trade-off between sampling speed and accuracy was found in the range of 0.3pF to 0.5pF. The buffer amplifier was implemented by a highbandwidth two-stage operational amplifier with phase compensation, comprising transistors M1 to M10. In addition, the voltage comparator comprises two simple differential amplifiers, consisting of transistor M11 to M20 and a single NAND gate, and reports pass/fail test outputs in the form of logical digital signals. For overall circuit controls and operations, Fig.4 also shows the timing waveforms of operating signals. Test operations can be accomplished in three procedures. Firstly, the impulse signal vIP with the specified impulse width of value itda is generated. As the delay time tda is set by each stage of Da1 to Dan, this specified impulse width of itda can be obtained from the ith-stage delay element (Dai), where i = 1,2,3…n, via the control signals a1 to an. Secondly, the CUT is stimulated by the applied signal vIP, and the impulse response vIR subsequently propagates over a limited period
1197
M10
M3
M4
M13
M7
vSP
CF
MSP
MSN
M1
M18
M19
vCP
vSH
M9
vIR
M14
Vmin
M2
M11
M12
M16
M17
Vmax
CH
M5
M6
M15
M8
M20
Window Comparator
Track-and-Hold Circuit
Figure 6. Circuit configurations of the track-and-hold and the window comparator circuits.
CUT 0.13 mm2
BIST
3,654 um2
Figure 7. Layout design of the CUT with BIST system.
of time. Finally, the impulse response vIR is sampled by the clock vSP and the voltage vSH is held instantly for the subsequent comparison process with Vmax and Vmin. The clock vSP can be acquired from the jth-stage (Dbj), where j = 1,2,3…n, via the control signals b1 to bn. The test output signal vPF is reported as Low (Gnd) for a fault-free CUT and High (VDD) for a faulty CUT. In addition, the test output vPF is obtained from AND operation between the signal vSPi, inverted from the signal vSP, and the compared output vCP. In this design, the number of delay stage determines the required frequency of the input clock ck. As the delay line DLb is dominant, the high time tCKH of the input clock ck is determined by the summation of the operating delay time jtdb and the extra delay time tIRD that provides small time for the simplicity of clock frequency setting through divisible integer. The clock high time tCKH is equal to jtdb + tIPD, and the resulting frequency of the clock ck is 1/(2tCKH) or 1/(2(jtdb + tIRD)).
4. Simulation Results Physical-level implementation was carried out using a 0.18-μm standard CMOS technology in Cadence environments, and simulations were performed through Hspice. The CUT was an 8thorder Sallen-Key low-pass filter, partitioned into four identical 2ndorder building blocks for the direct testing purposes. Fig.7 shows the layout of the CUT and the BIST system, occupying effective areas of 0.13mm2 and 3,654 μm2, respectively. The digital circuitry was excluded. Table 1 summarizes performance and parameter setting of each BIST building block. It can be seen from Table 1 that the inclusion of BIST exploits effective areas of 2.79% and 11.19%, compared to the 8th-order and 2nd-order filters, respectively. Frequency deviation, introduced by parasitic capacitances of BIST, was found at high frequency of 8MHz and at a very low gain of –98 dB, which are not in the filter specification. The input clock frequency was set at 250 KHz. The input impulse and the sampling
Table 1. Summary of performances and parameter setting. VIP
±10% R and C Var. Sh. and Op. in R and C
Undetected
8 7 1 11 11 0 Sh. and Op. in Transistors 38 38 0 Total 57 56 1 * sh. = Shorts, Op. = Opens, C = Capacitor, R = Resistor.
Faulty VSH
Time (us)
(d) Shorts and Opens in Transistors
VSP
VIP
Faulty VSH Fault-Free VSH
VSP
Voltage (V)
VIP
Time (us)
(c) Shorts and Opens in R and C
Faulty VSH Stuck-at-VDD
Fault-Free VSH
Time (us)
Time (us) (us) Time
Figure 8. Impulse response characteristics resulted from realistic faults. (a) Fault-Free Impulse Response Detection
VIP
Fault Coverage
87.5% 100% 100% 98.24%
VSP
(b) Faulty Impulse Response Detection
VIP Fault-Free VSH Fault-Free VIR
Voltage (V)
Detected
Faulty VSH
Fault-Free VSH
Voltage (V)
Types of Faults
VSP
Fault-Free VSH
Table 2. Total number of injected faults and resulting fault coverage. No. of Faults
(b) C : 10% variations
Voltage (V)
Units kHz dB mm2 μm2 % % V V kHz μs μs μs V V μs V V V V V %
Voltage (V)
Values 504.98 0 0.13 3,654 2.79 11.19 1.5 0.3 250 0.24 0.47 1.95 0.48
