The passive method requires a snubber circuit and this causes slow switching speed and introduces additional losses. The active methods require complicated ...
99IECEC-01-2599
Input Series-Output Parallel Connected Converter for High Voltage Power Conversion Applications Employing Charge Control Jung-Won Kim, J. S. You and B. H. Cho School of Electrical Engineering Seoul National University Seoul Korea
Copyright © 1999 Society of Automotive Engineers, Inc.
ABSTRACT In this paper, the charge control with the input voltage feed forward is proposed for the input series-output parallel connected converter configuration for highvoltage power conversion applications. This control scheme accomplishes the output current sharing for the output-parallel connected modules as well as the input voltage sharing for the input-series connected modules for all operating conditions including the transients. It also offers the robustness for the input voltage sharing control according to the component value mismatches among the modules.
I. INTRODUCTION In the field of high voltage power conversion the circuit designer is often confronted with a problem that there are no semiconductor devices capable of sustaining the required voltage and suitable for the desired switching speed. For this reason, several device-series connection methods and converter topologies are proposed. But the arising problem with device-series connection is the voltage balancing at the device turn-off. To get the voltage balancing, a passive or active balancing method is used. The passive method requires a snubber circuit and this causes slow switching speed and introduces additional losses. The active methods require complicated control circuits to get the voltage balancing [1-4]. And the control delay of the voltage-balancing controller [3,4] can increase the device stress, so the switching speed is restricted. Moreover, perfect balancing is hard to be accomplished during the switching transients. The problems mentioned above can be solved by the input series-output parallel-connected converter configuration. The input series-output parallel connected converter configuration has the input voltage balancing and the output current sharing requirements.
In this paper, the charge control with the input voltage feed forward scheme is proposed, which balances the input voltage sharing as well as the output current sharing for each module. With this scheme, the converter modular approach can be easily implemented for any types of converter topologies.
II. INPUT SERIES-OUTPUT PARALLEL CONNECTED CONVERTER CONFIGURATION Fig.1 shows the input series-output parallel connected converter configuration for high-voltage power conversion applications. Two modules are shown in this figure, but according to the input voltage range more modules can be series connected. Any topology can be used in this configuration if an isolation transformer is used in each module. In this configuration the input voltage is divided by the series connected input capacitors and the output is paralleled. The series connected converter experiences only divided input voltage so the device rating can be reduced. The input capacitors can be utilized as part of an input filter as shown in Fig.1.
Fig.1 Input series-output parallel connected converter configuration
In this system, there are two separate requirements for control: First, the load current must be shared equally by each output-paralleled module. Secondly, each inputseries module must share the input voltage equally.
the imbalance of the input capacitor voltage and the input capacitor voltage remains unbalanced. Module #1 Inductor Current [A] 20 10
For the output current sharing, a current mode control can be used. However if the output current is controlled to be the same between the two modules for example, then even a slight mismatch in the transformer causes the input current imbalance and this fails the input voltage sharing. Thus, the average input current of each module must be controlled instead of the output current. For the forward type converter shown in Fig.2, the charge controller directly controls the average input current. 114µH
i in1 4 :1
44.9µH
42.4mΩ
0
0.002
0.004 0.006 0.008 Module #2 Inductor Current [A]
0.01
0
0.002 0.004 0.006 0.008 Module #1 & #2 Input Capacitor Voltage [V]
0.01
0
0.002
0.01
20 10 0
200 100 0
io
0.004
0.006
0.008
[sec] Vo
30mΩ
Vc1
0.25Ω
10µF
0
2200µF
Fig.3 Simulation result of the charge capacitor mismatch
Vg Vc2
47.7µH
i in2
Module #1 Inductor Current [A]
567 . mΩ
20
12µF
10 0
External ramp
0
0.002
0.004 0.006 0.008 Module #2 Inductor Current [A]
0.01
0.002 0.004 0.006 0.008 Module #1 & #2 Input Capacitor Voltage [V]
0.01
0.002
0.01
20
d1
Mod#1
+
10
CT
Switch current per cycle charge
0
0
80
External ramp
70 60 0
d2
Mod#2
+
0.004
0.006
0.008
[sec]
CT
Switch current per cycle charge
Control Vc
Fig.2 Schematic of the input series-output parallel connected forward converter with the charge control
Fig.4 Simulation result of the input capacitor mismatch
III. CHARGE CONTROL WITH THE INPUT VOLTAGE FEEDBACK In order to solve the problems discussed above, the charge control employing the input voltage feedback scheme is proposed as shown in Fig.5.
However, the conventional charge control scheme still has the following problems for the input voltage sharing. If the component value mismatches in the switch current sensing circuit and the charge capacitor, CT, the average input current can be mismatched, which eventually causes the input voltage imbalance. Fig.3 simulates this case with the two-module forward converter system shown in Fig.2. In this simulation, there is 20% mismatch in the charge capacitors. As it is seen in this simulation, the imbalance in the input voltage causes the imbalance in the output current. Fig.4 illustrates the case where the value of the input voltage sharing capacitors is not perfectly matched. In this case the input capacitor voltage can be different during the transient. If the average input current of each module is the same, the voltage imbalance can never be fixed. Fig.4 simulates this case with the two-module forward converter system shown in Fig.2. The initial input voltage is 130V and steps up to 150V at 2ms and the initial load current is 20A and steps down to 10A at 7ms. The 20% imbalance of the input capacitors causes
i in1
io Vo
Vc1 Vg Vc2
i in2
External ramp
d1 Vc2 Vc1
+
Mod#1
k*(Vc1-Vc2)
+
Input capacitor voltage difference k*(Vc2-Vc1) Switch current per CT cycle charge
k*(Vc2-Vc1) External ramp
d2
Mod#2
+
Input capacitor voltage difference k*(Vc1-Vc2) Switch current per CT cycle charge
Control Vc
Fig.5 Proposed charge control scheme
The input current of each module is adjusted according to the input capacitor voltage to achieve the voltage balance between the modules for all operating conditions. In this scheme, the input voltage difference is multiplied by a gain, k and this controls the offset voltage in the duty ratio modulator
Module #1 Inductor Current [A]
20 10 0
0
0.002
0.004 0.006 0.008 Module #2 Inductor Current [A]
0.01
0
0.002 0.004 0.006 0.008 Module #1 & #2 Input Capacitor Voltage [V]
0.01
0.002
0.01
20 10
Control Vc Balanced Condition
0
Module #1
80
- k*(V1-V2)
Unbalanced Condition
∆ton1
70 60
Control Vc
0
0.004
[sec]
0.006
0.008
Module #2
Fig.7 Simulation result of the proposed scheme
+ k*(V1-V2)
∆ton2
IV. SMALL SIGANL ANAYSIS
when V1 > V2
Fig.6 Balancing mechanism of the proposed method Fig.6 illustrates the balancing mechanism of the proposed method when v1 is higher than v2. Because of the lowered offset voltage, -k*(v1-v2), module 1 input current increases and this increased input current makes input capacitor voltage decrease. On the other hand, module 2 input current decreases owing to the raised offset voltage, +k*(v1-v2), and this reduced input current makes input capacitor voltage increase. In this way v1 and v2 becomes equal and the power balance of two modules is accomplished. The amount of the difference in the input average current to balance the input voltage during the transient can be calculated by Eq.(1). ∆Vin max k ∆I in max = 2 ⋅ ⋅ C T n ∆t on
(1)
where, ∆Vin max is the maximum of the input capacitor voltage difference, CT is the charge control capacitor, ∆t on is the on-time of the switch, n is the turns ratio of current transformer and k is the gain of the differential amplifier of the input voltages. The higher the gain k, the larger ∆Iin max is , and lower the gain k makes ∆Iin max small but it takes longer time to reach the balanced steady state of the input capacitor voltages. Therefore, there must be a design trade-off for the gain, k between the current rating of the converter and the settling time. Fig.7 shows the simulation result of the proposed scheme. There is 20% mismatch in the charge capacitor and in the input capacitor. The initial input voltage is 130V and steps up to 150V at 2ms and the initial load current is 20A and steps down to 10A at 7ms. As shown in this figure, to achieve the balance of the input capacitor voltage the input average currents are controlled to be different during the transient.
Fig.8 shows the small-signal equivalent circuit of a twomodule ISOP (input series output parallel) converter system. In this figure, all switches are replaced with its small-signal PWM model [8]. Rp 1:N1
1:D1
Lp I1dˆ1
C1
Rc
R
C 1:D2
I 2dˆ 2
Rl1
Vc1N1 ˆ d1 D1
1:N2
C2
L1
L1
Rl1
Vc2 N 2 ˆ d2 D2
Fig.8 Small signal equivalent circuit model of ISOP system using PWM switch model The ISOP system uses input capacitor voltage as the control information for input capacitor voltage balancing. The input capacitor voltages adds new states to the system model and the overall small signal model can be completed adding this two input capacitor voltage feedback loop to the general two loop controlled parallel converter system. The overall small signal block diagram of the ISOP system including this control loop is shown in Fig.9. In Fig.9, Ri and FM are the equivalent current gain and the modulator gain, respectively. He(s) represents the sampled-and-hold effect in the current loop [9] and k represents the sensing gain of the input voltage difference. In order to obtain design information of the control loop for stability, it is necessary to simplify the system model in Fig.9. Since the system has additional input voltage feedback loops to the conventional current mode controlled parallel module system, the influence of the feedback loop is analyzed.
vˆ g iˆo
Ggo Zo
vˆo
ISOP system can be simplified to a equivalent single module, and its block diagram is shown in Fig.11. Where,
vˆc1
G dvo = 2G d1o , Ri ' = Ri / 2 , G di = 2(G d1i1 + G d 2 i1 ) (2)
Gd2o Gd1o
Gvc1 Gic1 Gd2c1 Gd1c1
Gvc2
vˆ g
vˆc2
Gic2
io
-Hv
Gd2c2
Gvgvo
Vˆo
Zo
Gd1c2
Gvi1
+
-
+
Gdvo
iˆin 1
Gii1 Gd2i1
Gvgi
iˆ l
Gd1i1
Gvi2
iˆin 2
Gii2
-Hv
Gioi k
k
Gd2i2
B
Ri1
Gd1i2
Gdi
Tv
Ri2
Ri'
He(s) He(s)
dˆ 2
Ti
FM2
-
+
dˆ 1
+
-
-
vc
FM
Fig.9 Overall small signal block diagram of ISOP system with input capacitor voltage feedback Fig.10 shows the transfer function from the control voltage, v c to the output voltage, v o (point B) in Fig.9 with and without the input capacitor voltage loop. As can be seen from this figure, the two plots are almost the same. This can be qualitatively interpreted as follows. Since amount of the input voltage feedback for each module is same but with opposite sign, there is a net canceling effect in the overall system.
Phase (deg); Magnitude (dB)
B
He
vc
FM1
+
Fig.11 Small signal block diagram of a equivalent single-module converter system
V. CONTROL LOOP DESIGN The first step of the current loop design is to determine the charge control capacitor, CT. The voltage across CT, should not exceed the comparator supply voltage v cs. Thus, CT is chosen as follows [9]:
40
CT >
20
(3)
1 D max Ts i L ,max ( t )dt ∫ vcs 0
FM, Ri and He(s) have the same expression as those in the conventional charge control [9]. The current loop gain, Ti in Fig.11 is then
0
-20 0
Ti = Ri'⋅He(s) ⋅ FM ⋅ G di
(4)
-50
-100
-150 1 10
2
10
3
10
4
10
5
10
6
10
Ti can be used for the stability analysis of the current loop closed power stage. Once the current loop is designed, the current loop closed power stage can be treated as a new power stage for the voltage loop design(Hv). The system loop gain defined at point B is
Frequency (rad/sec)
Fig.10 Transfer function from the control voltage to the output voltage with and without the input capacitor voltage feedback loop ( Gci ) Thus, we can conclude that the input capacitor voltage feedback loop has little effect on the control voltage to the output voltage transfer function at point B. Then the
TB = G ci ⋅ H v
(5)
where, G ci is the transfer function from the control voltage, v c to the output voltage, v o with the current loop closed (new power stage) for a given operating conditions. Fig.10 shows G Ci , from which the voltage loop compensator, Hv can be designed. For Hv, an
integrator plus two poles and two zeros compensator is used. H v (s ) =
K I (1 + s / ω z1 ) s (1 + s / ω p1 )
(6)
Fig. 12 shows the designed loop gain TB , which has a wide control bandwidth with an appropriate phase margin.
of the mismatches of the component values between the modules. Employing the charge control, the input average currents are controlled to be the same therefore the voltage imbalance is not fixed after the input voltage mismatch occurs. So the supplying power of two modules is unbalanced and one module suffers more stress than the other and this worsens the system reliability.
100
Phase (deg); Magnitude (dB)
50
0
-50 -50 -100
φ M = 60o
-150 -200 -250 1 10
2
10
3
10
4
10
5
10
6
10
Frequency (rad/sec)
Fig.12 Outer loop gain TB after the compensation
IV. EXPERIMENTAL RESULT To verify the effectiveness of the proposed control scheme, hardware experiments are performed. The experimental setup is the same as that of the previous simulation cases. Fig.13 shows an experimental result employing the conventional charge control scheme.
Fig.14 Experimental wave forms with proposed charge control scheme, [25V/div], [0.5s/div] Ch1, Ch2: input capacitor voltages of module #1, #2 Fig.14 shows an experimental result employing the proposed charge control scheme with the input voltage feed forward. The experimental condition is the same as that of Fig.13. In both the steady and transient states the perfect balance of the input capacitor voltages is achieved by the proposed control scheme. So the power balance between the two modules is accomplished by the proposed control scheme and the voltage stress is equally divided between the two modules. Fig.15 shows an expanded view of the input capacitor voltages and the inductor currents of the two modules during the input voltage step change.
Fig.13 Experimental wave forms with conventional charge control scheme, [25V/div], [0.5s/div] Ch1, Ch2: input capacitor voltage of module #1, #2 The input voltage steps up at 1.5s from 130V to 150V, steps down at 2.5s to 120V and steps up at 3.5s to 130V. The input capacitor of module #2 is 20% greater than that of module #1. The input voltage variation of module #1 during the transients, is greater than that of module #2 because of the smaller input capacitor. In the figure input voltage mismatch is observed not only in the steady state but also during the transients because
Fig.15 Experimental wave forms with proposed charge control scheme, [25V/div], [5A/div], [5ms/div] Ch1, Ch2: input capacitor voltages of module #1, #2 Ch3, Ch4: inductor currents of module #1, #2
The input voltage steps up from 130V to 150V at 10ms. Because the input capacitor of module #1 is smaller, the input capacitor voltage of module #1 goes higher than that of module #2. To balance the input capacitor voltage the proposed charge controller increases the input average current of module #1 and decreases the input average current of module #2.The current waveforms in Fig.15 verify the canceling effect for the output voltage control loop as discussed in section IV. In the figure the inductor currents are plotted instead of input average currents for the displaying convenience. There is about 2A difference between the inductor currents of the two modules to balance the input capacitor voltages.
V. CONCLUSION In this paper, the charge control with the input voltage feed forward is proposed for the input series-output parallel connected converter configuration for highvoltage power conversion applications. This control scheme accomplishes the output current sharing for the output-parallel connected modules as well as the input voltage sharing for the input-series connected modules for all operating conditions including the transients. It also offers the robustness for the input voltage sharing control according to the component value mismatches among the modules. The small signal analysis shows that an equivalent single module system can be used for the control loop design process in spite of the input capacitor voltage feedback loop. The performance of the proposed scheme is verified through the experimental results.
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9.
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