Comparison of Integrated SEPIC-Buck and SEPIC- C uk Converters as Off line Dimmable LED Drivers with Reduced Storage Capacitor M. R. Cosetin, E. A. Bitencourt, T. E. Bolzan, M. F. da Silva, 1. M. Alonso* and R. N. do Prado
FEDERAL UNIVERSITY OF SANTA MARIA - UFSM - BRAZIL * UNIVERSIDAD DE OVIEDO, DIEECS - TECNOLOGIA ELECTRONICA - SPAIN Av. Roraima n° 1000 - Cidade Universitaria - Bairro Camobi Santa Maria, Brasil
Tel.: +55 / (55) 3220 8000.
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Keywords
«Electronic ballast», «Integrated Circuit», «Lighting», Electrolytic Capacitor Substitution, LED Driver. Abstract
This paper presents comparison of two integrated DC-DC converters topologies, SEPlC-Buck and SEPlC-euk as off-line dimmable LED drivers from a storage capacitance reduction point of view. Considering the low lifetime of electrolytic capacitors compared to that of LEDs, this study presents an analysis and design of two topologies which allows replace electrolytic capacitor by longer lifetime capacitor technology. Therefore it is necessary a significant storage capacitance reduction which is possible due to the proposed output current control strategy. Moreover the integrated topologies are compared in terms of efficiency and storage capacitance reduction. Introduction
A considerable amount of electrical energy generated all over the world is converted in artificial lighting [1, 2]. The efficient utilization of this energy contextualizes the high-frequency electronic ballasts application for lighting. Furthermore, due to the features of the LED in terms of color rendering index, color temperature, size, robustness, reliability, luminous efficacy and lifetime, these devices have been used increasingly in general lighting [2-8]. However, traditional LED drivers use electrolytic capacitors which limit the overall system lifetime [3-8]. Electrolytic capacitors present a useful life between 1-18 kilohours in general [9, 10]. Meanwhile the LED reaches 80 kilohours under typical operating conditions [4]. Therefore these topologies aim for reducing the storage capacitance, replacing this component by a film capacitor, increasing the overall system lifetime. The reached capacitance value is smaller than any other high-frequency DC-DC converter topology found in the literature for the considered input and output parameters [5-8]. According to the IEC 61000-3-2 Standard, lighting systems require an adequate limit of input current harmonic content for power above 25 W [11]. The high-frequency DC-DC converters application has been proposed as an efficient method to perform the PFC [4-8, 12-14] for LED drivers. A simplified scheme for a typical LED driver using high-frequency switched converters is presented in Fig. 1. Considering an alternating current (AC) line, the first stage is the EMl filter followed by a rectifier bridge, a PFC stage and a PC stage, providing a LED constant current.
C
A
in E L e
0)
--+
te r p�ge p�r L1Ds cRITJ F1 e rn � ( T W e
r
--+
--+
--+
--+
'
Fig. 1: Typical LED driver system stages.
The integration of both PFC and PC stages is a method to reduce the number of active switches to simplify the command circuitry and consequently, to reduce the cost of the lighting system [15]. It also allows for reducing the storage capacitance compared to a single-stage topology [8]. Thus, a comparison between two integrated topologies, SEPIC-Buck and SEPIC-Cuk, as off-line dimmable LED drivers from a storage capacitance reduction point of view is proposed in this paper. This study also comprises the overall system efficiency and the input harmonic content standard compliance [11] considering the same input/output parameters. Furthermore an extremely simple dimming strategy is proposed. Integrated Converter Analysis
Among the well-known classical DC-DC converters to perform PFC, the SEPIC has attractive features. It presents a step-up and step-down voltage ratio, high power factor (PF), possibility of galvanic insulation, a single switch, which shares the input and output reference, and it also might operate performing an EMI input filter. This converter also has a voltage source characteristic, which can fit the input of PC stage. The SEPIC operating under DCM as PFC allows for a simplified control circuitry [16, 17]. It does not have a transformer and therefore it lacks the associated leakage ringing effect when compared to Flyback converter, for instance. SEPIC can be designed for a wide range of voltage conversion ratios. In addition, the input inductor current in DCM follows the input voltage with much smaller ripple current as compared to Flyback and Boost converters [18]. Meanwhile, to provide relatively low voltage levels to the output, the duty cycle (D) of the SEPIC could be a critical value, decreasing significantly the efficiency due to the relatively high current levels across the components for the same power. Thus another converter is necessary to provide an adequate power to the load, behaving as PC stage. A converter which presents current source output characteristic is appropriate when employing LED load. An option is to use a Buck converter as proposed in [19]. In other hand, a Cuk converter operating in Continuous Conduction Mode (CCM) behaving as an output continuous current source is either a possible relevant choice. This operation mode allows for applying a reduced output capacitance (Co) to the converter. Once SEPIC-Buck integration analysis and topology design is demonstrated in [19], this paper focuses on SEPIC-Cuk project to finally compare both topologies. The integration technique requires both converters to be operated at the same switching frequency (j,) and duty cycle [20]. The schematic of each converter is shown in Fig. 2.
+
Ro Vbu,
(a) Fig. 2: Simplified schematic of SEPIC (a) and Cuk (b). Connecting the output of SEPIC to Cuk converter input, a common node between the source of both switches Sc"uk and SSHPIC is identified, characterizing the T-type connection [20]. Using the auxiliary diodes DJ and D2, both switches SSHPIC and Sc"uk are replaced by only one switch S which is shared by
both stages. This connection produces an intrinsic switch over current. The LED simplified model is also added. The resulting integrated topology is shown in Fig. 3. • Vr"fY"I
L,
-:+ ill
D,
s-l
D2
L)
Ds
C, •
L2
L4
• Co •
•
iL2t
DL fL
VI;
Fig. 3: Simplified schematic of the integrated converter. The equivalent schematic circuitry considering each SEPIC-Cuk operation stage is shown in Fig. 4. This analysis considers the capacitor C1 as a voltage source with the same instantaneous value as the input voltage during a switching period (T,). Moreover the semiconductors are considered ideal. First stage (to:::: t < t 1 ): In this stage the shared switch S is turned on according to the duty cycle D. The switch current stress is defined by the sum of SEPIC typical on current (iu + i12) and Cuk (iu + h.;). Inductor L3 assumes the bus voltage. The sum of bus voltage and output voltage ( Vhus + Vr)) is inversely applied to inductor L4• During this time the capacitor C2 assures the output power. Second stage (t 1 :::: t < t2): At this time, the switch is turned off and the diodes Ds and Dc conduct. The sum of the iu and i12 currents flows through Ds. During this period the capacitor Cbus is charged until the current across Dc') reaches zero. Third stage (t2 :::: t < T,): In this stage, the inductor L4 supplies the LED. The current iLl is equal to -iL2' called residual current JR. During this period the capacitor Cbus is discharged until the current across Dc reaches zero. • Vre,fY"I
L,
-:+ ill
s-l • Vre,fY"I
L, -:+ ill
D,
s-l • Vre,fY"I
L, -:+ ill
s-l
C, •
O2
L)
D, L2
(a)
C, •
D2
Ds •
Cbus
iut
D2
Ds L2
iu t
•
L)
C2 •
L4
•
L)
L4
rL
VL
DL rL
VL
• Co •
•
DL
• Co •
D,
(b)
C, •
• Co •
•
iut
L2
L4
DL rL
VL
(c)
Fig. 4: First (a), second (b) and third (c) operational stage of the SEPIC-Cuk.
Topology Design
According to the presented SEPIC-Cuk operational stages, each intrinsic converter (SEPIC and CUk) operate as the converter individually. It allows designing each stage, PFC and PC, separately. The SEPIC operating under DCM may be represented as the equivalent circuitry according to Fig. 5 [21]. Ds
+
i(t)
RCUk Vbu,
Fig. 5: Equivalent circuitry of the SEPIC in DCM. The PFC stage average output current (in a line period, Tr) is represented by the current source i(t) in Fig. 5, and it is calculated through (1). The resistances RSEPIC and RC'uk, representing the PFC and PC stages equivalent input resistances, are given by (2) and (3), respectively.
(1) 2Le
_
q D2 Ts
R�APfC -
R,Cuk =R
0
(2)
�us2 V
2
o
(3)
A high PF is assured due to the resistive load emulation performed by the SEPIC stage for a constant D. The voltage Vpk represents the peak value of the input voltage and Leq corresponds to the parallel association of both inductances LJ and L2, and it is given by (4). The transferred input power Pin is determined by this inductance. The inductances LJ and L2 are determined through (5) and (6), respectively. The input current ripple percentage iJiL] is a design parameter. Ipk corresponds to the input current peak value, which is observed at the peak line voltage ( Vpk) [18].
(4) VpkDT: L = I I pk;}.iL I
(5)
(6) It is assumed that the voltage across the capacitor CJ is constant within a switching period, but at the same time it must follow the line voltage low frequency variation. When operating as PFC stage, the resonant frequency (fres) given by C], L] and L2 must be higher than the line frequency, in order to avoid input current oscillations within each line half cycle. Additionally, the resonant frequency given by L2 and C] must be lower than the switching frequency, so that a constant voltage within a switching period can be assured [18]. In this way, the capacitance C] may be calculated for a defined resonant frequency.lres (usually III 0 of the j;) through (7). The intrinsic Cuk converter inductances L3 and L4
must be calculated assuring the CCM for the Cuk converter. This is shown in (8) and (9), where Mn and MIA are the output high frequency current ripple percentage and IU:f) is the average output current.
(7)
L3
L
�us·D.I:
=
(8)
iJiL3.Ium
=�.(1-D).I: 4
(9)
iJiL4.Ium
The bus capacitor Cbus is designed as shown in (10), where (febus) is the average charging current through capacitor Cbu", considering the maximum acceptable bus voltage ripple L1 Vbus. This ripple is related to the output current ripple MU:f) according to (11). Chus
=
Uchu,)·T;, 2 iJ Vbus
(10)
o
(11) The capacitor Cbus is chosen according to the relation between the bus voltage ripple L1 Vbus and the output current ripple MIED for the open-loop configuration. If a MIED=50% is chosen, for a Vbus= 140 V, the corresponding bus capacitor is Cbu,,= 198.373 f.lF, for instance, as shown in Fig. 6.
0.1 0.08 .)0.06
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::::;-, ...r . -;::::::;: :::;:
r-l:---i"�l-&:!fi)O:?�il'
800 600 ... I� I 400 G 0.04 !' t , .. '-' .. ... . .... . . .. . ... . ...... I't�
