Integration Technology Parameters for Physical Design ... - IEEE Xplore

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Keywords: vertical SiP Integration, physical design, 2.5D 3D. Integration, design rules ... tity in the routing, testability of the layers and of the complete system as a ...
Integration Technology Parameters for Physical Design of Vertical System-in-Package David Dmitry Polityko1), Stephan Guttowski2), Herbert Reichl1) Technical University Berlin, FSP Mikroperipherik (TUB-MP) 2) Fraunhofer Institute for Reliability and Microintegration (Fraunhofer IZM) Gustav-Meyer-Allee 25, D-13355, Berlin, Germany E-mail: [email protected] 1)

Abstract A promising solution for achieving highest integration density has been seen in vertical integration of heterogeneous components as a System-in-Package (SiP). An important success factor of 2.5/3D SiP is efficiency in physical design. The main content of this article is an introduction to the structuring of physical design, novel classification of 2.5D technologies, and the calculation of a parameter set, which provides key data for an objective comparison and selection of integration technologies for the design process of vertical integrated SiP. Keywords: vertical SiP Integration, physical design, 2.5D 3D Integration, design rules, technology parameters, technology modeling, chip stacking, folding, vertical interconnects. Introduction The permanently growing market of portable and handheld applications demands very high density in electronic system integration. The 3- and 2.5D multichip integration solutions, also called System-In-Package (SiP), are gaining in importance. Compared to the monolithic integration – Systemon-Chip (SoC), In-Package integration approach allows, for instance, an easier integration of very heterogeneous components, the combination of which on the chip-level is very challenging in its technology [1]. Nevertheless, there is a number of advantages in contrast to the two-dimensional solutions such as shorter wires, a lower propagation delay, less size and weight, etc.[2]. As a consequence, the boundary between the system oriented PCB/MCM-Design and the technological oriented package design is disappearing and this conglomeration in its complexity is getting closer to IC-Design. Whilst a PCB/MCM designer has several clear technological criteria to make a decision regarding substrate and interconnection technology (e.g., wiring density, via types, the number of layers of laminated, thin film or ceramic substrates, interconnect pitch, cf. Tables 1 and 2), there is no clearly defined criteria for choosing optimal SiP technology for vertical integration. The system designer is faced with many different technological solutions presented by several industrial and research institutions. These can be, for example, stacked and wire bonded dies, circuitry on folded flexible substrates, flip chip modules soldered on each other and so on. New design rules, answering designers questions regarding technological possibilities in 2.5D like number and thickness of stackable layers, allowable dimension and number of vertical interconnects (VIC),

1-4244-0152-6/06/$20.00 ©2006 IEEE

must be formulated [3]. The derivation of a practical parameter table from different technologies would not only simplify the geometrical and consequently the technological decisions in the physical design flow, but would also allow for urgently necessary [1,3,4] computer aided design tools that could be based on it. This paper discusses on-going research on the technological parameter model for physical design of 2.5D SiP. After an introduction into the physical design flow for 2.5D SiP followed by short review and classification of available vertical SiP technologies, the parameter’s set will be presented. Different vertical SiP approaches will be compared in two case studies: stacking vs. folding for modules integration and chip wire bonding vs. substrates soldering for single dies integration. Conclusions and future works are presented in the last section. Physical Design Flow for SiP Integration In the beginning of the physical design, the net list and the component set (ICs-bare dies, passives in their values etc.) are defined for the most part. After partitioning and placement before starting a fine routing, the designer of 2D systems like PCB/MCM compares different interconnection and substrate technologies by clearly defined parameters [18], which are partly presented in Tables 1 and 2, and formulates the design rules in accordance with them. Within the 2.5D integration, where the functional layers are vertically integrated on each other [5], the physical design could be subdivided into two stages: 1. Global Layout, which can be abstracted away from any certain technology, 2. Detailed Layout/implementation, which is obviously based on definite technology. In analogy to PCB/MCM- and IC-Design, both stages consist of three main steps: partitioning, placement and routing (Fig. 1). The aim of global partitioning is to group the components and to allocate them on certain vertical layers. Global placement means the arrangement of layers in stack, and global routing is in this case the optimization of the electrical wiring/nets between the layers (Fig. 2). All these steps can be formulated as a mathematical problem with a number of boundary conditions and objectives, such as floor plan and volume minimization for partitioning, minimization of wire length in the placement, the reduction of nodes quantity in the routing, testability of the layers and of the complete system as a general task etc.

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Substrate

Line width [µm] Line space [µm]

50…75

125

250

10

Via land ø [µm]

100…225

650

200

30

No. layers

8…10

8...30

15..30

2..5

Diel. const.

2,3…4.7

4,7

6...10

2,7...3,5

FR4

FR4 Lowest

Alumina

Si, Metal… High

Parameters

Material Price approxim.

medium

cents/cm2

MCM-C

MCM-D

Ceramics

Thin Film

75..100

10

predetermined by the specific technology and there is no strict line to separate global layout from the detailed implementation.

MCM-L PCB HDI Standard 50…75 125

medium

$/cm2

Tab. 1. Design relevant parameters for laminated (MCM-L), ceramic (MCM-C) and thin film (MCM-D) substrate technologies. Based on [13] and industry enquiry, Apr. 2005

The detailed layout is not only an application of the same steps on the two dimensional “interlayer” problems, but at the latest at the beginning of this stage, the technology for the stacking and vertical interconnection of the functional layers must be selected. Schematic->Net lists, Components incl. Dice->Geometries

Global 2,5D Layout

Global Partition.

Physical Design 2,5D

System Complexity

Technology free Global Placement Global Routing

Technology Parameter Technology

Stacking Technology Substrate, VIC …

Technology Selection

Classification of Technologies The detailed description of numerous, completely different types of 2.5 D SiP solutions, which have been presented during the last decade, is beyond the scope of this paper. The classification and subdivision of these technologies into a manageable amount of groups by addressing discretionary criteria would simplify the design approach. In contrast to the example of MCMs, there are no industrially accepted standardizations of any kind regarding vertical integrated systems [1]. The IPC-7095A standard, which actually scopes the assembly challenges for implementing of BGA [10], gives only some not binding examples of an attempt to establish a definition for MCM housing more than one die – also vertically integrated. The SiP definition, which is described by [1] as any combination of semiconductors, passives, and interconnects integrated into a single package, does not limit SiP to any technology or integration approach. Based on primarily technological criteria, the classifications of 2.5D technologies by „Interconnects Technology“ (Area, Periphery [2]) or by „Integration Level“ (Wafer-, Chip-, Package-/Module-Stack [7,8]) have been presented. The abstract and “technologyfree” consideration of signal paths and nets complexity results in another classification, which is more helpful for design purposes.

Design Rules

Detailed Layout

Detailed Partition. 2D Layer Technology based Detailed Placement Validation -Extraction -Parasitics

Detailed Routing

Thermal Simulation Electrical Simulation

Fig. 2. Global layout - Components and Nets: a) on the beginning, b) after partitioning, c) after placement and routing

Fig. 1. Physical design flow for 2.5D SiP

So far, there are only a few publications on the physical design for 2.5D. These works are mostly focused on the cell placement for SoC [5] and not on the block placement [6]. The number of publications, which effectively apply mathematical models on 2.5D SiP needs [e.g.6], report the essential mathematical basics for 2.5D SiP integration, but target only one specific SiP technology at the very beginning of the physical design stage. The formulation of boundary conditions is Interconnect Parameters Min. Pad Pitch [µm]

Die Substr.

Mounting Electr. Performance Mech. Prot.

Wire Bond

Flip Chip

TAB

50

100...120

60

120

100...120

200

serial

parallel

serial/paral.

L [nH]

1-5

0.06-0.2

1-3

C [pF]

0.2-0.6

0.02-0.03

0.2-0.6

glob top

underfill

none

Tab. 2. Design relevant parameters for different interconnect technologies. Based on [12,13]

In [18], 2.5D SiP-Solutions have been subdivided in four groups, in accordance with their capability to connect/redistribute signals and nets in the vertical or lateral wiring passage (Fig.3, Tab.3): 1. Systems, where no redistribution in vertical wiring (in this case, it can be called vertical interconnect – VIC) and lower redistribution level in lateral wiring is possible, mostly represented by wire bonded die stakes (e.g. Sharp), 2. Systems with no redistribution in VICs and high redistribution level in lateral wiring, represented by solutions with functional layer on stacked modules (e.g. North), 3. Systems, where redistribution level in vertical and lateral wiring is high and approximately equal , represented by solutions with components on the folded flexible substrate (e.g. Tessera), 4. Systems with medium and approximately equal redistribution level in vertical und lateral wiring, represented by stacked and moulded devices with connecting metallization on the surface/sidewalls (3D Plus, Irvine)

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Fig. 3. Four main integration schemata and application examples of 2.5D SiP classified by redistribution level

Parameter’s Set Considering the net complexity schema and being supported by essential parameters which are partly presented in Table 3, a SiP designer at the beginning of the detailed layout/implementation stage can choose between four technology groups and start optimizing results of global layout targeting the chosen technology. The proposed parameter’s set is currently in its early development phase. Nevertheless, it gives the designer some rough guidelines for the trade off analysis and the technology selection. For example, systems dominated by chips only can be realized by wire bonded stacks (group 1), where the signal redistribution is mostly accumulated in the basic substrate/carrier. The stacked rigid solutions (group 2) are well suited for applications with high wiring demand in levels, owing to usability of advanced substrate technologies like HDI or thin film for lateral wiring. Folded flexes (group 3) are more suitable for applications with lower constraints regarding the signal delay time because of the higher wiring length. The highest number of the layers is available in the moulded stack solutions (group4), but only thin components can be integrated due to the relatively low layer gap. One of the important aspects in the design process for 2.5 D SiP is the amount of connections, which can be placed in the given space between the two next layers. In 2D applications, the term of “Connectivity” is often used for wiring effort estimation. This metric, which is defined as the available length of interconnect wiring per unit area [14] and summaTechnology Group Parameters Vertical Lateral Passives Integrati- Discrete on Capability Embedded WL Wire Length Ln No Funct. Layer Layer Gap G[µm] Layer Thickness L=G+S Substrate/Carrier S[µm] [1/(mm2mm)] VIC Density Redistribution capability

rizes the most important substrate parameters (the line- and the space-width, layer number), cannot be applied in this case. New metrics must be formulated and be utilized for the objective comparison and choice of the 2.5 D SiP technology. We propose to describe the maximal possible vertical connection throughput by Vertical Interconnect Density, which is defined as the available number of vertical interconnects/wiring lines per unit area and highness/layer gap (Fig.4):

N

Dv =

A⋅G

Dv N A G Vvic

– – – – –

=

N Vvic

[1/mm²mm]

(1)

vertical interconnect density, number of VICs, square occupied by N VICs [mm²], layer gap [mm], volume occupied by N VICs [mm³].

Fig. 4. Terms for definition of Vertical Interconnect Density The unit is [mm-2mm-1] and not [mm-3]. It emphasizes the primarily dependence of the Dv on G and not on the Vvic in general: as will be shown below, N is the function of G in certain cases.

Stacked Dice

Stacked Modules

Folded Flex

Moulded Devices

low low low high Up to 5 100…600 100…200 0,5…20;

high high high low 7 100…1200 ≈ 50…1200 0,5…15; ~f(G)

high high high medium high 10 200…1200 20…100 5…40

medium medium high medium medium 32 50…600 50…200 10…50

Tab. 3. Parameter set for labelled SiP technology groups

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Calculated Gap IPC values Min. Max. Ball G=0,6b Pitch Pitch Diam. b [mm] pmin [mm] pmax [mm] [mm]

p – Pitch of VIC (solder balls). The pitch p can be described as (Fig. 5):

Space Min.

Max.

smin=b-pmin

smax=b-pmax

[mm]

[mm]

0,75 1,27 1,5 0,45 0,52 0,75 0,6 1 1 0,36 0,4 0,4 0,5 0,8 1 0,3 0,3 0,5 0,45 0,75 1 0,27 0,3 0,55 0,4 0,65 0,8 0,24 0,25 0,4 0,3 0,5 0,8 0,18 0,2 0,5 0,25 0,4 0,4 0,15 0,15 0,15 0,2 0,3 0,3 0,12 0,1 0,1 0,15 0,25 0,25 0,09 0,1 0,1 Tab. 4. Ball diameter and pitch predicted by IPC, calculated values of layer gap and solder ball spacing

The proposed parameters, their interaction and principles offer interesting objectives for investigations. For instance, the pitch between solder balls (within the technology group two) is a non linear function of layer gap, as it will be shown below.

b

(3)

b – solder ball diameter, s – spacing between solder balls. The exact prediction of solder joints shape and its maximal diameter is very challenging. The necessary formula should include many parameters like ambient and internal pressure, surface tension and so on, as it has been shown in [9]. But there is also easier method for approximated calculation of the ball diameter and spacing. According to IPC7095A [10], the dimension of land pattern for solder balls averages 80% of solder ball diameter b (Fig.8) addressing the BGA implementation. Assuming for simplicity a spherical shape for the solder balls and a complete coverage of the land pad after mounting, the relationship between solder ball diameter and layer gap can be calculated as: 2

0,8b b 2

p =b+s

2

⎛ b ⎞ ⎛ 0,8b ⎞ G = 2 ⎜ ⎟ −⎜ ⎟ = 0,6b ⎝2⎠ ⎝ 2 ⎠

(4)

consequently b = 1,66G ≈ 1,7G

(5)

The IPC-7095A [10] also dictates the tolerable pitches for numerous solder ball diameters. The allowable space s between balls is not a constant value, it increases with bigger ball diameters. Table 4 gives discrete values for the allowable minimal and maximal space s calculated as a subtraction of pitch and ball diameter. Based on this data, the relationship between s and G can be approximated as (Fig. 7): s (G ) = 1,3G (6)

G

S s p Fig. 5. Necessary metrics for calculation of VIC pitch

Modules Integration: Stacking vs. Folding For a vertical integration of SiPs, which consist of heterogeneous devices and include for example passives components additionally to IC’s, a designer has principally two technological possibilities: either to stack the modules (group 2) or to fold them within the flexible substrates (group 3). In this section we will compare the vertical interconnects of these techniques. The behaviour of VIC-Number N depending on layer gap G in the case study for soldered modules will be considered first. It will be followed by the VIC calculation for laminated folded flexes. A. Stacking A module with square area Am=(10x10)mm² is given. One bare die in flip chip technique with the area Achip=(5x5)mm² and ten discrete passive SMD components are assembled on the module. A further module without assemblies on the bottom side is stacked over the first one and connected by solder joints (Fig. 6). To simplify the approach, we assume, that the area Asmd=Asmd1+Asmd2+…+Asmd10=5mm2 occupied by passives is constant. It is nearly equal to the area of ten 0402 SMD’s. Further we assume that the residual surface can be completely used for solder balls (Avic). The number of available VICs N can then be calculated as: Am − Achip − Asmd A N = = vic2 (2) 2 p p

Consequently, the pitch p as function of G can be calculated as: p = b(G ) + s (G ) ≈ 1,7G + 1,3G = 3G (7) b(G) – solder ball diameter given by (5), s(G) – spacing between solder balls estimated bei (6). a)

b)

Am Achip ...

Asmd1

...

Asmd10

Fig. 6. Case study soldered modules: a) integration schema with different layer gaps, b) components and modules area

The diagram in Fig. 7 demonstrates evaluated straight lines for approximated space and calculated pitch values in relation to allowable values from [10]. Using the result of equation (7) in the equation (2), we finally determine N as a function of layer gap G as follows:

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1,6

s [mm] p [mm]

of rmin by using an IPC standard. The IPC 2223A [11] estimates rmin for the double-sided laminated substrate as follows:

Min. spase smin Approximation s=1,3G Max. Spase smax Min. pitch pmin Max. pitch pmin Calculation p=3G

1,4 1,2

⎞ ⎛ 100 − E B ⎞ ⎛d ⎟⎟ − D + c ⎟ ⋅ ⎜⎜ ⎝ 2 ⎠ ⎝ EB ⎠

rmin = ⎜

1

d c D EB

0,8 0,6 0,4 0,2 0 0,05

0,1

0,15

0,2

0,25

0,3

0,35

0,4

G [mm] 0,45 0,5

Fig. 7. Approximated space and calculated pitch values vs. values from [10] as a function of layer gap

N =

– – – –

(9)

base material thickness, copper thickness, coverlayer/solder mask, copper deformation factor [%].

For the case study, a double-sided flex with following data is assumed: base edge 10mm, wiring pitch 150µm, d=50µm (PI,Espanex), c=18µm, EB=16%, D=20µm. Insetting of this data in (9) results in the minimum bending radius rmin=0,2mm and layer gap GminFL=2xrmin=0,4mm respectively, with constant VIC number of N=133.

Avic

(8) 2 9G The curve in the Fig. 10 provides the calculated values. Increasing of G causes a strong reduction of N in accordance with the behaviour of a x-² function. The thickness of the utilized components significantly influences the VIC number. As far as the highest passive component on module defines the limiting threshold in the thickness, the choice of the package with an optimal component value-dimension ratio is important. The diagram in Fig. 8 summarizes the enquiry of leading passives manufacturers for capacitors and inductors. Furthermore the trend in the development of embedded passives, which are thin in their nature (e.g. embedded capacitors with capacitance density up to 300 nF/cm2 [15]), is very interesting in this context.

B. Folding Similar calculation can be done for the folded flexes. In this case, the minimal layer gap GminFL is predicted by minimum bending radius rmin (Fig.9). As in the previous case, we can avoid a complex material stress analysis for the estimation

rmin G minFL=2xrmin

Fig. 9. Geometry metrics of folded flex

As it can be seen in the Fig. 11, the laminated folded flexes of this kind are applicable with higher vertical interconnect density at layer gaps beyond 400µm, while stacked technology offers advantages at smaller gaps.

Fig. 8. Available capacitor (a) and inductor (b) values for different packages. Industry enquiry, 2006

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200

N

This equation is valid as far as the minimal distance lmin between first pad raw and die attach can be realised by wire bond equipment and by the substrate manufacturing (Fig. 11):

N=194 Thinned Dice Thin Bumps

175

Folded Flex

125

1 ⎞ ⎛1 l min = ⎜ n ⋅ p S − a ⎟ / 2 = n ⋅ ( p S − pC ) 8 ⎠ ⎝4

100

a=

150

N=133 const.

Gm inFL

N=86

SMD Thickness Area Typical Die Thickness Area N=31

75 50

01005 0201

25

Soldered Modules

0402

N=12

0 0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

(12)

4

lmin – minimal distance between first pad raw and die, pc – pad pitch on chip, a – dimension of square chip’s side.

Avic 9G²

N=

0603

n ⋅ pC

N=8

a≈

G[mm]

0,9

1

Fig. 10. Compare of folded flex and stacked modules: VIC number vs. layer gap

A. Wire Bonding To simplify the approach we assume, that • each die in the stack requires a one pad row on the substrate; • substrate pads have square form with edge dimension w equal to space dimension s resulting in substrate pitch ps=w+s; • all pad rows themselves are ordered in square form, as it is exposed in Fig 11. The area A1, which is occupied by first wire bonded die in stack, can then be roughly calculated as: A1 =

2

2

2 ⎞ 2 ⎜ n ⋅ pS ⎟ = ⋅ pS = n ⋅ pS 4 16 16 ⎠ ⎝

A1 n ps

n

1

2

(10)

– area occupied by first die in stack, – pad number, – substrate pitch.

Parameters

Chip Thickn. Hc [µm] 150 200 250 300 350 400

Min. Dist. lmmin [µm]

87,4 96,2 Cf=3, d=20µm, 105,0 α =20°, 113,8 T=90µm 122,6 131,5 Tab. 5. Calculation of minimal distance defined by machine’s parameters

npc 4

ps

w

pc

Single Chips Integration: Wire Bonding vs. Soldering For the majority of today’s semiconductor manufacturers, wire bonding remains the most flexible and cost-effective interconnect solution for stacked chips applications [17]. The reason for this is not only a wide utilisation of wire bonding machines across the packaging industry. Using the proposed parameter model, it can be shown, that wire bonding of stacked dies is an effective technique for the vertical integration of “dies-only” systems. Therefore in this section we will calculate and compare the volume, which is necessary to interconnect a certain number of dies vertically by wire bonds and by stacking substrates with solder balls.

⎛1

(11)

s nps 4

lmin

2ps first row

second row

Fig. 11. Metrics for wire bond area calculation

Based on [17] and addressing ball-wedge gold wire bonding, the minimal distance between substrate’s and die’s pads lmmin, which results from wire bond machine’s parameters, can be formulated as follows (Fig. 12): ⎛α ⎞ T lmmin = C + Hc ⋅ tan ⎜ ⎟ + (13) ⎝2⎠ 2

C=

d ⋅ Cf

cos( α2 )

lmmin – C – d – Cf – Hc – α – T –

(14)

distance between chip and substrate pad centres, minimum wire clearance, wire diameter, clearance factor (typ. Cf ≥ 3 ), chip thickness, tool tip angle, radius of tool tip.

Table 5 summarizes calculated values of lmmin for some “state of the art” machine parameters and chip thicknesses. Varying the chip thickness up to 400µm we can observe, that the distance is still smaller than the substrate pitch of 150 µm, which is common for laminated substrates up to day. Neglecting the dimension of die attach, we can appoint for further calculation, that the manufacturability of the substrate and its pitch primarily determine the minimal distance between first pad row and die.

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Considering a wire bonded same-size die (not pyramid) stack [17], consisting of a number of Ln dies with thickness Hc=200µm, pad number n=160, chip pad pitch pc=120µm and chip edge of approximately a=5mm, we can determine the area (by applying of (10)), which is occupied by first die (Ln=1) including pads for wire bonds as A1=36mm². Validating this result, we receive lmin=600µm from (11). This value is smaller than ps=150µm of laminated substrate, which we assume for this case study. Since every further layer (chip) require one further pad row, and the distance between the rows amounts 2ps to enable some routing fan-out (Fig. 11,13), the caused increasing of the occupied substrate area can be investigated in accordance with the following equation: 2

2⎛ 1 ⎞ ⎞ ⎛1 ALn = ⎜ np S + 4 p S (Ln − 1)⎟ = p S ⎜ n + 4(Ln − 1)⎟ ⎝4 ⎝4 ⎠ ⎠

(15)

2

)

90 Vwb

Volume [mm ]

Dv -3

[mm ]

Vsb DvWB

75

DvSB 200

60 practical area

theoretical area

150

45

100

30

50

15

(16)

And finally, we can approximately calculate the necessary volume Vwb for vertical interconnects of wire bonded die stack:

(

(20)

300 3

(17)

Vwb = V − a ⋅ H st

Vsb = Avic ⋅ (L ⋅ (Ln − 1)) = Avic ⋅ (G + S ) ⋅ (Ln − 1)

250

Hst – stack height for Ln dies, S – spacer thickness, G=Hc – chip thickness or layer gap, L – layer thickness. The corresponding system volume excluding base substrate can be described as: V = ALn ⋅ H st

(19)

Assuming the most simple net schema, where each chip’s pad is connected bus-like to the same pad on the other layer, we can state a constant number of VIC on each layer N=n as well as an equally occupied area Avic=A1=A2=…=ALn on each level. Allowing a substrate thickness of S=100µm and neglecting the thickness of flip chip interconnects, we obtain ample variable’s set to calculate the volume Vsb, which is necessary for vertical interconnection of Ln dies by bonding of substrates with solder balls:

2

ALn – necessary area for wire bonds of Ln stacked dies, Ln – number of dies in stack. Furthermore, spacers/interposers in the stack have a thickness S=100µm (Fig. 13). Assuming that 100µm loop height is possible [19], we can express the stack height without base substrate as follows: H st = Ln ⋅ (H c + S ) = Ln ⋅ (G + S ) = Ln ⋅ L

2

Avic = 9G ⋅ N

(18)

B. Substrate Bonding For this study, we consider stacking substrates and dies as it is shown in the Fig. 6a, but without any passive components. Aiming a calculation with the same chip parameters (Hc=G=200µm, n=160) as in the previous section, we can modify equation (8) to express the necessary area for solder balls by the given VIC number and layer gap:

0 2

3

4

0

Ln 6

5

7

8

9

10

Fig. 14. Wire bonded and soldered substrates stack: volume of vertical interconnects and vertical interconnect density vs. layer number

The diagram in Fig. 14 provides a graphical comparison of investigated values of Vwb and Vsb for the theoretically possible maximum of 10 chips/layer. It can be clearly observed, that although Vwb is proportional to squired value of Ln (Vwb~Ln²) and Vsb is a linear function (Vwb~Ln), wire bonding has an advantage for SiPs with dies number less than five. At that point (Ln=5) both integration technologies achieve a nearly parity in the occupied space. It should be noticed, that even small increasing of chip thickness from 200µm up to 250µm moves this point towards Ln=8 for the benefit of wire bonding. But thinning dies down to 150µm results in a parity at Ln=2 and a smaller volume for soldered VICs above this point. Furthermore, the number of effectively Hl ≈ S

d

Ln

α

Hl

dx C f

.. .

Hst

Hc

T

α/2

2.

C

S

T/2 lmin

Fig. 12. Necessary metrics for calculation of minimal distance defined by machinery’s parameters

1.

H

HC

2ps

c

Fig. 13. Wire bonded die stack with interposers

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Y1

GND

Signal Line

r=200µm r=300µm r=400µm r=500µm r=600µm

2r

GND

a) Freq.[GHz] b) Fig. 15. a) Geometry model for simulation (substrate and coverlayer materials are deembedded in this view); b)simulated transmission magnitude vs. frequency for varying folding radii

existing nets is constant in the soldered stack (N=n=const), while it grows linearly in Ln with every further connected die in the wire bonded stack (N=n·Ln). Insetting these N values and evaluated volume amounts in equation (1), we receive the “over all” vertical interconnect density Dv, which is advantageous for wire bonding in entire Ln range (Fig.14). This is valid only for this certain case study: in SiP applications with some other net and signal redistribution schema, which are aiming not only at transferring all signals outside the package, staked substrates allow for an easier layer-to-layer interconnection resulting in other Dv behavior.

Conclusions and Future Work In this paper, a structuring of physical design flow, a classification of available 2.5D SiP technologies and their linking by design relevant technology parameter’s set have been discussed. The demonstrated models and formula can be applied by the SiP designer for an objective choice between different 2.5D integration approaches and for fast calculation of design rules. Hence, it increases the design effectiveness. To establish the proposed parameter’s set as a really applicable tool for physical design of 2.5D SiP, further analytical investigations and practical verifications are necessary. Future work should also link proposed geometrical parameters and electrical characteristics of vertical interconnects. The interaction between geometry and electrical performance of wire bonds and solder balls have been investigated and reported in numerous publications (e.g. [12]) owing to their wide utilisation since decades. But there is minimum published information about electrical performance of e.g. folded flex. Fig. 15b demonstrates first results of signal transmission simulations, achieved by a full wave 3D simulation tool, for various folding radii in accordance to the geometry and material set, which have been described in the section “Modules Integration: Stacking vs. Folding” of this paper. Furthermore, additional terms and metrics should be developed. For instance, a new term for the evaluation of technology effectiveness has to be formulated. A common planar benchmark – silicon efficiency, expressed as the ratio of overall silicon IC area to substrate or board area – cannot be meaningfully applied. A “figure of merit” presented in [16],

which is relating IC area to system volume, could be used, but it doesn’t consider passive components. The research results discussed in this paper allow not only for an optimisation of 2.5D SiP physical design flow. They can also quantitatively confirm or predict the needs and trends for research in packaging. For instance, the diagram in Fig. 10 demonstrates, that a highest effectiveness in the vertical wiring could be reached only by an advanced packaging technologies dealing with dimensions beyond the 200µm border such as thinned dies, ultra thin bumps, assembly of smallest discrete and integration of embedded passives (Fig. 16). These technologies are being currently developed at the Fraunhofer IZM and TU Berlin. IZM HDI

a)

IZM CIT

b)

Fig. 16. Examples of advanced packaging technologies: a) thin film modules stacked with 300 µm solder balls; b) 40µm thinned chip with 4µm plated Au bumps on PI substrate (6µm Cu adhesiveless metallization on 25µm PI)

Acknowledgments A part of the reported work in this paper was carried out in the frame of the Project “AVM – Autarkic Distributed Microsystems/eGrain“. This project was supported by the Federal Ministry of Education and Research (BMBF) of the Federal Republic of Germany under grant 16SV1658. The reported particular results are part of a task which aims the development of a design methodology for system miniaturization within advanced 3D packaging integration. The responsibility for contents of this publication is held by the authors only. Special thank is addressed to IZM colleagues Ivan Ndip und Uwe Maass (IZM) for their support in the HF simulation. The valuable input of Dr. K.-D. Lang in wire bonding issues is highly appreciated.

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