Interface Trap Density of Gate-All-Around Silicon ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 8, AUGUST 2013

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Interface Trap Density of Gate-All-Around Silicon Nanowire Field-Effect Transistors With TiN Gate: Extraction and Compact Model Faraz Najam, Student Member, IEEE, Yun Seop Yu, Senior Member, IEEE, Keun Hwi Cho, Member, IEEE, Kyoung Hwan Yeo, Dong-Won Kim, Jong Seung Hwang, Sansig Kim, and Sung Woo Hwang, Senior Member, IEEE Abstract— Si/SiO2 interface trap charge distribution of cylindrical cross-sectioned gate-all-around silicon nanowire field-effect transistor is extracted by using three-dimensional simulation. While the interface chemistry of conventional gatestack (Si/SiO2 polysilicon) in conventional planar devices is well documented, not much work is available on interface trap distribution Dit of alternate gatestacks (gatestacks employing alternate gate materials) in silicon nanowire MOSFET devices. Furthermore, a compact drain current model with interface trap charge parameter is presented. The model is based on gradual channel approximation and uses self-consistent calculation of interface trap charge and surface potential to reproduce experimental current–voltage characteristics. Index Terms— Compact model, drain-source current, gate-all-around metal-oxide-semiconductor-field-effect-transistor, (GAAMOSFET), interface trap distribution.

I. I NTRODUCTION

W

ITH constant need for scaling, alternate 3-D structures and materials are being tested. Gate-all-around (GAA) devices are expected to play a major role in sustaining Moore’s law [1]. These 3-D devices show better immunity to short channel effects (SCEs) compared with conventional planar MOSFET devices. However, the reported experimental subthreshold swing (SS) values for long-channel GAA silicon nanowire field-effect transistors (SNWFETs) are found to be much beyond the ideal value of 60 mV/dec. It is a well known fact that in the absence of SCEs, the interface trap states are responsible for SS degradation. These trap states are found at the Si/dielectric boundary. While the interface chemistry of conventional Si/SiO2 Manuscript received February 2, 2013; revised May 2, 2013 and May 23, 2013; accepted May 28, 2013. Date of publication June 27, 2013; date of current version July 19, 2013. The work was supported in part by the National Research Foundation of Korea grant funded by the Korea government under Grant NRF-2007-0054845. The review of this paper was arranged by Editor R. Huang. (Corresponding authors: Y. S. Yu and S. W. Hwang.) F. Najam and S. Kim are with the School of Electrical Engineering, Korea University, Seoul 136-701, Korea. Y. S. Yu is with the Department of Electrical, Electronic and Control Engineering and IITC, Hankyong National University, Anseong 456-749, Korea (e-mail: [email protected]). K. H. Cho, K. H. Yeo, and D.-W. Kim, are with the Semiconductor R&D Center, Samsung Electronics Co., Yongin 446-711, Korea. J. S. Hwang and S. W. Hwang are with the Research Center for Timedomain Nano-functional Devices, Samsung Advanced Institute of Technology, Yongin 446-712, Korea (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2013.2268193

gatestack devices is well documented, the use of alternate gatestack (high-κ oxides, metal gates, etc.) in GAASNWFETs is found to strongly degrade the quality of the dielectric interface [2]. While there is a literature available on hot carrier injection HCI related reliability issues of GAAMOSFET devices with alternate gatestacks [3], [4], not much work exists on the quantitative extraction of interface trap density of TiN/SiO2 /Si gatestack of surrounding gate MOS FET devices. The available references are generally found to deal with the metal-gate/Hf-based-dielectric gatestack [2], [5]–[8]. Studies showed that nitrogen from TiN-metal gate and SiON/HfSiON-dielectric is responsible for the interface trap state generation as it diffused into the Si/dielectric interface during the metal gate deposition or oxide nitridation steps [2], [7] whereas, the OH molecules are reported to contribute to interface trap states in gatestacks employing HfO2 [9]. These references presented the impact of both TiN and HfO2 on interface defect states in their study, but not the isolated case of TiN gate in a TiN/SiO2 /Si gate stack. Thus, there is a need for quantitative interface trap density data of TiN/SiO2 /Si gate stacks of surrounding gate MOSFET devices. Additionally, the available GAASNWFET analytical current models ignored the critical interface trap charge parameter [10], [11] important for realistic modeling. The models that do consider the interface trap are based on the assumption of only one interface trap state in the bandgap that is physically unreasonable [12], [13]. Furthermore, the drain current expressions used in these models have some error in reproducing experimental current–voltage (I − V ) curves. In this paper, we first present the quantitative extraction of interface trap density of TiN/SiO2 /Si gatestack in GAASNWFET by using 3-D numerical simulation (Section II) and introduce an analytical drain current model using extracted interface trap distribution for GAASNWFET (Section III). The model is verified extensively by 3-D numerical simulation and the effect of interface trap charge on GAASNWFET is evaluated (Section IV). II. E XTRACTION OF I NTERFACE T RAP D ENSITY A schematic and a TEM image of GAASNFWT are shown in Figs. 1(a) and (b), respectively. Experimental GAASNWFET used in this paper has the geometry of an elliptical cross section with long axis 25 nm and short axis 18 nm, channel length equal to 300 nm, and the gate oxide thickness tox

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(a)

(b) Fig. 1. (a) Schematic representation of the simulated device. (b) TEM image of the experimental device.

2.5 nm. One nanowire is present in the channel. The channel is undoped (or lightly doped). The source/drain regions are highly doped, i.e., 1 × 1020 cm−3 . The detailed fabrication procedures were reported in [14] and other references therein. To extract an interface trap distribution of GAASNWFET, a Silvaco ATLAS device simulator [15] is used. The elliptic cross section of the experimental device is approximated as a cylindrical in numerical simulation by using equivalent GAAMOSFET cylindrical radius R calculated from [16]. Only acceptor type states are considered for our undoped device [17]. In the simulation, drift-diffusion model and concentration dependent Shockley Read-Hall recombination models are used. Interface trap density is extracted for two different mobility models including the constant mobility and the Lombardi CVT mobility model. Lombardi CVT model was used with all default parameters as mentioned in [15]. The mobility μ for constant mobility model is estimated by a standard MOSFET model used to estimate nanowire MOSFET mobility [18].

Interface trap density is extracted by employing several random distributions until a best fit to the experimental I − V data is obtained. Best fit is subjected to the Dit distribution satisfying two criterions: 1) SS fitting in the subthreshold region; in the absence of other factors affecting the SS (discussed later), interface trap states are known to affect the SS; and 2) transconductance gm fitting in the higher Vgs regions; transconductance is also known to be affected by the presence of interface trap states owing to the reduced gate field effect coming from the presence of an interface trap charge [19]–[21]. Initially a U-shaped distribution which is typically reported in literature is assumed and further tuned to satisfy the above mentioned criterions. At this point it must be pointed that from [22]–[24], with increasing channel lengths, the impact of random dopant fluctuation (RDF) on threshold voltage variation and SS becomes progressively lesser. Therefore, for our device dimensions, RDF is not expected to play any significant role. It must also be pointed out that from [25]–[27], the RDF varies proportionally with the thickness of the channel. For our device dimensions, the channel width is not expected to contribute in any significant way to RDF (also channel width’s contribution to RDF is experimentally difficult to evaluate precisely owing to the very small diameter of the GAASNWFET devices). In addition, other sources of Vth variation including TiN gate work function variation and nanowire cross-sectional variations diminish with increasing length and channel diameter, and for our device dimensions are not expected to be significant [28]–[30]. Extracted interface trap density as a function of energy in the bandgap referenced to conduction band edge E c for five sample devices is shown in Fig. 2(a). Experimental I − V curves (symbols) for a sample device [device three from Fig. 2(a)], fitted with interface trap distribution in simulation (lines) for constant mobility and CVT models, respectively are shown in Fig. 2(b) and (c). In Fig. 2(b) and (c), Vth is constant-current threshold voltage extracted at 10−8 A. Fitted transconductance and SS for both experimental data and numerical simulation (for device 3) are shown in Fig. 2(d) and (e), respectively. For verification of the extracted Dit distribution we used the SS method [17], and [31], [32] according to which the difference in experimental SS from the perfect SS value of 60 mV/dec, SS, is given by (2) SS = ln (10) Vt h

Cox + C D + Cit Cox Cit Cox

(2)

d Q it dϕs

(3)

SS = ln (10) Vt h Cit =

(1)

Cit for experimental SS is calculated by using (2) and compared with Cit extracted from simulation. The results (for device 3) are shown in Fig. 2(f). Here, symbols denote experimental-Cit calculated from (2) and lines denote Cit extracted from simulation, and both are in an excellent agreement.

D it _ C o n s ta n t M o b ility, D e v ic e 1 D it _ C V T M o b ility, D e v ic e 1

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D it _ C o n s ta n t M o b ility, D e v ic e 4 D it _ C V T M o b ility, D e v ic e 4 D it _ C o n s ta n t M o b ility, D e v ic e 5

2

D it _ C V T M o b ility, D e v ic e 5

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Cit [µF/cm ]

SS [mV/Dec]

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Ids [A]

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Ids [µA]

D (10 13 2 /cm eV) it

NAJAM et al.: INTERFACE TRAP DENSITY OF GATE-ALL-AROUND SILICON NANOWIRE FIELD-EFFECT TRANSISTORS

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Line: C it extracted from simulation CV curve Symbols: Experimental C it calculated using (2)

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V gs-V t [V ]

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(e)

0.0 -0.30

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V gs-V t [V ]

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(f)

Fig. 2. (a) Extracted Dit distributions for different devices by fitting experimental I − V curves with random Dit distributions. (b) Experimental I − V curve fitted for constant mobility model. (c) Experimental I − V curve fitted for Lombardi CVT model. In (b) and (c), symbols and lines are experimental data and fitted data, respectively. (d) and (e): gm and SS fitting for the experimental device shown in (c), symbols: experimental data and lines: fitted data from numerical simulation. (f): Cit calculated from (2) (symbols), compared with Cit extracted from numerical simulation (line).

Constant mobility model does not consider scattering at high Vgs region and thus overestimates the mobility as shown in Fig. 2(b). CVT model satisfactorily reproduces universal mobility curve for low doped devices [33] which is relevant to our case and is widely used in the GAASNWFET simulation studies. CVT model does not consider coulombic scattering limited mobility (dominant in low Vgs region), which results from coulombic scattering from interface trap charge and dopant ions. The contribution of coulombic limited mobility, however, is found to be minor as compared with other scattering mechanisms for nanowire structures [34]. Further, owing to quantum-mechanical effects in nanowire structures, phonon-limited mobility and consequently actual overall mobility could be lower than what estimated by the CVT mobility model [35]. The CVT model does not have the quantum mechanical corrections needed to take the reduced phonon-limited mobility exhibited by the nanowire structures into account and thus overestimates the mobility. With these

factors, the extracted Dit distribution can be considered as the upper limit and could be lower with these factors considered. III. C OMPACT GAASNWFET M ODEL W ITH I NTERFACE T RAP C HARGE This section is divided in three subsections. The first section deals with the surface potential calculation, the second section introduces interface trap charge calculation, and drain current expression is derived in the third section. A. Surface Potential Calculation From [10], Poisson’s equation for an undoped cylindrical n-type GAASNWFET can be given by the following equation: kT q(ϕ − V ) 1 dϕ d 2ϕ = δe + r dr q kT dr 2

(4)

where δ = q 2 n i /kT ε Si , q is the electronic charge, n i is the intrinsic carrier concentration, ε Si is the permittivity of silicon,


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Fig. 4. Comparison of drain-source current calculated from (14) with numerical simulation for Vds = 0.05 V and Vds = 0.10 V. (symbols: numerical simulation, lines: analytical model). Constant mobility μ = 150 cm2 /Vs.

B. Self-Consistent Interface Trap Charge Calculation

Fig. 3.

Flowchart for φs and Q it self-consistent calculation.

r is the directional component along the radial direction, φ(r ) is the electrostatic potential, V is the applied bias, k is the Boltzman constant, and T is the temperature. The boundary condition for (4) can be given as follows: dϕ = 0, ϕ (r = R) = ϕs (5) dr r=0 where φs is the surface potential. Analytical solution of (4) can be given as follows: −8B kT log (6) ϕ (r ) = V + 2 . q δ 1 + Br 2 Here B is related to φs through the second boundary condition. The total charge per unit area, Q can be given as follows: Q it − ϕs Q = Cox Vgs − φ + (7) CO X where ϕ is the work function difference between the gate electrode and silicon, Vgs is the gate-source voltage, Q it is the total interface trap charge (cm−2 ) and is accounted for by subtracting it from function the work difference (ϕ − Q it /Cox ), and Cox =εox (Rln 1 + tox R) . By applying Gauss’s law, the relationship between φs and Q can be given as follows: dϕ Q it . (8) Q = Cox Vgs − φ + − ϕs = εsi CO X dr Substituting (6) into (8), (9) can be given as follows: q(Vgs − φ + (Q it C O X ) − V ) 8 − log kT δ R2 1−β 2 = log (1 − β) −logβ + η β

(9)

where β = 1+B R 2 and η = 4ε Si /Cox R is a device parameter. For a given Vgs , (9) can be numerically solved for β from which B can be obtained that can finally be used to find the corrected surface potential ε Si from (6) including trap charge induced surface potential φs reduction.

Interface trap charge Q it can be calculated from the following [36]:

Ec (10) Q it = (−q) E Dit (i )F t A (i )d E it g 2

Ft A (i ) =

cns n s + e ps cns n s + ens + c ps ps + e ps

(11)

where Ft A (i ) is the probability of occupation of acceptor trap states which is evaluated for all of the k interface trap states each defined at i th energy level, Dit (i ) is the interface trap density (cm−2 eV−1 ) defined at i th energy level, and cns ,c ps ,ens ,e ps , n s = n i exp[(φs - φ F n )/v t h ], and ps = n i exp[(φ F p −φs )/v t h ], are the electron and hole capture, emission coefficients and carrier surface concentrations, respectively. The total Q it is given by considering the integral of all k interface trap states extracted above [Fig. 2(a)], between midgap and conduction band. From (9)–(11), it is obvious that the solution of φs would require self-consistent calculation of both φs and Q it . The self-consistent solution procedure is summarized as shown in Fig. 3. Using this method, interface trap charge can be applied to compact models of MOSFET or multigate MOSFETs [10], [12], [37]–[40]. C. Drain Current Expression For drift-diffusion current, drain current is given by the following: V ds R Qd Vch . (12) Ids = 2πμe f f L 0 Here μe f f is the effective mobility [39]. All symbols hold their normal meaning with Q given by (7). Applying gradual channel approximation the drain current expression now becomes μIds

2π R Q it = − ϕs Vds . (13) eff Cox Vgs − φ − L CO X

The excess potential on the drain side causes a reduction in electron concentration which in turn reduces the probability of ionization of trap states (11). It is thus important to consider an


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1 .6 Q i t s , A n a ly tic m o d e l

Q i t d , N u m e r ic a l s im u la tio n

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ϕ ss, ϕ ss, ϕ sd , ϕ sd,

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Fig. 5. Interface trap charge calculated from the analytic model compared with that extracted from numerical simulation, shown for both source and drain sides. Symbols: numerical simulation. Lines: analytical model.

averaged trap charge calculated for both the source and drain sides in the drain current expression. Applying Ward’s theory of charge partition [40], the drain current now be obtained as follows:

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0 .0 V gs [V ]

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Fig. 6. ϕs calculated from the analytic model compared with that extracted from numerical simulation, shown for both source and drain sides. Symbols: numerical simulation. Lines: analytical model.

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L in e s : A n a lytic m o d e l

10

where Q it s , Q it d , φss , and φsd are the interface trap charge and surface potential on source and drain sides, respectively.

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D ec reasin g V d s

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Ids [μA]

Ids

2π R = μe f f C ox

L (ϕ ss + ϕ sd ) Q it s + Q it d − Vgs −φ − Vds (14) 2C O X 2

- 0 .2

Ids [A]

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A n a ly tic m o d e l N u m e r ic a l s im u la tio n A n a ly tic m o d e l N u m e r ic a l s im u la tio n

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IV. M ODEL V ERIFICATION Fig. 7. Comparison of drain-source current calculated from (14) with numerical simulation for V ds = 0.10 V by using Lombardi CVT model. Symbols: numerical simulation. Lines: analytical model.

100 90 SS [mV/dec]

To verify our analytical model, a Silvaco ATLAS device simulator is used for comparison. The following parameters are considered in the analytical model and numerical simulation: R = 20.65 nm, L = 300 nm, tox = 2.5 nm, and T = 300 K. Ids –Vgs current calculated from (14) compared with simulation results, without any trap charge considered for general verification of the drain current expression, for Vds = 0.1 V and mobility μ = 150 cm2 /Vs is shown in Fig. 4. The analytic drain current expression (lines) is in excellent agreement with numerical simulation results (symbols). Q it for both the source and drain sides as a function of ϕs is shown in Fig. 5. Symbols and lines denote Q it obtained from the numerical simulation and calculated from (6)–(11), respectively. Analytically calculated trap charges are in excellent agreement with trap charge extracted from numerical simulation. Surface potentials for both the source and drain sides as a function of gate-bias are shown in Fig. 6. Symbols and lines denote ϕs obtained from the numerical simulation and that calculated from (6)–(11), respectively. Ids -Vgs characteristics as a function of Vds for device 3 from Fig. 2(a) is shown in Fig. 7. Lombardi CVT model is used for the numerical simulation and analytic model. Symbols and lines are the numerical simulation and analytic model by using extracted interface trap distribution shown in Fig. 2(a), respectively. The analytic model is in excellent agreement with the numerical simulation results and reproduces the experimental I − V curve for all operating regions (subthreshold, linear, and saturation) very well for low Vds bias values.

L ines : N um erical sim ulatio n Sym bo ls : R ef [1 2]

80 70 60 50

1E -3

0.01 Q it [ μ C ]

0.1

Fig. 8. SS as a function of interface trap charge. Symbols: [12], and solid line: numerical simulation. X-axis is log scale.

From (1), a relation between SS and Q it can be obtained, as shown in Fig. 8. The presence of distribution of the interface trap states (within the bandgap) as a function of surface potential has a combined effect on device SS performance as in (10); it is thus critical to analyze the effect of distribution of trap states on device SS performance. This is highlighted by Fig. 8 that compares SS as a function of Q it for numerical simulation (solid line) with a reference [12] (symbols) that considers only one interface trap level. Equivalent device parameters are used for fair comparison. The reference clearly underestimates SS

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for equivalent trap charge value. The advantage of our model over [12] and other models including BSIM.CMG is the ability to input user-defined Dit distribution in the model unlike [12] which only considers one trap level and BSIM.CMG which does not allow user-defined input of interface trap capacitance parameter Cit [37].

[13] Z. Chen, X. Zhou, G. Zhu, and S. Lin, “Interface-trap modeling for silicon-nanowire MOSFETs,” in Proc. IEEE Int. Rel. Phys. Symp., May 2010, pp. 977–980. [14] K. H. Cho, K. H. Yeo, Y. Y. Yeoh, S. D. Suk, M. Li, J. M. Lee, M. S. Kim, D.-W. Kim, D. Park, B. H. Hong, Y. C. Jung, and S. W. Hwang, “Experimental evidence of ballistic transport in cylindrical gate-all-around twin silicon nanowire metal-oxide-semiconductor fieldeffect transistors,” Appl. Phys. Lett., vol. 92, no. 5, pp. 052–102, Feb. 2008. [15] ATLAS Ver. 5. 10. 2., Silvaco Int., Santa Clara, CA, USA, 2005. [16] L. Zhang, L. Li, J. He, and M. Chan, “Modeling short-channel effect of elliptical gate-all-around MOSFET by effective radius,” IEEE Electron Device Lett., vol. 32, no. 9, pp. 1188–1190, Sep. 2011. [17] S. M. Sze and K. K. Ng, Physics of Semiconductor Devices. New York, NY, USA: Wiley, 1969. [18] A. Ford, J. Ho, Y. Chueh, Y. Tseng, Z. Fan, J. Guo, J. Bokor, and A. Javey, “Diameter-dependent electron mobility of InAs nanowires,” Nano Lett., vol. 9, no. 1, pp. 360–365, Jan. 2009. [19] J. G. Hwu, C. M. Lin, and W. S. Wang, “Effect of interface traps related to mobile charges on silicon n-channel metal/oxide/semiconductor field effect transistors determined by a charge-temperature technique,” Thin Solid Films, vol. 142, no. 2, pp. 183–189, Sep. 1986. [20] M. W. Dryfuse and M. Tabib-Azar, “A relationship between interface trap density and transconductance in 6H-SiC enhancement mode field effect transistors,” Solid-State Electron., vol. 39, no. 9, pp. 1331–1335, 1996. [21] G. I. Zebrev, E. V. Melnik, and D. K. Batmanova, “Using capacitance methods for interface trap level density extraction in graphene fieldeffect devices,” in Proc. 28th Int. Conf. Microelectron., May 2012, pp. 335–338. [22] A. Martinez, M. Aldegunde, N. Seoane, A. Brown, J. Barker, and A. Asenov, “Quantum-transport study on the impact of channel length and cross sections on variability induced by random discrete dopants in narrow gate-all-around silicon nanowire transistors,” IEEE Trans. Electron Devices, vol. 58, no. 8, pp. 2209–2217, Aug. 2011. [23] Y. Li and S. Yu, “Comparison of random-dopant-induced threshold voltage fluctuation in nanoscale single-, double-, and surrounding-gate field-effect transistors,” Jpn. J. Appl. Phys., vol. 45, no. 9A, p. 6860, 2006. [24] J. Lin, K. Chan, C. Chen, and M. Chiang, “Discrete impurity dopant fluctuation in multi-Fin FinFFTs: 3D simulation-based study,” in Proc. IEEE Conf. Electron Devices Solid-State Circuits, Dec. 2010, pp. 577–580. [25] Y. Ashizawa, R. Tanabe, and H. Oka, “Design perspective against random dopant fluctuation and process variation for scaling multi-gate devices,” J Comput. Electron, vol. 5, no. 4, pp. 319–322, Dec. 2006. [26] Y. Li and S.-M. Yu, “A study of threshold voltage fluctuations of nanoscale double gate metal-oxide-semiconductor field effect transistors using quantum correction simulation,” J Comput. Electron, vol. 5, nos. 2–3, pp. 125–129, Jul. 2006. [27] L. Xia and X. Gan, “Random dopant induced threshold voltage fluctuations in double gate MOSFET’s,” in Proc. 7th Int. Conf. Solid-State Integr. Circuits Technol., vol. 1. 2004, pp. 138–141. [28] H. Dadgour, V. De, and K. Banerjee, “Statistical modeling of metalgate work-function variability in emerging device technologies and implications for circuit design,” in Proc. IEEE/ACM Comput. Aided Design, Nov. 2008, pp. 270–277. [29] K. Endo, S. I. O’uchi, Y. Ishikawa, Y. Liu, T. Matsukawa, K. Sakamoto, J. Tsukada, H. Yamauchi, and M. Masahara, “Variability analysis of TiN metal-gate FinFETs,” IEEE Electron Device Lett., vol. 31, no. 6, pp. 546–548, Jun. 2010. [30] R. Wang, J. Zhuge, R. Huang, T. Yu, J. Zou, D.-W. Kim, D. Park, and Y. Wang, “Investigation on variability in Metal-Gate Si nanowire MOSFETs: Analysis of variation sources and experimental characterization,” IEEE Trans. Electron Devices, vol. 58, no. 8, pp. 2317–2324, Aug. 2011. [31] E. W. Enlow, R. L. Pease, and D. R. Alexander, “Subthreshold technique for fixed and interface trapped charge separation in irradiated MOSFETs,” Mission Research Corp., Univ. Volkswagen Mazda, Albuquerque, NM, USA, Tech. Rep. 28, Feb. 1987. [32] S. Sato, W. Li, K. Kakushima, K. Ohmori, K. Natori, K. Yamada, and H. Iwai, “Extraction of additional interfacial states of silicon nanowire field-effect transistors,” Appl. Phys. Lett., vol. 98, no. 23, pp. 233506-1–2335063-3, Jun. 2011.

V. C ONCLUSION In summary, we extracted interface trap distribution for GAAMOSFET device with TiN/SiO2 /Si gatestack. The extracted interface trap density followed the same trend as [6]. Further, a simple to implement compact model of the GAA Si NWFET including the extracted interface trap distribution, was developed. The model was based on self-consistent calculation of trap charge and surface potential on both the source and drain sides. The analytical drain current expression used an average value of inversion charge, interface trap charge, and surface potential on drain and source sides to reproduce experimental I − V curves. I − V curves from the newly developed model agreed very well with the experimental results for low Vds bias values. R EFERENCES [1] ITRS Reports and Ordering Information [Online]. Available: http://www.itrs.net/reports.html [2] X. Garros, M. Cassé, G. Reimbold F. Martin, C. Leroux, A. Fanton, O. Renault, V. Cosnier, and F. Boulanger, “Guidelines to improve mobility performances and BTI reliability of advanced high-k/metal gate stacks,” in Proc. VLSI Technol. Symp., 2008, pp. 68–69. [3] R. Wang, R. Huang, D.-W. Kim, Y. He, Z. Wang, G. Jial, D. Park, and Y. Wang, “New observations on the hot carrier and NBTI reliability of silicon nanowire transistors,” in IEDM Tech. Dig., 2007, pp. 821–824. [4] R. Gautam, M. Saxena, R. S. Gupta, and M. Gupta, “Hot-Carrier reliability of gate-all-around MOSFET for RF/microwave applications,” IEEE Trans. Device Mater. Rel., vol. 13, no. 1, pp. 245–251, Mar. 2013. [5] P. Magnone, F. Crupi, G. Giusi, C. Pace, E. Simoen, C. Claeys, L. Pantisano, D. Maji, V. Ramgopal Rao, and P. Srinivasan, “Noise in drain and gate current of MOSFETs with high-k gate stacks,” IEEE Trans. Device Mater. Rel., vol. 9, no. 2, pp. 180–189, Jun. 2009. [6] M. Casse, K. Tachi, S. Thiele, and T. Ernst, “Spectroscopic charge pumping in Si nanowire transistors with a high-κ/metal gate,” Appl. Phys. Lett., vol. 96, no. 12, pp. 123506-1–123506-3, 2010. [7] M. Rafik, X. Garros, G. Ribes, G. Ghibaudo, C. Hobbs, A. Zauner, M. Muller, V. Huard, and C. Ouvrard, “Impact of TiN metal gate on NBTI assessed by interface states and fast transient effect characterization,” in IEDM Tech. Dig., 2007, pp. 825–828. [8] G. M. Cohen, E. Cartier, S. Bangsaruntip, A. Majumdar, W. Haensch, L. M. Gignac, S. Mittal, and J. W. Sleight, “Interface state density measurements in gated p-i-n silicon nanowires as a function of the nanowire diameter,” in Proc. Device Res. Conf., Jun. 2010, pp. 277–278. [9] C. Driemeier, E. P. Gusev, and I. J. R. Baumvol, “Room temperature interactions of water vapor with HfO2 films on Si,” Appl. Phys. Lett., vol. 88, no. 20, pp. 201901-1–201901-3, 2006. [10] B. Iñíguez, D. Jiménez, J. Roig, H. Hamid, L. Marsal, and J. Pallarès, “Explicit continuous model for long-channel undoped surrounding gate MOSFETs,” IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1868–1873, Aug. 2005. [11] M. Cheralathan, G. Iannaccone, E. Sangiorgi, and B. Iniguez, “Analytical drain current model reproducing advanced transport models in nanoscale cylindrical surrounding-gate (SRG) MOSFETs,” J. Appl. Phys., vol. 110, no. 3 pp. 034510-1–034510-5, 2011. [12] Y. S. Yu, N. Cho, S. W. Hwang, and D. Ahn, “Implicit continuous current-voltage model for surrounding-gate metal-oxide-semiconductor field-effect transistors including interface traps,” IEEE Trans. Electron Devices, vol. 58, no. 8, pp. 2520–2524, Aug. 2011.


[33] S. Villa, A. Lacaita, L. Perron, and R. Bez, “A physically-based model of the effective mobility in heavily-doped n-MOSFETs,” IEEE Trans. Electron Devices, vol. 45, no. 1, pp. 110–115, Jan. 1998. [34] S. Jin, M. Fischetti, and T. Tang, “Modeling of electron mobility in gated silicon nanowires at room temperature: Surface roughness scattering, dielectric screening, and band nonparabolicity,” J. Appl. Phys., vol. 102, no. 8, pp. 083715-1–083715-14, 2007. [35] E. Ramayya, D. Vasileska, S. Goodnick, and I. Knezevic, “Electron mobility in silicon nanowires,” IEEE Trans. Nanotechnol., vol. 6, no. 1, pp. 113–117, Jan. 2007. [36] J. G. Simmons and G. W. Taylor, “Nonequilibrium steady-state statistics and associated effects for insulators and semiconductors containing an arbitrary distribution of traps,” Phys. Rev. B, vol. 4, no. 2, pp. 502–511, 1971. [37] S. Venugopalan, D. D. Lu, Y. Kawakami, P. M. Lee, A. M. Niknejad, and C. Hu, “BSIM-CG: A compact model of cylindrical/surround gate MOSFETs for circuit simulations,” Solid State Electron., vol. 67, no. 1, pp. 79–89, Jan. 2012. [38] H. Jung, “The analysis of breakdown voltage for the double-gate MOSFET using the Gaussian doping distribution,” J. Inf. Commun. Converg. Eng., vol. 10, no. 2, pp. 200–204, 2012. [39] H.-J. Park, P. K. Ko, and C. Hu, “A charge sheet capacitance model of short channel MOSFET’s for SPICE,” IEEE Trans. Comput. Aided Design, vol. 10, no. 3, pp. 376–389, Mar. 1991. [40] S. Oh, D. Ward, and A. Dutton, “Transient analysis of MOS transistors,” IEEE J. Solid-State Circuits, vol. 15, no. 4, pp. 636–643, Aug. 1980.

Faraz Najam (S’12) is currently pursuing the Ph.D. degree from Korea University, Seoul, Korea. His current research interests include analytical modeling, process development, and process-device integration of multiple gate nano-devices.

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K. H. Yeo, photograph and biography are not available at the time of publication.

D.-W. Kim, photograph and biography are not available at the time of publication.

Jong-Seung Hwang received the B.S. and M.S., and Ph.D. degrees in semiconductor physics from Yonsei University, Seoul, Korea, in 1984, 1986, and 1993, respectively. He is now a Research Professor in the SKKU Advanced Institute of Nanotechnology, SungKyunKwan University, Suwon, Korea.

Sangsig Kim received the Ph.D. degree in applied physics from Columbia University, New York, NY, USA, in 1996. He has been a Professor of electrical engineering with Korea University since 1999.

Yun Seop Yu (S’96–M’01–SM’11) received the B.S., M.S., and Ph. D. degrees in electronics engineering from Korea University, Seoul, Korea, in 1995, 1997, and 2001, respectively. He is currently an Associate Professor with Hankyong National University, Anseong, Korea. Sung Woo Hwang (M’97–SM’10) received the Ph.D. degree in electrical engineering from Princeton University, Princeton, NJ, USA, in 1993. Since 2012, he has been with Frontier Research Lab., Samsung Advanced Institute of Technology, Yongin, Korea, as Senior Vice President.

K. H. Cho, photograph and biography are not available at the time of publication.