Interleaved Power Converter with Current Ripple Cancelation at a Selectable Duty Cycle Julio C. Rosas-Caro, Jesus E. Valdez-Resendiz, Jonathan C. Mayo-Maldonado, Ruben Salas-Cabrera, Juan M. Ramirez-Arredondo, Joel Salome-Baylon.
Abstract— This work proposes a topology for a boost converter with the capability of canceling the input current ripple at an arbitrarily selected duty cycle. In the traditional interleaved boost converter the zero input current-ripple feature depends on the number of interleaved switching circuits. For example, two traditional interleaved converters have a zero input current ripple if and only if the duty cycle is 0.5. Other advantages of this proposed topology are: (i) the perfect ripple-cancelation duty-cycle can be selected without increasing the component count, (ii) higher voltage gain compared to the traditional interleaved boost converter; this feature is highly desirable in renewable energy applications, (iii) the voltage gain can be easily increased with a diode-capacitor voltage multiplier. Experimental results and a theoretical analysis are presented in this work. Index Terms— DC-DC power converters, Power conversion, Pulse width modulation converters, current ripple cancelation.
I. INTRODUCTION
I
N a boost converter design, the input current-ripple is required to be a small percentage of the input dc current. It is well known that the current ripple is smaller as the input inductor becomes larger. This is a constraint since increasing the input inductor increases the size and cost of the converter. Several solutions have been proposed for addressing this drawback of the boost converter [1-6]. In addition, a large inductor also slows down the open loop transient response of the converter. A brief review of the literature follows. (i) Interleaving or multi-phase converters, see Fig. 1(a), utilize several switching stages. They have several advantages compared to the traditional boost converter such as smaller input current-ripple with the same storage energy in inductors, the input current-ripple is zero for a fixed duty cycle i.e. when there are two switching stages connected in parallel as shown in Fig. 1(a) the input current ripple is zero for a D=0.5. A This work was developed under the project “Investigación de topologias de electronica de potencia” registered in DGEST 2011. Julio Cesar Rosas-Caro, Jesus Elias Valdez-Resendiz, Jonathan Carlos Mayo-Maldonado and Ruben Salas-Cabrera, are with the Madero City Technological Institute, Tamaulipas State, México (e-mail:
[email protected]). Juan Manuel Ramirez-Arredondo and Joel Salome-Baylon are with the Guadalajara Campus of CINVESTAV, México.
978-1-4577-0541-0/11/$26.00 ©2011 IEEE
disadvantage of topology in Fig. 1(a) is that the duty cycle for zero input current-ripple can not be selected; it depends on the number of switching stages.
Fig. 1. Converters with input current cancelation.
(ii) Several canceling circuits have been proposed in the literature, for example the circuit in Fig. 1(b) was presented in [1]; it is similar to the traditional interleaved converter, however the output of the switching structures are connected in series instead of being connected in parallel; there are two switching structures, one of them requires synchronous rectification as this switching structure drains a current with zero dc component; the main advantage is that the zero current-ripple duty cycle can be selected; the main disadvantage is that the component count increases but not the power rating of the converter. (iii) Other solution is the use of passive cancelation [2-3], see Fig. 1(c); this passive cancelation can be hybridized by employing an active circuit to improve the current cancelation [4]. Fig. 1(d) shows another circuit with passive cancelation [5-6]; inductors in Fig. 1(d) may be magnetically coupled and then the circuit becomes similar to one depicted in Fig. 1(c). This paper proposes a boost converter with input currentripple cancelation with advantages such as (i) the zero input current-ripple can be achieved with a arbitrarily selected duty cycle without increasing the component count, (ii) since the current canceling circuit drains dc current the power rating of the converter increases, (iii) the boost factor is higher than those factors of the available configurations shown in Fig. 1 and this factor may be extended by utilizing voltage multipliers.
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An experimental prototype was build, experimental results are provided along with theoretical analysis. II. PROPOSED TOPOLOGY The proposed topology is shown in Fig. 2(a), it contains two transistors, three diodes, two inductors and three capacitors. Both transistors switch complementary, i.e. when s1 is closed, s2 is open and vice-versa. The operation of the converter will be explained assuming the small ripple approximation [7] and the continuous conduction mode. In this case a positive current and voltage (positive according with the sign defined in Fig. 2) are assumed with a ripple that is considered to be small compared to the magnitude of DC component. The circuit will be introduced by employing several waveforms obtained from simulation and experimental tests.
the converter operates as the equivalent circuit shown in Fig. 2(b). During the time s1 is on, the diode d1 is reverse biased with VC1. Similarly, diode d3 is reverse biased with VC3. And then both diodes are open during this period of time. The current through inductor L2 allows the diode d2 to be closed since transistor s2 is open. Fig. 2(d) shows both inductor currents, the total input current and the switching sequence for s1 (the switching sequence for s2 is complementary). During the time s1 is on, the current through L1 is rising with a slope of Vin/L1 and L2 is discharging while C2 is charging. On the other hand, when s1 is off (and s2 is on) the resulting equivalent circuit is depicted in Fig. 2(c). During this time, the current in L1 discharges with a slope of (Vin-VC1)/L1; L2 is charging as a result of applying the input voltage and its corresponding current rises with a slope of Vin/L2. A key fact of the proposed converter can be derived from observing Fig. 2(d) and considering the explanation mentioned above. During each one of the switching states, one inductor is charging while the other one is discharging. Since both inductors can be calculated to have the same current ripple at an arbitrarily selected duty cycle, then the cancelation of the current ripple in the input voltage can be accomplished. As it was established earlier this fact stands as an advantage considering that in the traditional interleaved boost converter the duty cycle for accomplishing zero input current-ripple strongly depends on the number of switching stages. Currents depicted in Fig. 2(d) are shown for a converter that presents a zero input current-ripple at a duty cycle of D=0.7. III. ANALYSIS AND SELECTION OF COMPONENTS As it can be seen from Fig. 2, the proposed converter is an interleaving converter between the boost converter [7] and a three-switch high-voltage converter [8], the advantage of interleaving circuits with this characteristics are that the voltage gain is higher than interleaving circuits of the same type, furthermore, the duty cycle of each converter may be different, in this case the duty cycle of one is defined as the complement of the other one and this is the trick of the current ripple cancelation. A. Voltage gain In order to analyze the converter during steady state conditions the small ripple approximation [7] will be assumed. Considering the duty cycle d as the time when the switch s1 is closed over the total switching period Ts, see Fig. 1(d), the average voltages across the input inductors are given as
di L1 = d (vin ) + (1 − d )(vin − vC1 ) dt di L L 2 = d (vin − vC 2 ) + (1 − d )(vin ) dt
L Fig. 2. (a) Proposed topology, (b)-(c) equivalent circuits for each switching state, (d) magnitude of the total input current, current waveforms through the input inductors, and switching sequence.
The converter has two equivalent circuits corresponding to each one of the switching states. When s1 is on (and s2 is off)
(1) (2)
In steady state, the average value of variables in (1) and (2) are constant, average voltages across the inductors should be equal to zero. Under these conditions and using expressions
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B. Inductors and Input current ripple From Fig. 2(d), it is evident that the current ripple of each one of the inductors is given by
(1) and (2) the voltages across C1 and C2 may be expressed as
1 1− D 1 = Vin D
VC1 = Vin
(3)
VC 2
(4)
It is important to note that capital letters indicate steady state values. C2 clamps the voltage in C3 during the time when the switch s2 is on, see Fig. 2(c) ant then they get practically the same average voltage [8]. The load is connected to the voltage that results of adding VC1+VC3. The voltage gain of the converter can be written as:
Vo
Vin
( ) = 1 = VC1 + VC 3 Vin D(1 − D)
Vin V D DTS = in ⋅ L1 L1 f S V V (1 − D) = in (1 − D)TS = in ⋅ L2 L2 fS
∆iL1 =
(6)
∆i L 2
(7)
where f s denotes the switching frequency. The input current ripple, denoted by ∆in, is the difference between the current ripple of the inductors defined by equations (6) and (7), thus
(5)
∆iin =
The plot of the above voltage gain as a function of the duty cycle is shown in Fig. 3 (a).
Vin D (1 − D) − f S L1 L2
(8)
The converter can be designed for obtaining a zero input current-ripple at a certain duty cycle. This duty cycle can be calculated from the expected input and output voltages and using expression given by (5). For the purpose of obtaining a zero input current-ripple, expression (8) should be equal to zero and assuming that the duty cycle is known, then the following relationship between the inductors may be derived
L1 = L2
D (1 − D)
(9)
For example, if the expected input and output voltages are such that the duty cycle is equal to 0.75, then the value of L1 should be three times the value of L2 (according with (9)) for accomplishing zero input current-ripple. Once we have selected the duty cycle and calculated the values of each inductor, we can use (8) for analyzing the input current ripple through the full operation range. For example, if L1=3L2 and employing expression (8), then the input current ripple can be expressed as:
∆iin =
Vin D (1 − D ) Vin 4 = − D − 1 f S 3L2 L2 f S L2 3
(10)
It is clear that there is a linear dependence of current ripple on the value of the duty cycle. This fact is shown in Fig. 3(b). If the converter duty cycle is set to 0.6 (inductors are calculated for having a zero ripple at D=0.75) then the current ripple would be 0.2 times Vin/(fSL2). It is important to note that this current ripple is given in amperes (not in percentage). Finally and consistent with (3) and (4), the average current through the inductors can be defined as
Fig. 3. (a) voltage gain vs. duty cycle, (b) input current-ripple vs. duty cycle.
According to Fig. 3 (a) and expression (5), the minimum voltage gain is 4 and it is obtained when the duty cycle is equal to 0.5. If the duty cycle is smaller than 0.5 the gain increases again, therefore it is recommendable to employ duty cycles higher than 0.5.
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1 1− D 1 = Io D
I L1 = I o
(11)
I L2
(12)
C. Capacitors For calculating the adequate values of the capacitors we can use a procedure similar to the one used for calculating inductors. For example, during the time s1 is on, the load current is passing through capacitor C1, then
∆ vC 1 =
Io DTS C1
voltage. A diode-clamped multilevel converter can be connected as a load, as it is shown in Fig. 4(b). In Fig. 4(b) a branch of a five level inverter is connected as a load. Two branches may be connected in the same way providing higher voltage with nine levels.
(13)
For calculating the value of the capacitor C2, the period of time when s2 is open can be used, i.e.
∆ vC 2 =
I L2 DTS C2
(14)
Capacitor C3 is charged by C2 when the switch S2 closes connecting them in parallel, after this pretty fast dynamics, this capacitor is always discharging with the load current, the load current pass throw C3 in Fig. 2(b) and by C2 and C3 in Fig. 2(c) A good approach which doesn’t depend on the capacitance in C2 is to consider than the load current pass throw C3 all the time, in this case the voltage-ripple would be given by (15), the real voltage ripple in C3 is smaller than the one expressed in (15).
∆vC 3 =
Io TS C3
(15)
IV. POSSIBLE APPLICATIONS AND VARIATIONS The application of the proposed topology is mainly focused on renewable energy sources, where the power source should have a current-ripple as small as possible. This converter is able to provide a wide voltage gain (as it is shown in Fig. 3(a)) and a small current ripple for solar cell or fuel cells (as it is shown in Fig. 3(b)). A possible variation of the topology is to extend it by utilizing voltage multipliers. Hybridizing dc-dc converters with voltage multipliers has been previously proposed in the literature [9]. It provides higher voltage gain to the traditional boost converter and to the three-switch high-voltage converter. Since the boost converter processes most of the power, the three-switch high-voltage converter can be seen as a current cancelation circuit,
Fig. 4. (a) voltage multiplier extension (b) balancing mode.
V. EXPERIMENTAL RESULTS A prototype was developed to obtain some experimental results. The schematic of the implemented converter is the same as the one presented in Fig. 2(a). A picture of the prototype is shown in Fig. 5.
A. High voltage gain zero ripple converter The proposed converter can be extended to a multiplier boost converter [9] as it is shown in Fig. 4(a). An advantage of this topology is that helps to reduce the size of the input inductor and its corresponding series resistance. B. Balancing mode The converter is designed to have both switches operating in a complementary way. However, they can also operate with the same duty cycle in a truly interleaving manner. In this particular case, both output capacitors would obtain the same voltage. Furthermore, if the design is extended with voltage multipliers, all the output capacitors would have a balanced
Fig. 5. Implemented Prototype.
The variables and parameters of the prototype during the experimental tests are: Vin=20V, L1=360µH, L2=120µH,
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C1=33µF, C2=47µF, C3=10µF, Rout=100Ω, D=0.75 and fs=50kHz. The real voltage gain was tested in several points, they are shown in Fig. 6(a)
VI. CONCLUSIONS This paper proposes a boost converter with input currentripple cancelation with advantages such as: (i) the zero input current-ripple can be achieved with an arbitrarily selected duty cycle. (ii) the current canceling circuit drains dc current, therefore it contributes to increase the power rating of the converter. (iii) the boost factor is higher than the available configurations shown in Fig. 1; this boost factor may be extended by utilizing diode-capacitor multipliers. Those features are highly desirable in fuel cell applications. Experimental results are provided along with a theoretical analysis. Future work will be done in the research of this topology. REFERENCES [1]
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(b)
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(c) Fig. 6. (a) Experimental voltage gain (b) traces of both inductor currents 2 A/div (c) trace of the total input current 4 A/div.
Current were measured with sensing resistors, Fig. 6(b) shows the experimental traces of the input current and each one of the currents flowing through the inductors with 2 A/div. Fig. 6(c) shows the total input current with 4 A/div .
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