Interleaved PWM Control for Neutral Point Balancing in ... - IEEE Xplore

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the dual 2-level inverter fed dual 3-phase traction motors. [7,8] have drawn attention, no work has been done in developing an integrated inverter fed motor drive ...
Interleaved PWM Control for Neutral Point Balancing in Dual 3-Level Traction Drives *Subhadeep Bhattacharya, Student member, IEEE, Diego Mascarella, Member, IEEE, Benoit Boulet, Senior Member, IEEE, and Geza Joos, Fellow IEEE Electrical and Computer Engineering McGill University Montreal, Canada *[email protected] Abstract – This paper presents a new approach for neutral point balancing in dual three-level, T-type, neutral-pointclamped (T-NPC) inverters feeding a dual 3-phase permanent magnet synchronous machine (PMSM). Three-level Space Vector PWM (SVPWM) modulation scheme, without any separate capacitor balancing capability has been employed. However, by synchronously interleaving the switching pulses of both inverters, neutral-point balancing can be achieved over the entire torque/speed range of the traction motor, characterized by varying modulation indexes and load power factors. A control algorithm consisting of two PI loops has been developed in order to eliminate any mismatch between the two 3-level inverters. This technique alleviates the requirements for additional switching to achieve neutral point balancing, resulting in a reduction of both switching loss and AC waveform distortion. Simulation results verifying the proposed control algorithm are presented.

I. INTRODUCTION In automotive applications, traction drives typically commutate large motor currents with a frequency up to 20 kHz in order to achieve satisfactory control performance. Employing the conventional 2-level inverter to operate under such conditions results in substantial switching loss and associated EMI problems. In addition, for heavier electric vehicles (EV) like trucks and buses, a modular and scalable traction drive solution is required to fulfil the higher power requirements. With the advent of three-level NPC inverters [1], a higher power rated drive can be achieved by doubling the DC bus voltage of the system. Compared to a conventional 2-level inverter, the NPC inverter uses lower voltage rated switches which switch at half of the switching frequency. Thus, this topology incurs lower switching loss [2] and lower output voltage distortion. A variant of the NPC inverter, the T-NPC inverter has gained interest as it incorporated the advantages [3] associated with the conventional VSI, for instance, lower conduction loss when compared to the NPC inverter. Nevertheless, even with a 3level inverter, the power level of the system remains limited by the current ratings of the switches. This led to machine

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designs with higher number of phases [4-6] so that more power can be fed by using two or more inverters. Although the dual 2-level inverter fed dual 3-phase traction motors [7,8] have drawn attention, no work has been done in developing an integrated inverter fed motor drive system where two three-level inverters (dual T-NPC/NPC) will be feeding power to a dual 3-phase (or multiphase) machine. Previous works on the operation of a T-NPC inverter fed system focused on the neutral-point (NP) potential variation of the split DC bus. In [9], the influence of load current, power factor (pf) and the output voltage magnitude (i.e. modulation index) on NP balancing has been subjectively analyzed and control techniques using SVPWM have been studied in [10-14]. Most of the control techniques work with nearest three-vector (N3V) [10,11] or virtual vector scheme [12,13] where control strategies use and/or create more number of voltage vectors to nullify the unbalancing effects of medium and short voltage vectors. In [14] an even order harmonic cancellation technique has been discussed which creates more switching sectors to effectively reduce the NP potential variation. In all these previous studies, by using larger number of vectors/switching sectors, switching loss increases appreciably, almost by 15-20%. Furthermore, the effectiveness of these control strategies during transient operation, essential for electric vehicle traction drives, has not been reported. These studies also dealt with an inverter with output voltage fundamental frequency 50 or 60 Hz unlike an inverter for an automotive application that has a maximum output voltage fundamental frequency of 1000 Hz, thus narrowing down the bandwidth of NP balancing. Also, unlike previous studies, a typical automotive system will use a lower DC link voltage (400-700 V) to supply a high power motor, increasing the NP unbalance due to high current flow. Acknowledging the pros and cons associated with TNPC inverters and previous approaches, a new approach of using interleaved PWM (SVPWM) for the control of dual three-level T-type neutral-point-clamped (T-NPC) inverters has been presented in this paper. As shown in Fig. 1, both inverters use a single 400 V DC source and two input

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Figure 1: Dual T-NPC inverter withh a dual PMSM (neutral points of two three-phase stator windings are no ot connected)

capacitors (each 500 μF) as required by a single T-NPC inverter. The inverters feed power to a duall 3-phase surface mounted exterior rotor PMSM. The dual PM MSM consists of two separate three-phase stators (the rrespective stator windings are 180 electrical degrees aparrt) with a single exterior rotor. The main work of this papeer can be divided into three different parts. First, the flexibiliity introduced by employing the dual 3-phase PMSM topologgy on the control strategies of dual T-NPC inverters is discuussed. Secondly, based on the previous analysis, interleaveed PWM control strategy for neutral point balancing is exxplained. Finally, simulation results showing effectiveness of the control strategy for a wide range of operating pointts and conditions are presented.

of two sets of windings are not con nnected to each other. In this configuration, the mutual indu uctance between two sets of windings is very low, thuss allowing independent control/excitation of each three-phase winding set.

RFACE MOUNTED II. DUAL T-NPC WITH DUAL 3-PHASE SUR

EXTERIOR ROTOR PMSM M The dual T-NPC inverter supplies pow wer to a dual 3phase surface mounted exterior rotor PMSM (Fig.1). The dual PMSM consists of two separate three-pphase stators (the respective stator windings are 180 electrical degrees apart) with a single exterior rotor as shown in Figg. 2(i). The motor parameters have been tabulated in table I. The neutral points

(i)

TABLE I MOTOR PARAMETERS Item

Descrription/Value

Type of PMSM

Exterior rottor Surface PMSM

Maximum line-line voltage

2882 Vrms

Number of Poles

10

Motor Inductances (Lq,Ld)

00.02 p.u.

Base Speed

85500 RPM

Maximum Speed Maximum Continuous Torque/Power Maximum Transient Torque/Power

120000 RPM 70 N Nm/50 kW 180 N Nm/100 kW (ii) Figure 2: (i) Dual 3-φ surface mounted exterior rotor PMSM (ii) Two 1800 shifted 3-φ stato or winding sets

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In Fig. 2(ii), two sets of three-phase stator windings have been superimposed on each other with 180° phase difference within a single exterior rotor. It can be seen that if the currents flowing through each of the three-phase winding sets are also 180° phase-shifted, both currents corresponding to any phase (for instance for phase A: , ) are in the same direction, relative to rotor d-q axis. As they are in the same direction, torque produced by the dual PMSM will be the algebraic sum of torque produced by each motor (Eq. 1).

such a way that the current produced by one inverter is always 180° shifted compared to the other inverter. Hence, for seamless operation, the d/q-axis currents from each inverter need to be the same at every operating point. To ensure this, a synchronized interleaved dual PWM scheme has been developed which provides the switching pulses for each inverter, maintaining capacitor balancing from the output side current control. vdq_ref2

(1) nref

These 180° phase-shifted current sets are supplied by two three-level inverters.

vdq_ref1

ίqref Speed Current Controller Synchronization & Flux ίdref & Weakening Decoupling

dq

As seen from the previous section, the dual T-NPC inverter needs to supply 180° degree shifted sets of current to the dual PMSM. Referring to Fig. 3, (in which only a single leg of two T-NPC inverters have been shown) if the modulation for the two inverters is interleaved such that the uppermost IGBT of inverter 1 (IG11) gets similar pulse as lowermost IGBT of Inverter 2 (IG24) and IG12 of inverter 1 gets similar pulse as IG23 of inverter 2, the output currents will be 180° phase-shifted. In consequence, the upward(or downward) capacitor current due to inverter 1 will get substantially cancelled by downward (or upward) capacitor current due to inverter 2 (shown in Fig. 1 by arrows).Thus, NP unbalance created by first inverter will get substantially cancelled by the second inverter. Inv. 1 IG12 C1

IG11

IG13 IG14

N C2 IG22

IG21

n

θe

vref1

abc

θe

III. INTERLEAVED PWM CONTROL STRATEGY FOR DUAL T-NPC/PMSM

vref2

ίsq1 ίsd1

dq

ίsq2 ίsd2

dq

Interleaved Switching sequence PWM2 PWM1

T-NPC T-NPC Inverter1 Inverter2

ίabc1

abc

θe

abc

ίabc2 Dual PMSM

Positioning

Figure 4: Control structure for synchronized interleaved control of dual TNPC/PMSM

Control structure of synchronized interleaved control of dual T-NPC inverter and PMSM has been depicted in Fig. 4. The conventional field oriented control technique has been used to control each sets of stator windings using two inverters. As shown in Fig. 4, the speed controller and fluxweakening controller controls the speed of the system and generates the reference d/q-axis currents ( ). Though the dual three-phase machine has two sets of windings fed by two inverters, they will only experience a single torque and speed reference from the controller. Let us consider the following d-q current variables: , , , which are d-q axis currents of inverter 1 and inverter 2 respectively. Using scalar notation, the dq model for PMSM in the synchronous rotor reference frame is 0

IG23 IG24

0

Inv. 2

Figure 3: Single legs of a Dual T-NPC

0

for i

Now, without any proper control loop, it would be difficult to achieve perfectly out of phase winding currents, which can be caused by factors such as mismatches in dual inverter switching and machine inherent asymmetry/eccentricity causing impedance mismatch at the load side. To avoid any discrepancy between the inverters’ output currents, two inverters need to be carefully synchronized in

1,2 (2)

, , , are the d-q axis voltages produced by the inverter 1 and inverter 2 respectively. , , , are the motor winding resistance, motor d/q-axis inductance, motor electrical speed and back-emf constant respectively. Now the reference d-axis and q-axis currents ( and ) required to produce the reference torque needs to be the same as the summation of d-axis and q-axis currents produced by each inverter. As the torque produced by the dual PMSM is

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6

algebraic sum of torque produced by each motor, the dual PMSM torque reference needs to be met by equal contribution from both inverters. If there is any mismatch between inverters’ pulse patterns or machine impedances, the proposed current synchronization controller will work as follows:



0

8 ∆

0

A. Case I: Unbalance due to inverter switching mismatch

∆ ∆

0 0

0

Kp+K i/s

+ -

vdq.ref1

+

1/M

vdq1

-

System I +

v´dq1

ίdq1

-

1/(Ls+R)

ωeL

+ -

∆ίdq

Kp1+Ki1/s

Synchronizing Block

ίdq2 -

∆ ∆

Δίdq2

Kp+K i/s

+

+

vdq.ref2

vdq2 +

1/M

ωeλƒ

v´dq2 +

ωeL 1/(Ls+R) System II

Figure 5: Block diagram of dual inverter-PMSM synchronizing control

B. Case II: Unbalance due to motor impedance mismatch

0 0

Due to mismatches arising out of asymmetrical motor windings, stator teeth and air-gaps, motor resistance and leakage inductance of one set of stator winding may differ from another set of stator winding. Let us consider that there is a winding resistance mismatch between two sets of stator windings defined by

∆ ∆

4 So, the voltage deviation due to current deviation can be written as ∆

Δίdq1 -

3

∆ ∆



ίdq.ref +

ίdq.ref +

This can be simplified as ∆ ∆

9 ω eλ ƒ

Fig. 5 presents the block diagram of the dual inverter PMSM synchronizing control. One single inverter with the corresponding set of three-phase stator winding has been considered as a system. Let us consider that the current produced by system II ( ) gets deviated by an amount from the system I current ( ). So, the input voltage ∆ ) also gets deviated from the of the second inverter ( ). This can be input voltage of the first inverter ( expressed as: ∆ ∆

7





5

Due to this current deviation, the dc link capacitors become unbalanced. If the inverters’ input reference voltages are adjusted depending on the magnitude and polarity of the current deviation, the current flowing through each inverter can be controlled to have same magnitude. This will reduce the capacitor balancing problem arising from inverter switching mismatches. As seen in Fig.5, the current synchronizing controller uses two proportional-integral controllers (one each for d and q axis current mismatch) to regulate the current error between two T-NPC/PMSM systems. It adds the output of the PI controllers to the input reference voltage of the inverter such that if the system I outputs more current than the system II, the controller tries to lower first inverter’s input reference voltage which essentially reduces the current error between two systems and creates balanced dc-link capacitor voltages. Using this current synchronizing block, each inverter output current attains its reference current in a synchronous manner while regulating the relative error between them. Analytically written as



10

The input voltage of each stator winding set can be written as 11 12 In order to maintain balanced dc-link capacitor voltages, the current flowing through each inverter need to be same in magnitude. This can be achieved by employing the current synchronizing controller discussed in the previous section. Thus to maintain the current magnitudes, the controller will increase the input reference voltage of the inverter which is supplying power to the stator winding set having higher winding resistance. Analytically written, ∆

13

So, the current synchronizing controller depicted in Fig. 5 will automatically adjust the input inverter and motor voltages such that the input DC-link capacitors carry same currents and remain balanced.

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SIMULATION RESULTS

Capacitor voltage deviation (V)

IV.

Synchronising Signal (id1 - id2) (A) (iq1 - iq2) (A)

0.38

0.4

0.42

0.44 0.46 Time (s)

0.48

0.5

0.52

0.38

0.4

0.42

0.44 0.46 Time (s)

0.48

0.5

0.52

0.38

0.4

0.42

0.44 0.46 Time (s)

0.48

0.5

0.52

0.38

0.4

0.42

0.44 0.46 Time (s)

0.48

0.5

0.52

1 0.5 0

20 0 -20

50 0 -50

Figure 7: Effect of synchronizing signal on operation

-100 0.2

0.205

0.21

0.215 Time (s)

0.22

0.225

Item

0.23

Description/Value

Switching frequency

Inv. 1 Inv. 2

0

-200 0.2

TABLE II OPERATING CONDITIONS

Inv. 1 Inv. 2

0

200

0.205

0.21

0.215 Time (s)

0.22

0.225

0.23

0.205

0.21

0.215 Time (s)

0.22

0.225

0.23

Operating power factor

8 kHz (below base speed) 16 kHz (above base speed) 0.8-0.95 lagging (below base speed) 0.95-0.99 lagging & 0.5-0.95 leading (above base speed)

5

Capacitor voltage deviation (V)

0 -5 0.2

500 Inv. 1 Inv. 2

-500 0.2

0.205

0.21

0.215 Time (s)

0.22

0.225

0.23

Figure 6: Dual T-NPC output currents, neutral point currents, capacitor voltage deviation and output line voltages (Operating point: 2000 RPM, 40 Nm)

id1 & iq1 (A)

Fig. 7 shows the effectiveness of the synchronising control loop. At one point during operation, the synchronising control loop was switched off. This resulted in the dc-link capacitor voltages deviate from the nominal voltage (200 V). Also, the d and q axis currents of two inverters start deviating due to possible mismatches in switching pulses. Once the current synchronising control loop was switched on, it reduced the switching pulse mismatch between two inverters, thus restoring the dc-link capacitor voltages to the nominal value. Figs. 8-10 show the effectiveness of the synchronising control strategy for different operating torque and speed points of the dual PMSM. Different operating characteristics of the system have been tabulated in Table II. Thus, along the full speed range (0-12000 RPM); the effectiveness of the control strategy has been tested for different traction motor operating conditions.

20 0 -20

0

0.5

1

1.5 Time (s)

2

2.5

3

0

0.5

1

1.5 Time (s)

2

2.5

3

200 Torque (Nm)

0

Speed (RPM)

Inverter o/p voltages (V)

100 0 -100 -200 -300

100

Capacitor Neutral point voltage deviation currents (A) (V)

Inverter o/p currents(A)

Simulations have been conducted to check the effectiveness of the proposed control strategy. As shown in Fig. 6, the output current of one inverter is 180° phase shifted from the output current of the other inverter, as required by the dual PMSM stator windings. Due to these 180° phase-shifted output currents, the current through the neutral point due to first inverter (shown in blue) is opposite to the neutral point connection current due to the second inverter (shown in red). Thus the currents through each capacitor due to two inverters will also be opposite to each other, cancelling out each other and naturally balancing the capacitors (Fig. 6). Also, the output line and phase voltages of two inverters have 180° phase shift between each other which shows the effective interleaved operation of the dual T-NPC inverter. Thus, operation with the dual 3-phase PMSM enables the dual T-NPC inverter to effectively balance the DC link capacitors by supplying two 180° phase shifted three-phase current sets.

100 0

10000 speed Ref. speed

5000 0

0

0.5

1

1.5 Time (s)

2

2.5

100

3

iq1

0

id1

-100 0

0.5

1

1.5 Time (s)

2

2.5

3

Figure 8: Capacitor voltage deviation, torque, different speed and respective d and q axis current profile at 20 Nm load torque

As shown in Fig. 8, for 20 Nm torque, the dual motor runs for a wide range of speeds (1000-12000 RPM). As the DC link voltage of the traction drive is 400 V, the capacitor voltages need to be controlled around the nominal voltage of 200 V. It can be seen that using interleaved synchronized PWM strategy, the dual PMSM is able to supply the reference torques while keeping the input capacitor voltage

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50

0 -50

0

0.5

1

1.5

2 Time (s)

2.5

3

3.5

3.15

3.2

3.25 Time (s)

3.35

3.4

60 Nm

20 Nm 3.15

3.3

0

0.5

1

1.5

2 Time (s)

2.5

3

3.5

3.2

3.25 Time (s)

3.3

2.5

3

3.5

100 0

10000 3.35

3.4

speed Ref. speed

5000 0

0

0.5

1

1.5

10000

3.3

3.35

40

iq1

20 0 3.1

3.4

id1 3.15

3.2

3.25 Time (s)

3.3

3.35

3.4

2000 1000 0.2

Figure 9: Capacitor voltage deviation, torque, 5000 RPM speed and respective d and q axis current profile at 20 to 60 Nm change in load torque

In Fig. 10, operation the dual inverter-PMSM providing high torque has been presented. Two different operating points have been considered: i) Speed: 2000 RPM, Load torque: 150 Nm ii) Speed: 8000 RPM, load torque: 120 Nm. It can be seen that, during steady state operation, the controller operates as expected, maintaining dc-link neutral point balanced. During transient state (change in speed reference), as discussed earlier, the capacitor voltages deviate but again come back towards their nominal value during steady state of operation. As discussed in Section III, there might be mismatches between two sets of stator windings in terms of stator winding resistance, stator leakage/mutual inductances and flux linkages. To validate the proposed control strategy in the presence of those mismatches, three difference cases have been simulated. In case I, two similar sets of threephase windings have been considered. In case II and III the resistance and leakage inductance of one set of three-phase windings has been increased by 10%, respectively. An

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2 Time (s)

Figure 10: Capacitor voltage deviation, operating torque and speed at high torque operation

Capacitor voltage deviation (V)

3.25 Time (s)

q-axis voltage differences (V)

3.2

Torque difference (Nm)

3.15

0.205

0.21

0.215 Time (s)

0.22

0.225

0.23

10 Ideal R mismatch L mismatch

0 -10 0.2

0.205

0.21

20

0.215 Time (s)

0.22

-20 0.2

0.225

0.23

Ideal R mismatch L mismatch

0

0.205

0.21

0.215 Time (s)

0.22

0.225

0.23

10 0 -10 0.2

R mismatch L mismatch 0.205

0.21

100 Torque (Nm)

0 3.1

Speed (RPM)

speed Ref. speed

5000

(A)

id1 & iq1

Speed (RPM)

0 3.1

50

200 Torque (Nm)

4 2 0 -2 -4 3.1

Speed (RPM)

Torque (Nm)

Capacitor voltage deviation (V)

In Fig. 9, operation of the controller for change in torque reference has been presented. It can be seen that, during operation, the torque reference was changed from 20 Nm to 60 Nm. The system was able to track the reference torque without any significant capacitor voltage deviation, even during transient state. This can be attributed to the fact that unlike a speed reference change of operation, during this operation, the controller does not need to provide an acceleration/deceleration torque.

exaggerated increase has been considered to check the effect of the mismatch on different output variables of the system. In Fig.11, effect of impedance mismatches is shown. With resistance and leakage inductance mismatch, the controller readjusts the output voltages such that the current produced by each inverter is same, thus maintaining dc-link capacitors’ voltages balanced. Even with 10% impedance mismatch, the capacitor voltage deviation remains within a limit, whereas the difference between q-axis voltages of two inverters gets increased to take care of the impedance mismatch. Also, it can be seen that the torques produced in all three cases are similar although the torque ripple due to inductance mismatch is slightly higher than the other two cases. Capacitor voltage deviation (V)

deviation within a narrow band. The capacitor voltages remained within 2% of nominal voltage during steady state operation. During the transient state (when the reference speed was changed), capacitor voltage deviates towards the limit of the dc-link voltages. This can be attributed to the fact that the controller tries to track the reference speed and thus is not able to synchronize the output currents of the inverter.

0.215 Time (s)

0.22

0.23

R mismatch L mismatch Ideal

50 0 0.2

0.225

0.205

0.21

0.215 Time (s)

0.22

0.225

0.23

Figure 11: Effect of current synchronizing block on impedance mismatch

V.

DISCUSSION

The control scheme presented for the dual T-NPC inverter-PMSM topology is able to take care of the inverters’ switching pulse mismatches and respective stator winding impedance mismatches. However, there are some other issues of the system which require further study and are listed below. i. During transient operation, the proposed current synchronizing control is limited as shown in the paper. A separate synchronizing control loop which will operate during acceleration/deceleration of the motor needs to be implemented. ii. In practical inverter switching pulses, dead-times are always introduced to avoid shoot-through effect. The effects of these dead-times need to be considered in the current synchronizing block. iii. If there is any mismatch between two sets of threephase stator windings (arising due to machine asymmetry due to manufacturing tolerances), the current synchronizing loop will try to adjust itself so that one inverter will provide more voltage. So, one inverter will reach the limit of linear operation (m=1) faster than the other inverter. This may create synchronizing problems at that limit. A closed loop voltage balancing method with the effect of these non-idealities on capacitor voltage deviation will improve the overall effectiveness of this control strategy. VI.

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

CONCLUSION

This paper presented a technique for neutral point balancing in dual three-level inverter drives feeding dual three-phase PMSMs. An effective synchronized interleaved modulation scheme has been presented which coordinates both inverters to operate in a synchronous manner producing 180° phase shifted output currents, resulting in balanced dc link capacitors. It was shown that without the use of any separate capacitor balancing scheme; the dual 3level inverter topology effectively balanced the dc link capacitors. Simulation results demonstrated that the capacitor voltage deviation remained within an acceptable tolerance irrespective of operating speed or reference torque. Thus, the dual T-NPC/PMSM can be considered as an attractive topology for higher power vehicle segments taking the advantage of the benefits associated with low switching frequency operation due to absence of capacitor unbalance.

[11]

[12]

[13]

[14]

ACKNOWLEDGEMENT The authors would like to thank the Natural Science and Engineering Research Council of Canada (NSERC) and TM4 Electrodynamic Systems for their support under Automotive Partnership Canada (APC) project. REFERENCES [1]

[2]

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