Interleaved resonant converter with the balanced flying ... - IEEE Xplore

www.ietdl.org Published in IET Power Electronics Received on 16th January 2014 Revised on 6th June 2014 Accepted on 13th July 2014 doi: 10.1049/iet-pel.2014.0041

ISSN 1755-4535

Interleaved resonant converter with the balanced flying capacitors Bor-Ren Lin, Jeng-Yu Chen Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin 640, Taiwan E-mail: [email protected]

Abstract: This study presents a new DC/DC converter for high input voltage and high load current applications. To adopt low voltage rating power devices in high voltage applications, two split capacitors with four active switches are used in the primary side to reduce the voltage stress of power switches at Vin/2. Two flying capacitances are used to automatically balance two split capacitor voltages in every switching cycle. The proposed converter includes two resonant circuits to share the load current and to reduce the current stress of passive components. If the switching frequency is less than the series resonant frequency, power switches can be turned on under zero-voltage switching and rectifier diodes can be turned off under zero current switching. Therefore the switching losses on power semiconductors are reduced. The interleaved pulse-width modulation is adopted to further reduce the ripple current at output side. Thus, the output filter inductances can be reduced. Finally, experiments with a 1.2 kW prototype are provided to verify the effectiveness of the proposed converter.

1

Introduction

High-voltage power converters have been researched and developed for AC motor drives [1, 2], reactive power compensators [3, 4] and industry power applications. Conventional full-bridge DC/DC converters with high-voltage rated power switches are commonly adopted in industry power supplies with three-phase AC utility input. However, power metal-oxide semiconductor field-effect transistors (MOSFETs) with high voltage rating have large turn-on conduction resistance Rds which will result in high conduction losses and low circuit efficiency. To overcome this drawback, the series-connected switches approach [5] was introduced to reduce the voltage stress. However, the power switches may not be triggered at the same instant so that the actual voltage stress of the power switch is >Vin/2 under two switches. Qian and Lehman [6] presents a series-connected flyback converter to reduce the voltage stress. However, the voltage stress of power MOSFETs is still higher than Vin/2. The neutral-point diode clamp topology [7, 8], capacitor clamp topology [9] and series H-bridge topology [10] are normally adopted in multilevel converters to reduce the voltage stress of power switches for high voltage applications. However, power switches in conventional multilevel converters are operated at hard switching. In [11–15], three-level converters with soft switching scheme were developed to reduce the switching losses on power switches. Normally, the output capacitor of power switches and the leakage inductance of transformer are resonant at the transition interval to achieve zero-voltage switching (ZVS) on power switches. However, the ZVS range of power switches in these circuit topologies is depended on the leakage inductance. Resonant converters IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 447–457 doi: 10.1049/iet-pel.2014.0041

were presented in [16–19] to have high circuit efficiency and low switching losses on power switches. If the switching frequency is less than the series resonant frequency, the rectifier diodes at the secondary side can be turned off under zero-current switching (ZCS). Thus, the reverse recovery losses of rectifier diodes are improved. Power switches can be turned on at ZVS under wide range of load conditions in resonant converters. Thus, resonant converters have a wide ZVS range compared with the conventional ZVS converters. A new interleaved ZVS converter based on resonant converter is presented for high voltage application. Two half-bridge legs are connected in series at high voltage side such that the voltage stress of each power switch is clamped at Vin/2. To supply high load current and reduce current stress of passive components at output side, two circuit modules are connected in parallel with interleaved pulse-width modulation (PWM) scheme. Therefore the ripple currents at input and output side are reduced. In each circuit module, two balance capacitors are connected in series between the AC sides of two half-bridge legs to balance input split capacitor voltages. Thus, the input split capacitor voltages can be automatically balanced in each switching cycle. The resonant converter with variable frequency modulation is adopted to regulate output voltage. The input impedance of the resonant converter is an inductive load at the switching frequency so that power switches can be turned on under ZVS. If the switching frequency is lower than the series resonant frequency, then rectifier diodes can be turned off under ZCS. Experiments based on a laboratory prototype were provided to verify the effectiveness of the proposed converter. 447

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Circuit configuration

The circuit configuration of the conventional half-bridge resonant converter is given in Fig. 1a to achieve ZVS turn-on for all switches and possible ZCS turn-off for rectifier diodes if the switching frequency is less than the series resonant frequency. The voltage stress of S1 and S2 is limit to Vin. Power MOSFETs with 500 or 600 V voltage rating are normally adopted in the half-bridge resonant converter with 390 V input voltage. If the three-phase AC/ DC converter with power factor correction is used in high power applications, then the 900 V voltage rating MOSFETs or 1200 V insulated-gate bipolar transistors (IGBTs) must be adopted in the second-stage full-bridge DC/DC converter. To use low-voltage rating MOSFETs and high switching frequency in the modern switching converters, two half-bridge legs shown in Fig. 1b are connected in series at high voltage side to limit the voltage rating of power switches at Vin/2. However, two input split capacitor voltages cannot be automatically unbalanced and result in the unbalanced diode currents. Figs. 1c and d shows the circuit configurations of the three-level DC/DC converter with the clamped diodes and flying capacitor topologies, respectively. Owing to the clamped diodes or flying capacitor, the voltage stress of each power switch is clamped at Vin/2 in steady state. The duty cycle PWM

scheme is adopted to regulate output voltage. Power switches can be turned on under ZVS with the narrow load range. Fig. 2a gives the proposed converter with the balanced flying capacitor. Compared with Fig. 1c, two flying capacitors are used in Fig. 2a instead of two clamped diodes. There is only one flying capacitor with large root-mean-square (‘rms’) current in Fig. 1d. However, two flying capacitors with only half rms current rating are adopted in Fig. 2a based on the same power level. Therefore the cost of flying capacitor is less than that of high-voltage-clamped diodes. The capacitor with low rms current rating is cheaper than the capacitor with large rms current rating. Fig. 2b gives the circuit configuration of the proposed converter for high input voltage and high load current applications. The DC bus voltage after the three-phase PFC circuit is normally in the range of 750– 800 V. The proposed DC/DC converter has two resonant circuits operated by an interleaved PWM scheme to reduce the output ripple current and to reduce the current stress of active and passive components. Each circuit delivers half of load power. Cdc1 and Cdc2 form a capacitive divider to split the input voltage. In circuit 1, S1 and S3 have the same PWM signals and S2 and S4 have the same PWM waveforms. However, S1 and S2 are complementary to each other with a dead time to allow ZVS operation. Cr1 and Cr2

Fig. 1 Circuit configuration a Conventional half-bridge resonant converter b Resonant converter with two half-bridge legs c Three-level diode clamped PWM converter d Three-level flying capacitor PWM converter 448 & The Institution of Engineering and Technology 2015

IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 447–457 doi: 10.1049/iet-pel.2014.0041

www.ietdl.org are connected in series between the terminals d and e. If S1 and S3 are conducting and S2 and S4 are off, then vCr1 + vCr2 = VCdc1 . On the other hand, vCr1 + vCr2 = VCdc2 if S2 and S4 are conducting and S1 and S3 are off. Therefore VCdc1 and VCdc2 can be automatically equal to Vin/2 in a switching cycle. The voltage stress of each power MOSFET is clamped to Vin/2. In the proposed DC/DC converter, Vin is the input DC bus voltage and Vo is the output voltage. Co is output capacitance and Ro is load resistance. Cr1–Cr4 are the series resonant capacitances. Lr1 and Lr2 are the series resonant inductances. Lm1 and Lm2 are the magnetising inductances of transformers T1 and T2, respectively. S1–S8 are power switches. C1–C8 are the output capacitances of S1–S8, respectively. (Cr1, Cr2, Lr1 and Lm1) and (Cr3, Cr4, Lr2 and Lm2) compose two resonant tanks. D1–D4 are the rectifier diodes. The output voltage is controlled by pulse frequency modulation scheme. If the switching frequency is less than the series resonant

frequency at full load and maximum input voltage case, then all switches S1–S8 are turned on under ZVS and all rectifier diodes D1–D4 are turned off under ZCS. The switching losses of power switches are reduced and the reverse recovery losses of rectifier diodes are improved. Therefore the general fast recovery diodes can be used at the secondary side.

Fig. 2 Circuit configuration

Fig. 3 Main PWM waveforms

a Proposed converter with the balanced split capacitor voltages b Proposed interleaved resonant converter for high power applications

a Resonant converter 1 b Proposed interleaved resonant converter


3

Operation principle

The proposed converter is controlled by an interleaved PWM scheme to regulate output voltage and reduce the output ripple current. The PWM signals are generated by the pulse frequency modulation technique. The output voltage error is used to regulate the switching frequency to change the AC voltage gain of the resonant converter. Some assumptions are made to simplify the discussion of the proposed converter at steady state.

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Fig. 4 Operation modes 1–3 of the proposed converter in a switching cycle

Fig. 5 Operation modes 4–6 of the proposed converter in a switching cycle

a Mode 1 b Mode 2 c Mode 3

a Mode 4 b Mode 5 c Mode 6

(1) Two isolated transformers T1 and T2 are identical with the same magnetising inductances Lm1 = Lm2 = Lm and the same turns ratio n = np/ns1 = np/ns2. (2) Power switches S1–S8 have the same output capacitances C1 = … = C8. (3) Resonant capacitances are Cr1 = Cr2 = Cr3 = Cr4 = Cr. (4) Resonant inductances are identical Lr1 = Lr2 = Lr. (5) Input split capacitances Cdc1 = Cdc2.

Based on the PWM signals of S1–S8 and D1–D4, there are six operation modes (if the switching frequency fs is less than the series resonant frequency fr) in each resonant converter during one switching cycle. The key waveforms of resonant circuit 1 in a switching cycle are given in Fig. 3a. Fig. 3b shows the key waveforms of the proposed interleaved resonant converter. The output currents of two circuits are partially cancelled each other because of the interleaved

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www.ietdl.org PWM scheme. Since two resonant circuits have the same operation modes, only the operation modes of circuit 1 under fs < fr are discussed in the following to simplify the system analysis. Figs. 4 and 5 show the equivalent circuits of six operation modes in circuit 1 (if fs < fr). If the switching frequency fs > fr, then there are only four operation modes (modes 1, 3, 4 and 6) in a switching cycle. Before time t0, S1–S4 and D2 are in the off state. C1 and C3 are discharged and C2 and C4 are charged. 3.1

Mode 1 [t0 ≤ t < t1]

At t0, C1 and C3 are discharged to zero voltage. Since iLr1 is positive and iLr2 is negative, anti-parallel diodes of S1 and S3 are conducting. S1 and S3 can be turned on at this moment to achieve ZVS. In this mode, vS2 ,ds = VCdc1 , vS4 ,ds = VCdc2 and vCr1 + vCr2 = VCdc1 . Since iLr1 . iLm1 , D1 conducts, vLm1 = nVo and iLm1 increases. Cr1, Cr2 and Lr1 are resonant with the initial voltage vCr2 (t0 ) − nVo = Vin /2 − vCr1 (t0 ) − nVo in this mode (Fig. 4a). Thus, the resonant inductor currents and capacitor voltages in this mode are expressed as: (see (1,2 and 3)) where Zr = Lr1 /(Cr1 + Cr2 ) = Lr /(2Cr ) and vr =

1/ Lr1 (Cr1 + Cr2 ) = 1/ 2Lr Cr . At time t1, iLm1 = iLr1 . Therefore D1 and D2 are all off in resonant circuit 1. 3.2

Mode 2 [t1 ≤ t < t2]

At t1, iLm1 = iLr1 . Diodes D1 and D2 are in the off state. Since power switches S1 and S3 are still conducting, Cr1, Cr2, Lr1 and Lm1 are resonant in this mode (Fig. 4b). The inductor current iLr1 and capacitor voltages vCr1 and vCr2 are expressed as (see (4, 5 and 6 on bottom of the next page)) where Zp = (Lr1 + Lm1 )/(Cr1 + Cr2 ) = (Lr1 + Lm1 )/2Cr and vp = 1/ (Lr1 + Lm1 )(Cr1 + Cr2 ) = 1/ 2Cr (Lr1 + Lm1 ). At time t2, power switches S1 and S3 are both turned off. 3.3

Mode 3 [t2 ≤ t < t3]

At time t2, S1 and S3 are turned off. Since iLr1 , iLm1 , diode D2 is conducting and vLm1 = −nVo . In this mode, iLm1 decreases, C1 and C3 are charged and C2 and C4 are discharged because of iLr1 (t2 ) . 0. C2 and C4 can be discharged to zero voltage at time t3 if the energy stored in Lr1 at t2 is greater than the energy stored in C2 and C4 (Fig. 4c).

⎤ (Vin Cr1 /2(Cr1 + Cr2 )) − nVo − Cr1 vCr1 (t0 )/(Cr1 + Cr2 ) ⎢ ⎥ ⎢ ⎥ ⎢ + Cr2 vCr2 (t0 )/(Cr1 + Cr2 ) ⎥ ⎢ ⎥ iLr2 (t) = ⎢ ⎥ sin vr (t − t0 ) + iLr1 (t0 ) cos vr (t − t0 ) ⎢ ⎥ Zr ⎢ ⎥ ⎣ ⎦ ⎡

(1)

⎤ (Vin /4) − nVo − vCr1 (t0 )/2 + vCr2 (t0 )/2 ⎦ sin vr (t − t0 ) + iL (t0 ) cos vr (t − t0 ) =⎣ r1 Zr ⎡

Cr1 vCr1 (t0 ) Cr2 vCr2 (t0 ) Vin Vin Cr1 − nVo + iLr1 (t0 )Zr sin vr (t − t0 ) − − nVo − + cos vr (t − t0 ) 2 2(Cr1 + Cr2 ) (Cr1 + Cr2 ) (Cr1 + Cr2 )

vC (t0 ) vCr2 (t0 ) V V = in − nVo + iLr1 (t0 )Zr sin vr (t − t0 ) − in − nVo − r1 + cos vr (t − t0 ) 2 4 2 2

vCr1 (t) =

(2)

vCr2 (t) = nVo − iLr1 (t0 )Zr sin vr (t − t0 )

Cr1 vCr1 (t0 ) Cr2 vCr2 (t0 ) Vin Cr1 − nVo − + + 2(Cr1 + Cr2 ) (Cr1 + Cr2 ) (Cr1 + Cr2 ) cos vr (t − t0 ) = nVo − iLr1 (t0 )Zr sin vr (t − t0 )

vCr1 (t0 ) vCr2 (t0 ) Vin − nVo − + + cos vr (t − t0 ) 4 2 2

(3)

⎤ ⎡ (Vin Cr1 /2(Cr1 + Cr2 )) − Cr1 vCr1 (t1 )/(Cr1 + Cr2 ) + Cr2 vCr2 (t1 )/(Cr1 + Cr2 ) ⎦sin vp (t − t1 ) + iL (t1 ) cos vp (t − t1 ) iLr2 (t) = ⎣ r1 Zp ⎤ ⎡ (Vin /4) − vCr1 (t1 )/2 + vCr2 (t1 )/2 ⎦ sin vp (t − t1 ) + iL (t1 ) cos vp (t − t1 ) =⎣ r1 Zp (4) IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 447–457 doi: 10.1049/iet-pel.2014.0041

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Fig. 7 AC voltage gain and DC voltage gain at different frequency ratio fs/fr

in this mode. Since iLr1 (t5 ) , 0, C1 and C3 are discharged and C2 and C4 are charged. If the energy stored in Lr1 at t5 is greater than the energy stored in C1 and C3, then C1 and C3can be discharged to zero voltage at time Ts + t0. Then, the operating modes of resonant circuit 1 in a switching cycle are completed (Fig. 5c). Fig. 6 Equivalent circuit of the proposed converter for the derivation of steady-state model

3.4

4

The circuit characteristics of the proposed converter at steady state are discussed by the fundamental harmonic approach. Power transfer from input terminal Vin to output load Ro through two resonant tanks is related to the switching frequency fs. All harmonics of the switching frequency are assumed to be less than the fundamental component of the switching frequency. Thus, all harmonics are neglected in the system analysis. Fig. 6 gives the equivalent circuit of the proposed converter for the derivation of steady-state model. The equivalent circuit components in two resonant tanks are identical. Each resonant tank supplies Po/2 to output load. Since each power switch has 0.5 duty cycle, the input AC voltage of resonant tank is a square waveform with two voltage levels 0 and Vin/2. Therefore, the AC voltages can be expressed as

Mode 4 [t3 ≤ t < t4]

At t3, C2 and C4 are discharged to zero voltage and iS2 and iS4 are both negative. Thus, the anti-parallel diodes of S2 and S4 are conducting. Power switches S2 and S4 can be turned on at this moment to achieve ZVS. Since D2 is conducting and vLm2 = −nVo , iLm1 decreases in this mode. The voltage stresses of S1 and S3 are equal to VCdc1 and VCdc2 , respectively, and vCr1 + vCr2 = VCdc2 . Cr1, Cr2 and Lr1 are resonant with the initial voltage nVo − vCr1 (t3 ) in this mode (Fig. 5a). 3.5

Mode 5 [t4 ≤ t < t5]

At t4, iLr1 = iLm1 and D1 and D2 are all in the off state. Since S2 and S4 are still conducting, Cr1, Cr2 Lr1 and Lm1 are resonant in this mode (Fig. 5b). 3.6

Circuit characteristics

vac,1 (t) = vac,2 (t) = +

Mode 6 [t5 ≤ t < T + t0]

1 V

in

np n=2

Vin Vin + sin vs t 4 p sin nvs t = vDC + vf + vh

(7)

The fundamental rms values of vac,1 and vac,2 are equal to √ Vin /( 2p). Owing to the on–off states of D1–D4, the

At time t5, S2 and S4 are turned off and D1 is conducting. The magnetising inductance voltage vLm1 = nVo and iLm1 increases

Cr1 vCr1 (t1 ) Cr2 vCr2 (t1 ) Vin Vin Cr1 + iLr1 (t1 )Zp sin vp (t − t1 ) − − + 2 2(Cr1 + Cr2 ) (Cr1 + Cr2 ) (Cr1 + Cr2 )

vC (t1 ) vCr2 (t1 ) V V cos vp (t − t1 ) = in + iLr1 (t1 )Zp sin vp (t − t1 ) − in − r1 + cos vp (t − t1 ) 2 4 2 2 vCr2 (t) =

Cr1 vCr1 (t1 ) Cr2 vCr2 (t1 ) Vin Cr1 − + vCr3 (t) = −iLr1 (t1 )Zp sin vp (t − t1 ) + 2(Cr1 + Cr2 ) (Cr1 + Cr2 ) (Cr1 + Cr2 )

Vin vCr1 (t1 ) vCr2 (t1 ) − + cos vp (t − t1 ) cos vp (t − t1 ) = −iLr1 (t1 )Zp sin vp (t − t1 ) + 4 2 2 452 & The Institution of Engineering and Technology 2015

(5)

(6)


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Fig. 8 Measured PWM waveforms at full load a S1–S4 with Vin = 750 V b S1–S4 with Vin = 800 V c S1, S5, S2, S6 with Vin = 750 V d S1, S5, S2, S6 with Vin = 800 V

fundamental rms values of the magnetising inductance √ voltages are vLm1 ,rms = vLm2 ,rms = 2 2nVo /p. The rms values of the secondary√winding currents are equal to iT1 ,rms,s = iT2 ,rms,s = pIo /4 2. Thus, the load resistance Ro reflected to the transformer primary side is equal to Rac,1 = Rac,2 = Rac = 16n2 Ro /p2 . Thus, the AC resonant tank, such as Lr1 and (Cr1 + Cr2 = 2Cr), is excited by an effectively sinusoidal input voltage vac, f and drives the effective resistive load Rac. The input impedance Zin of the resonant tank is related to the switching frequency. Zin (fs ) =

Rac (j2pfs Lm ) 1 + j2pfs Lr + Rac + j2pfs Lm j2pfs (2Cr )

(8)

The AC voltage gain of the resonant tank can be expressed as (see (9)) |Gac (fs )| =

where fr = 1/(2p 2Lr Cr ), Q = Lr /(2Cr )/Rac , k = Lr/Lm, Cr1 = Cr2 = Cr3 = Cr4 = Cr, Lr1 = Lr2 = Lr and fs is the switching frequency. The DC voltage gain Gdc of the proposed converter is equal to Gdc = 4n(Vo + Vf )/Vin and Vf is the voltage drop on diodes D1–D4. If the input and output DC voltages are given, the switching frequency can be obtained by Gdc = |Gac( fs)|.

5

Design procedure

The experiments based on a laboratory prototype were provided to verify the effectiveness of the proposed converter. The electric specifications of the prototype converter are: Vin = 750–800 V, Vo = 24 V, Io = 50 A, series resonant frequency fr = 110 kHz. The select inductance ratio k = Lr/Lm = 0.2 in this prototype circuit. The design procedures of the proposed converter are: Step 1: Turns ratio of T1 and T2

Rac (j2pfs Lm )/(Rac + j2pfs Lm ) 1 = 2 (Rac (j2pfs Lm )/(Rac + j2pfs Lm )) 1 + k 1 − fr2 /fs2 +Q2 ((fs /fr ) − (fr /fs ))2 + j2pfs Lr + (1/j2pfs (2Cr ))


(9)

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Fig. 9 Measured waveforms of gate voltage, drain voltage and switch current a S1 at 25% load b S1 at 100% load c S2 at 25% load d S2 at 100% load

The minimum DC gain at maximum input voltage is designed to be unity at series resonant frequency. The turns ratio of T1 and T2 is obtained as

n=

np Vin,max 800 = = 8.11 = ns 4(Vo + Vf ) 4(24 + 0.67)

(10)

where Vf is the voltage drop on diodes D1–D4. The actual primary and secondary turns used in the prototype circuit are np = 34 turns and ns = 4 turns. Step 2: DC voltage gain The actual minimum and maximum DC gains of the proposed converter are

Gdc,min =

4(Vo + Vf )np 4 × (24 + 0.67) × 34 = Vin,max ns 800 × 4

= 1.048 454 & The Institution of Engineering and Technology 2015

Gdc,max =

= 1.118

(12)

Step 3: Q value at full load Fig. 7 gives the AC voltage gain curves against frequency ratio fs/fr with k = 0.2. In (12), the maximum DC gain of the proposed converter is equal to 1.118. From Fig. 6, it is clear that the maximum Q at full load should be < 0.3. Otherwise, the output voltage cannot be regulated at the desired voltage level. Therefore Q = 0.3 is selected in the prototype circuit under full-load condition. Step 4: AC equivalent resistance The AC equivalent resistance Rac at full load can be obtained as Rac =

(11)

4(Vo + Vf )np 4 × (24 + 0.67) × 34 = Vin,min ns 750 × 4

16n2 16 × (34/4)2 24 Ro = × = 56.22 V 2 p 3.141592 50

(13)

Step 5: Resonant capacitances and inductances IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 447–457 doi: 10.1049/iet-pel.2014.0041

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Fig. 10 Measured waveforms of capacitor currents, inductor currents and capacitor voltages at full load a vS1 ,gs , iCr1 , iCr2 and iLr1 of resonant circuit 1 b iLr1 , iLr2 and vCr1 − vCr4 c Vdc1, Vdc2, vCr1 + vCr2 and vCr3 + vCr4

and Q= Since fr = 1/(2p 2Lr Cr ) = 110 kHz Lr /(2Cr )/Rac = 0.3, the resonant inductances and capacitances are expressed in (14) and (15), respectively.

Lr1 = Lr2 = Lr =

QRac 0.3 × 56.22 ≃ 24.5 mH = 2pfr 2p × 110000

Cr1 = Cr2 = Cr3 = Cr4 = Cr =

1 8p2 Lr fr2

1 = 2 ≃ 43 nF 8p × 24.5 × 10−6 × (110000)2 Since

the

selected

k = Lr/Lm = 1/5.

The

(14)

(15)

magnetising


inductances of T1 and T2 are obtained in (16). Lm1 = Lm2 = Lr /k =

24.5 mH = 122.5 mH 1/5

(16)

Step 6: Power semiconductors and DC capacitances The input maximum voltage is 800 V. The voltage stress of power MOSFETs is limited to Vin,max/2 = 400 V. Thus, MOSFETs IRFP460 with 500 V voltage rating and 20 A current rating are used for power switches S1–S8. The output voltage is 24 V and load current 50 A. The voltage stress of rectifier diodes D1–D4 should be at least >2Vo = 48 V. The average diode current of D1–D4 is equal to 50 A/4 = 12.5 A. 60CPQ150 Schottky diodes with 150 V voltage rating and 60 A current rating are used for rectifier diodes D1–D4 in the prototype circuit. The input split capacitances Cdc1 = Cdc2 = 470 nF/450 V and output capacitance Co = 3000 μF/100 V. 455


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Fig. 11 Measured results of diode currents and output currents of two resonant circuits under full-load condition

under full-load condition. Two capacitor currents iCr1 and iCr2 are balanced and out of phase. Fig. 10b shows the measured waveforms of inductor currents iLr1 and iLr2 and capacitor voltages vCr1 − vCr4 under full-load condition. Two inductor currents iLr1 and iLr2 are balanced. Fig. 10c shows the measured results of two input split capacitor voltages VCdc1 and VCdc2 and capacitor voltages vCr1 + vCr2 and vCr3 + vCr4 under full-load and 800 V input voltage conditions. It is clear that two input capacitor voltages Vdc1 and Vdc2 are balanced at 400 V and vCr1 + vCr2 = vCr3 + vCr4 = VCdc1 = VCdc2 = Vin /2. Fig. 11 shows the measured waveforms of diode currents and output currents of two resonant circuits at full load. The output currents of two resonant circuits are balanced. Since the interleaved PWM scheme is adopted to control two resonant circuits, the resultant output current io1 + io2 has less ripple current compared with the output currents io1 and io2. Fig. 12 shows the measured circuit efficiencies of the proposed converter under different load conditions. The main power losses of the proposed converter are conduction losses on power MOSFETs and rectifier diodes, copper losses on transformer windings and core losses on magnetic cores.

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Fig. 12 Measured circuit efficiencies of the proposed converter

6

Experimental results

Based on the circuit parameters derived from the previous section, Test results are provided in this section to demonstrate the performance of the proposed converter. Figs. 8a and b show the measured PWM waveforms of S1– S4 at full load with different input voltage cases. S1 and S3 have the same PWM waveforms. Similarly, S2 and S4 are turned on/off at the same time. Figs. 8c and d show the measured PWM signals of S1, S5, S2, S6 at full load with different input voltage cases. It is clear that PWM signals of S5 and S6 are phase-shifted by one-fourth of the switching period with respective to PWM signals of S1 and S2, respectively. Fig. 9 shows the measured waveforms of gate voltage, drain voltage and switch current of S1 and S2, respectively, under 25 and 100% load conditions. Before switches S1 and S2 are turned on, drain currents iS1 and iS2 are negative to discharge the drain-to-source capacitor of S1 and S2. Thus, S1 and S2 can be turned on under ZVS. In the same manner, S3–S8 can be expected to achieve ZVS from 25 to 100% load. Fig. 10a gives the measured waveforms of gate voltage vS1 ,gs , iCr1 , iCr2 and iLr1 of resonant circuit 1 456 & The Institution of Engineering and Technology 2015

Conclusion

There are two main contributions in this paper. The first one is to overcome the unbalanced input split capacitor voltages in the conventional three-level diode clamp converter or three-level flying capacitor converter. Two flying capacitors are adopted at the AC terminal of two half-bridge legs. Thus, input split capacitor voltages can be automatically balanced in every switching cycle. The second one is to reduce the input and output ripple currents using interleaved PWM scheme for high load current applications. Therefore the current stress of power devices and passive components are reduced. Two-series half-bridge legs are connected in series to reduce the voltage stress of power devices at Vin/2 for high input voltage applications. To reduce switching losses, the resonant converter is adopted to regulate output voltage. In the proposed converter, all power switches are turned on under ZVS and rectifier diodes are turned off under ZCS. Compared with the conventional parallel three-level converter, the proposed converter has less power switch counts. The main drawback of this circuit topology is the current balanced issue. However, this issue can be overcome by the current balance control scheme. Finally, experiments with a 1.2 kW prototype are provided to demonstrate the performance of the proposed converter.

8

Acknowledgment

This project is partly supported by the National Science Council of Taiwan under Grant NSC 102-2221-E-224022-MY3.

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References

1 Rodriguez, J., Lai, J.-S., Peng, F.Z.: ‘Multilevel inverters: a survey of topologies, controls, and applications’, IEEE Trans. Ind. Electron., 2002, 49, (4), pp. 724–738 2 Malinowski, M., Gopakumar, K., Rodriguez, J., Pérez, M.A.: ‘A survey on cascaded multilevel inverters’, IEEE Trans. Ind. Electron., 2010, 57, (7), pp. 2197–2206 IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 447–457 doi: 10.1049/iet-pel.2014.0041

www.ietdl.org 3 Akagi, H., Kitada, R.: ‘Control and design of a modular multilevel cascade BTB system using bidirectional isolated DC/DC converters’, IEEE Trans. Power Electron., 2011, 26, (9), pp. 2457–2464 4 Ortuzar, M.E., Carmi, R.E., Dixon, J.W., Moran, L.: ‘Voltage-source active power filter based on multilevel converter and ultracapacitor DC link’, IEEE Trans. Ind. Electron., 2006, 53, (2), pp. 477–485 5 Song, T.T., Chung, H.S.H., Ioinovici, A.: ‘A high-voltage DC-DC converter with Vin/3 voltage stress on the primary switches’, IEEE Trans. Power Electron., 2007, 22, (6), pp. 2124–2137 6 Qian, T., Lehman, B.: ‘Coupled input-series and output-parallel dual interleaved flyback converter for high input voltage application’, IEEE Trans. Power Electron., 2008, 23, (1), pp. 88–95 7 Barros, J.D., Silva, J.F.: ‘Optimal predictive control of three-phase NPC multilevel converter for power quality applications’, IEEE Trans. Ind. Electron., 2008, 55, (10), pp. 3670–3681 8 Lewicki, A., Krzeminski, Z., Abu-Rub, H.: ‘Space-vector pulsewidth modulation for three-level NPC converter with the neutral point voltage control’, IEEE Trans. Ind. Electron., 2011, 58, (11), pp. 5076–5086 9 Ertl, H., Kolar, J.W., Zach, F.C.: ‘Analysis of a multilevel multicell switch-mode power amplifier employing the flying-battery concept’, IEEE Trans. Ind. Electron., 2002, 49, (4), pp. 816–823 10 Lin, B.R., Lu, H.H.: ‘New multilevel rectifier based on series connection of H-bridge cell’, IET Proc., Electr. Power Appl., 2000, 147, (4), pp. 304–312 11 Shi, Y., Yang, X.: ‘Zero-voltage switching PWM three-level full-bridge DC–DC converter with wide ZVS load range’, IEEE Trans. Power Electron., 2013, 28, (10), pp. 4511–4524


12 Duarte, J.L., Lokos, J., van Horck, F.B.M.: ‘Phase-shift-controlled three-level converter with reduced voltage stress featuring ZVS over the full operation range’, IEEE Trans. Power Electron., 2013, 28, (5), pp. 2140–2150 13 Lin, B.-R., Chung, S.-K.: ‘Analysis and implementation of a new zero-voltage switching dc converter with less active switches’, IET Power Electron., 2014, 7, (1), pp. 85–95 14 Rodrigues, J.P., Mussa, S.A., Barbi, I., Perin, A.J.: ‘Three-level zero-voltage switching pulse-width modulation DC-DC boost converter with active clamping’, IET Proc., Power Electron., 2010, 3, (3), pp. 345–354 15 Lin, B.-R., Hou, B.-R.: ‘Analysis and implementation of a zero-voltage switching pulse-width modulation resonant converter’, IET Power Electron., 2014, 7, (1), pp. 148–156 16 Yang, B.: ‘Topology investigation of front end DC/DC power conversion for distributed power system’. PhD dissertation, Virginia Polytechnic Institute and State University, 2003. 17 Fu, D., Liu, Y., Lee, F.C., Xu, M.: ‘A novel driving scheme for synchronous rectifiers in LLC resonant converters’, IEEE Trans. Power Electron., 2009, 24, (5), pp. 1321–1329 18 Beiranvand, R., Rashidian, B., Zolghadri, M.R., Alavi, S.M.H.: ‘A design procedure for optimizing the LLC resonant converter as a wide output range voltage source’, IEEE Trans. Power Electron., 2012, 27, (8), pp. 3749–3763 19 Lin, B.-R., Cheng, P.-J.: ‘Analysis of an interleaved zero-voltage switching/zero current switching resonant converter with duty cycle control’, IET Proc., Power Electron., 2013, 6, (2), pp. 374–382

457
