Interleaved zero-voltage switching three-level converter ... - IEEE Xplore

IET Power Electronics Research Article

Interleaved zero-voltage switching three-level converter with less output inductor counts

ISSN 1755-4535 Received on 15th January 2016 Revised 22nd October 2016 Accepted on 27th December 2016 E-First on 23rd February 2017 doi: 10.1049/iet-pel.2016.0038 www.ietdl.org

Bor-Ren Lin1 1Electrical

Engineering, National Yunlin University of Science and Technology, Touliu, Yunlin, Taiwan E-mail: [email protected]

Abstract: An interleaved three-level converter with the new current doubler rectifier is proposed. The main advantages of the proposed converter are zero-voltage switching (ZVS) turn-on for all switches, low output ripple current and less voltage stress of the output diodes. Two three-level converters connected in parallel are used to decrease the input current ripple, as well as to reduce the current rating of power switches. At the secondary side, two current doubler rectifiers sharing the same output filter inductors to reduce the output current ripple. Compared with the conventional centre-tapped rectifier and current doubler rectifier, the adopted current doubler rectifier has less output current ripple. The output capacitance of the power switch and the leakage inductance (or external inductance) are resonant at the transition interval so that the power switches can be turned on under ZVS. The adopted converter can be employed in high voltage input and high current output applications. Experiments with a prototype with 750–800 V input and 48 V/30 A output are provided to verify the theory analysis.

1 Introduction High power high efficiency power converters have been demanded at modern power supply units for the applications of internet of thing systems, telecommunication system, cloud computing systems, social network site systems, big data systems, plug-in hybrid electric vehicle battery chargers, medical instruments, and dc-based micro-grid systems. Generally the front-stage of the high power AC/DC converters is a three-phase power factor corrector (PFC) with boost voltage type [1] to achieve the main functions of high circuit efficiency, low line current harmonics, and high input power factor. However, the output voltage of three-phase PFC is higher than 800 V for universal three-phase utility voltage. Threelevel pulse-width modulation (PWM) converters [2, 3] have been developed with the main advantages of low voltage rating of power semiconductors, the balance input spilt voltages, and medium power applications. Soft-switching PWM techniques [4–8] including zero-voltage switching (ZVS) and zero-current switching (ZCS) have been proposed in three-level converters to reduce the switching losses on power semiconductors due to high switching frequency operation. Phase-shift PWM scheme is one of the most ZVS techniques to improve circuit efficiency in three-level converters. Resonant three-level converters with frequency modulation were discussed in [9–12] to realise the ZVS turn-on and possible ZCS turn-off for wide load range. The main drawbacks of the resonant three-level converters are wide switching frequency variations within the whole load range, high circulating current due to low inductance ratio to obtain high voltage gain, and large ripple current on output capacitor. To reduce the ripple current for high current output, the current doubler rectifier topology [13] using two filter inductors has been discussed to partially cancel two output inductor currents. Thus, the total output ripple current can be reduced and the size of inductors can be also reduced. Interleaved PWM techniques [14] are the other approaches to increase the total output power, lessen the current rating of power devices, and also reduce the input and output ripple currents. The ripple frequency is two times of switching frequency which can minimise the weight and size of the output filter. A new interleaved three-level converter with new current doubler rectifier for high voltage applications is presented to realise the main advantages of less current rating of power semiconductors, less output ripple current, ZVS turn-on for all IET Power Electron., 2017, Vol. 10 Iss. 7, pp. 707-716 © The Institution of Engineering and Technology 2017

switches, and less filter inductor counts. Two three-level circuits, which are operated by an interleaved PWM to lessen the output ripple current and reduce the current rating of power components, are adopted in the proposed converter. The current doubler rectifier is used at the secondary side to achieve current ripple cancellation. To reduce the filter counts, two filter inductors at the secondary side are both used in each three-level circuits. Based on the phaseshift PWM operation, the output capacitances of power switches and resonant inductance are resonant at the transition interval and ZVS turn-on of all switches are realised. Finally, experiments are conducted and provided to verify the theoretical analysis of the adopted circuit.

2 Circuit diagram Fig. 1a shows the circuit diagram of the conventional three-level converter with centre-tapped rectifier for high voltage input case such as DC traction or rapid rail train power unit. Based on the phase-shift PWM scheme, three voltage levels Vin/2, 0 and −Vin/2 are generated on the primary voltage vab. The voltage rating of each power switches is clamped at one half of input voltage. Fig. 1b gives the circuit configuration of the three-level converter with current doubler rectifier. The main advantage of this circuit topology is the output ripple currents ΔiL and ΔiL can be o1

o2

partially cancelled each other. Thus, the output inductances Lo1 and Lo2 can be reduced under the same allowed output capacitor current ΔiC in Figs. 1a and b. Fig. 1c shows the circuit diagram of o

an interleaved three-level converter with current doubler rectifier to achieve the low ripple currents at the input and output sides and reduce the current stress of the passive components for large current output. Therefore, the more power can be delivered to output load with less output ripple current in the interleaved threelevel converter compared with the conventional three-level converter. Fig. 2 gives the circuit configuration of the adopted interleaved three-level converter with new current doubler rectifier. Compared with the conventional interleaved three-level converter shown in Fig. 1c, the proposed converter can achieve the main advantages of less output inductor components, ZVS operation of power switches and less output ripple current. C1–C8 are input split capacitors. The clamped diodes Da–Dd and the flying capacitors Cf1 and Cf2 are 707

adopted to limit the voltage stress of power switches S1–S8 at Vin/2 and to balance the capacitor voltages V C = … = V C = V in /2. T1 1

8

and T2 are the isolated transformers to achieve the electrical isolation and transfer energy to output load. Lr1 and Lr2 are the primary leakage (or external) inductances. Lo1 and Lo2 are the output inductances and D1–D4 are the rectifier diodes. The gating signals of S5–S8 are phase-shifted one fourth of switching period with respective to the gating signals of S1–S4 in order to reduce the output ripple current. The energy stored on the output inductors Lo1 and Lo2 can be reflected to the primary side to help the ZVS operation of S1–S8.

3 Operation principle Two three-level converters with the clamped diode and flying capacitor are adopted in the adopted circuit to distribute input power through two converters and reduce the current rating of power semiconductors. The new current doubler rectifier is adopted at the secondary side to reduce the output ripple current. The secondary windings of two transformers are operated in series to reduce the turn ratio of transformers and minimise the primary current stress. The operation principle of the adopted circuit is based on the following assumptions. i. The capacitor V C = V C = V C = V C = V C = V C = V in /2. f1

f2

1

2

3

voltages

4

ii. The output capacitances of power switches Cr1=…=Cr8=Cr. iii. The output inductances Lo1 = Lo2 = Lo. iv. Power semiconductors are ideal. v. Transformers T1 and T2 are identical n1 = n2 = n and Lm1 = Lm2. vi. The output capacitance is large enough and the output voltage Vo is a constant voltage.

Fig. 1 Circuit diagram (a) Three-level converter with centre-tapped rectifier, (b) Three-level converter with current doubler rectifier, (c) Interleaved three-level converter with current doubler rectifier

Due to the switching states of S1–S8, Da–Dd, and D1–D4, twenty operation stages exist in the adopted circuit during one half of switching cycle. Fig. 3 shows the key waveforms of the adopted interleaved PWM circuit during one switching cycle. Two output inductor currents partially cancelled each other. The PWM waveforms for each half switching cycle are symmetrical each other. Thus, only the first ten operation stages shown in Fig. 5 are discussed to simplify the system analysis. Stage 1 [t0–t1]: At time t0, the diode current iD is decreased to 2

zero current. Switches S1, S2, S7 and S8 are in the on-state and the voltages vab = Vin/2 and vcd = −Vin/2. The secondary winding voltages of T1 and T2 are positive and negative, respectively (Fig. 4). The output inductor voltages vL and vL are negative and o1

positive, respectively.

o2

vL = − V o

(1)

o1

vL ≃ o2

V in V in V in + − Vo = − Vo 2n1 2n2 n

(2)

Thus, the inductor currents iL and iL decrease and increase, o1

Fig. 2 Circuit diagram of the adopted interleaved three-level converter with new less output inductors

708

o2

respectively. The diodes D2 and D4 are reverse biased. The secondary sides of transformers T1 and T2 and inductor Lo2 are connected in series to output load Ro. Energy is transferred to output load through transformers T1 and T2 and inductor Lo2. Stage 2 [t1–t2]: S8 turns off at time t1. Given that ip1(t1) > 0 and ip2(t1) Vo, the inductor currents iL and iL o1

o2

4

iD = iL − n2 | ip2| 4

(4)

o2

The primary currents ip1 and ip2 are given as: iL (t2) o2

n

ip2(t) = ip2(t2) +

2 Lr2i2p2(t3) ≥ CrV in /2

+

V in /2 − nV o n2 L L

(t − t2)

The time duration in stage 4 is given as. Δt34 = t4 − t3 =

7

Lr 2

d

CrV in −ip2(t3)

(8)

Stage 5 [t4–t5]: V C reaches zero voltage at time t4. The primary r6

current ip2 is negative and flows through the anti-parallel diode of S6. Therefore, S6 is turned on at this moment under ZVS. Since D3 and D4 are forward biased, the primary magnetising voltage of T2 is zero voltage. The primary inductor voltage vL = V in /2 and the

ip2(t) = ip2(t4) +

(5)

o2

V S , drop + V D , drop

(7)

r2

primary current ip2 increases in this stage.

(t − t2)

(6)

where V S , drop and V D , drop are the voltage drop on switch S7 and 7

r6

obtained in the following equation.

o2

decrease and increase, respectively, in this stage. The diode current iD is given in the following equation.

ip1(t) ≃

energy stored in Lr2 is greater than the energy stored in Cr6 and Cr7, then vC reaches zero at time t4. The ZVS condition of S6 is

d

diode Dd, respectively. Stage 4 [t3–t4]: Switch S7 turns off at time t3. The primary circulating current ip2(t3) charges Cr7 and discharges Cr6. If the IET Power Electron., 2017, Vol. 10 Iss. 7, pp. 707-716 © The Institution of Engineering and Technology 2017

V in (t − t4) 2Lr

The inductor current ip2 increases from −iL

o2, max

(9) /n to iL

o2, max

/n in

this stage and ends at time t5. The slopes of the diode currents iD

3

and iD are given by 4

diD (t) 3

dt

= −

nV in 4Lr

(10)

709

Fig. 4 Operation stages 1–5 of the first half switching cycle (a) Stage 1, (b) Stage 2, (c) Stage 3, (d) Stage 4, (e) Stage 5

710

IET Power Electron., 2017, Vol. 10 Iss. 7, pp. 707-716 © The Institution of Engineering and Technology 2017

Fig. 5 Operation stages 6–10 of the first half switching cycle (a) Stage 6, (b) Stage 7, (c) Stage 8, (d) Stage 9, (e) Stage 10

diD (t) 4

dt

=

nV in 4Lr


(11)

If the ripple currents on the output inductors can be neglected, then the time duration in this stage is obtained as follows.

711

Δt45 = t5 − t4 ≃

2I oLr nV in

(12)

In this stage, S5, S6, D3 and D4 are conducting and the secondary side voltage of transformer T2 is zero voltage. No energy is transferred to output load Ro through transformer T2. The duty loss in stage 5 is obtained as. Δt45 2I oLr f sw ≃ T sw nV in

dloss, 5 =

r3

r1

primary current ip1 decreases and can be expressed as: ip1(t) = ip1(t9) −

(13)

where Tsw and fsw are the switching period and switching frequency, respectively. Stage 6 [t5–t6]: Diode D3 is reverse biased at time t5. The primary side voltages vab = vcd = Vin/2 and the output inductor voltages vL = vL = V in /(2n) − V o. Thus, the primary currents ip1 o1

Stage 10 [t9–t10]: At t9, V C reaches zero voltage. The primary current ip1 > 0 and flows through the anti-parallel diode of S3. At this moment, S3 can be turned on under ZVS. Since D1 and D2 are forward biased, the primary magnetizing voltage of T1 is zero voltage. The primary inductor voltage vL = − V in /2 so that the

1

diD (t) 1

dt

o2

this stage. ip1(t) ≃ ip1(t5) + ip2(t) ≃ ip2(t5) −

V in /2 − nV o 2

Lr + n Lo

V in /2 − nV o Lr + n2Lo

(14)

(t − t5)

1

4

o1

o2

Stage 7 [t6–t7]: S1 turns off at time t6. Given that ip1 > 0, Cr1 is charged and Cr4 is discharged by ip1. Since the energy stored on the output inductor Lo2 is larger than the energy stored in Cr1 and Cr4, Cr4 can be discharged to zero voltage at time t7. The ZVS turn-on condition of S4 is given as. 2 (Lr1 + n2Lo2)i2p1(t6) ≥ CrV in /2

(16)

This stage ends at time t7 when V C reaches zero voltage. r4

Stage 8 [t7–t8]: At time t7, V C reaches zero voltage so that Da r4

is conducting. The primary current ip1 flows through the antiparallel diode of S4. Therefore, S4 can be turned on at this moment under ZVS. The primary side voltage vab = 0 and vL = 0 so that m1

diode D2 is forward biased. In this stage, vL = V in / 2n2 − V o, o1

vL = − V o, iL increases and iL decreases. The diode current iD o2

o1

is given as:

2

o2

iD = iL − n1 | ip1| 2

(17)

o2

The primary currents ip1 and ip2 are given as: ip1(t) = ip1(t7) − ip2(t) ≃

V S , drop + V D , drop

iL (t7) o1

n

2

+

a

Lr1

V in /2 − nV o n2 L L

(t − t7)

(t − t7)

(18)

(19)

o1

where V S , drop and V D , drop are the voltage drop on switch S2 and 2

a

diode Da, respectively. Stage 9 [t8–t9]: Switch S2 turns off at time t8. The primary circulating current ip1(t8) > 0 will charge Cr2 and discharges Cr3. If the energy stored in Lr1 is greater than the energy stored in Cr2 and Cr3, then vC reaches zero at time t9. The ZVS condition of power r3

switch S3 is obtained as follows. 2 Lr1i2p1(t8) ≥ CrV in /2

712

2

dt

(20)

=

nV in 4Lr

nV in 4Lr

(22)

(23)

If the ripple currents on the output inductors can be neglected, then the time duration in stage 10 is given as: Δt910 = t10 − t9 ≃

(15)

The diode currents iD = iD = iL + iL ≃ I o.

2

= −

diD (t)

o2

(t − t5)

(21)

The slopes of the diode currents iD and iD are given by

and ip2 and the output inductor currents iL and iL all increase in o1

V in (t − t9) 2Lr

2I oLr nV in

(24)

In this stage, no energy is transferred to output load Ro through transformer T1. The duty loss in stage 10 is obtained as follows. dloss, 10 =

Δt910 2I oLr f sw ≃ T sw nV in

(25)

At time t10, the operation in the first half switching cycle is completed. The operation behaviours of the adopted circuit in the second half switching cycle are symmetrical to the operation principles in the first half switching cycle.

4 Design consideration Comparison between the proposed converter and the conventional parallel three-level converter shown in Fig. 1c, two more filter inductors are used in the conventional parallel three-level converter. The charge and discharge times of Cr1–Cr8 in stages 2, 4, 7, and 9 are much less than the other time durations such that these stages are neglected in the following design consideration. Based on the voltage-second balance on output inductors Lo1 and Lo2, the voltage gain is obtained as: V o + 2V d deff d − dloss, 5 1 2I oLr f sw = = = d− V in n n n nV in

(26)

where deff and d are the effective duty cycle and duty cycle of the voltages vab and vcd and Vd is the voltage drop on the rectifier diodes D1–D4. In conventional parallel three-level converter, the voltage gain is (V o + V d)/V in = deff /n. Given the allowed maximum duty loss, the necessary primary inductances Lr1 and Lr2 can be obtained as follows. Lr1 = Lr2 = Lr =

dloss, maxnV in, min 2I o, max f sw

(27)

Based on the maximum effective duty cycle, the turn ratio of the transformers T1 and T2 is obtained as follows. n1 = n2 = n =

deff , maxV in, min V in,min 2I o, maxLr f sw = d − V o + 2V d V o + 2V d max nV in,min (28)


For the three-level converter, the ZVS condition of the lagging-leg switches is more difficult to be achieved. Based on the obtained primary inductance Lr and (7) and (20), it is clear that the minimum ZVS load condition of the lagging-leg switches is approximately given as. I o, min ZVS ≥ 2nV in, max

Cr 2Lr

o4

output inductances Lo1 and Lo2 can be derived in the following equation. 2(V o + 2V d) 3 − deff rI o f sw 4

(31)

In conventional parallel three-level converter, the output inductances Lo1–Lo4 are Lo1 = … = Lo4 = 4(V o + V d)(1 − deff )/(rI o f sw). It is clear that the proposed converter has less output inductance under the same ripple current factor r. The voltage stresses and average currents of the rectifier diodes D1–D4 are approximately expressed as: vD , stress = … = vD , stress = V in, max /(2n)

(32)

I D = … = I D = I o, max /2

(33)

4

1

4

In conventional parallel three-level converter, the voltage stresses and average currents of the rectifier diodes D1–D4 are approximately expressed as V in, max /(2n) and I o, max /4, respectively. Therefore, the average diode current in the proposed converter is two times the average diode currents in the conventional parallel three-level converter. If the ripple currents of power switches S1–S8 are neglected, the root-mean-square (rms) currents and the voltage stresses of power switches S1–S8 are approximately expressed as: (34)

Io iS , rms = iS , rms = iS , rms = iS , rms ≃ 2 3 6 7 2n 2

(35)

vS , sterss = … = vS , stress ≃ V in, max /2

(36)

8

8

clear that the proposed converter has less rms current on switches S1, S4, S5 and S8. The main power losses of the proposed converter are conduction losses on power semiconductors S1–S8 and D1–D4, transformers T1–T2 and inductors Lo1–Lo2. The main conduction losses of S1–S8 are expressed in the following equations. PS , loss = PS , loss = PS , loss = PS , loss ≃ deff 1

4

5

8

PD = PD = PD = PD ≃

Io 2 R 2n ON


2

3

4

I oV f 2

(38)

(39)

where Vf is a voltage drop on D1–D4 when D1–D4 are conducting. The main copper losses of T1–T2 and Lo1–Lo2 are expressed as: PT

1, copper

= PT

PL

≃

2, copper

o1, copper

Io 2 Io 2 rT, p + r 2n 2 T, s

(40)

Io 2 r 2 Lo

(41)

= PL

o2, copper

≃

where rT,p and rT,s are primary and secondary winding resistance of transformers T1 and T2, and rL is copper resistance of output o

inductors Lo1 and Lo2.

5 Experimental results On the basis of the design considerations in the previous section, the experiments with a laboratory prototype under 750 to 800 V input, 48 V/30 A output and 100 kHz switching frequency are provided to demonstrate the circuit performance. The maximum effective duty cycle is assumed as deff,max = 0.35. Based on (28), the turn ratio of T1 and T2 is obtained as: n1 = n2 = n =

deff , maxV in, min 0.35 × 750 = ≃ 5.3 V o + 2V d 48 + 2 × 0.74

(42)

The actual transformers T1 and T2 are implemented with TDK PC40EER35 core with Np = 32 turns, Np = 6 turns and Lm = 1.6 mH. The maximum duty cycle loss is assumed as dloss = 0.07. Based on (27), the primary inductances Lr1 and Lr2 are given as: Lr1 = Lr2 =

dloss, maxnV in, min 0.07 × (32/6) × 750 = ≃ 46.7 μH (43) 2I o, max f sw 2 × 30 × 100 × 103

On the basis of (32) and (36), the voltage stresses of the rectifier diodes and the power switches are given as: 1

4

(44)

vS , stress = … = vS , stress ≃ V in, max /2 = 800/2 = 400 V

In conventional parallel three-level converter, the rms currents and the voltage stresses of power switches S1–S8 are iS , rms = … = iS , rms ≃ I o /(2n 2) and V in, max /2, respectively. It is 1

7

vD , stress = … = vD , stress = V in, max /(2n) = 800/(2 × 32/6) ≃ 75 V

I o deff iS , rms = iS , rms = iS , rms = iS , rms ≃ 1 4 5 8 2n

1

6

2 1 Io R 8 n ON

where RON is turn-on resistance of S1–S8. The conduction losses on D1–D4 are expressed as:

(30)

where r is the current ripple factor of output inductors. In conventional parallel three-level converter, the ripple currents on the output inductors are ΔiL = … = ΔiL = (V o + V d)(1 − deff )/(Lo f sw) = rI o /4. The

1

3

1

(V o + 2V d) 3 ΔiL = ΔiL = − deff = rI o /2 o1 o2 Lo f sw 4

Lo1 = Lo2 = Lo =

2

(29)

It is assumed that two output inductor currents are equal to half of the load current Io/2. The ripple currents on the output inductors are expressed as follows.

o1

PS , loss = PS , loss = PS , loss = PS , loss ≃

(37)

1

8

(45)

The MBR40100PT and IRFP460 are used for the rectifier diodes D1–D4 and power switches S1–S8, respectively. Based on (31) with r = 0.3, the output inductances Lo1 and Lo2 are expressed as in the following equation. 2(V o + 2V d) 3 − deff rI o f sw 4 2 × (48 + 2 × 0.74) 3 = − 0.35 ≃ 44 μH 0.3 × 30 × 100 × 103 4 Lo1 = Lo1 =

(46)

The power MOSFETs IRFP460 at 400 V voltage stress has output capacitance Cr = 166 pF. Based on (29), the minimum ZVS condition of the lagging-leg switches is obtained as in the following equation.

713

Fig. 6 Measured PWM signals of power switches S1–S8 at full load

Fig. 8 Measured primary side voltage and currents at 800 V input and (a) 50% load, (b) 100% load

I o, minZVS ≥ 2nV in, max

Cr = 2 × (32/6) 2Lr

166 × 10−12 × 800 ≃ 11.4 A 2 × 46.7 × 10−6

Fig. 7 Measured primary side voltage and currents at 750 V input and (a) 50% load, (b) 100% load

714

(47)

Therefore, all power switches can be turned on at ZVS from 11.4 A (39%) load to 30 A (100%) load under the primary inductance Lr = 46.7 μH. Fast recovery diodes 30ETH06 are adopted for the clamped diodes Da–Dd. The DC input capacitances C1–C4 are 220 μF. The flying capacitances Cf1 and Cf2 are 1 μF. The output capacitance Co is 4000 μF. The stable constant output voltage is demanded in the proposed converter. Therefore, a resistor-based voltage divider, a voltage controller based on TL431 and an optocoupler with PC817 are adopted to regulate output voltage at the desired voltage value. The K-factor approach [15] is used to select control parameters in order to have minimum 60°phase margin. The experimental waveforms of the gate voltages of S1–S8 are given in Fig. 6. The gate voltages of S5–S8 are phase-shifted one fourth of switching period with respective to S1–S4. The experimental waveforms of the primary side voltages and currents at different input and output conditions are illustrated in Figs. 7 and 8. It can be seen that the primary voltages vab and vcd are interleaved each other. Similarly, the primary currents ip1 and ip2 are also interleaved by one fourth of switching period. Fig. 9 gives the experimental waveforms of the gate voltage, drain voltage, and switch current of the leading-leg switches S1 and S5 at 40% load and full load under 800 V input. It is clear that the drain voltage is decreased to zero before switch is turned on. Thus, the leading-leg switches S1 and S5 are all turned on from 40% load to full load. IET Power Electron., 2017, Vol. 10 Iss. 7, pp. 707-716 © The Institution of Engineering and Technology 2017

Fig. 9 Measured gate voltage, drain voltage and switch current at the leading-leg (a) S1 under 40% load, (b) S5 under 40% load, (c) S1 under 100% load, (d) S5 under 100% load

Since the other leading-leg switches S4 and S8 have the same operation behaviour as S1 and S5, switches S4 and S8 can be expected to be turned on under ZVS from 40% load. Fig. 10 shows the experimental waveforms of the gate voltage, drain voltage, and switch current of the lagging-leg switches S2 and S6 at 40% load and full load. The leading-leg switches S1 and S5 are also turned on from 40% load to full load. Fig. 11a illustrates the experimental waveforms of the primary side voltages and the secondary side currents at full load. Fig. 11b shows the output diode current iD + iD , capacitor current iC and the load current. It is clear that 1

2

o

two output inductor currents iL and iL are partially cancelled so o1

o2

that the output diode current iD + iD is almost constant and the 1

2

ripple current on the output capacitor Co is reduced. The ripple current ΔiC on the output capacitor in the proposed converter is o

about 2 A. Under the same power rating and same output inductance, the measured ripple currents ΔiC in conventional o

DC/DC converter with centre-tapped rectifier and current doubler rectifier are 3.3 and 2.7 A, respectively. Fig. 11c give the measured circuit efficiencies of the adopted circuit and the conventional interleaved three-level converter in Fig. 1c from light load to heavy load. The proposed converter has about 1% efficiency better than the conventional interleaved three-level converter.


Fig. 10 Measured gate voltage, drain voltage and switch current at the lagging-leg (a) S2 under 40% load, (b) S6 under 40% load, (c) S2 under 100% load, (d) S6 under 100% load

6 Conclusions A new interleaved three-level converter with new current doubler rectifier is presented for high voltage applications. Based on the phase-shift PWM scheme, the secondary windings of two transformers can be connected in series or parallel operation to reduce the output ripple current. The output inductor counts are also reduced in the adopted circuit compared with the conventional interleaved current doubler rectifier. Two three-level converters are operated by interleaved PWM scheme to decrease the current rating of active and passive components. In each three-level circuit, the voltage stress of power switches is limited at Vin/2 by using the diode clamped topology. The flying capacitors are adopted at the primary side to balance two input split capacitor voltages. The adopted converter can achieve ZVS for all power switches from 40% load to full load. To further improve circuit efficiency, the synchronous rectifiers instead of rectifier diodes can be used in the proposed converter to reduce conduction losses. Experiments are provided to verify the theoretical analysis.

7 Acknowledgments This project was supported by the National Science Council of Taiwan under grant nos. NSC 102-2221-E-224 −022 -MY3. The author also thanks Mr. Yu-Bin Nian for testing and measuring the experimental waveforms of the laboratory prototype. 715

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Fig. 11 Measured waveforms at the secondary side (a) the primary side voltages and the secondary side currents at full load, (b) the diode current iD + iD , output capacitor current iCo and load current under full load, (c) 1

2

measured circuit efficiencies of the proposed converter and the conventional interleaved three-level converter from 5% load to full load

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