Introduction - 3D Integration & Through Silicon Via(TSV). ➢ Why TSV for 3D
integration? Chip 3. Chip 2. Chip 1. Interposer 2. Interposer 1. Die attach film.
Introduction - 3D Integration & Through Silicon Via(TSV) Through silicon via (TSV) Vertical electrical interconnection passing through the silicon
TSV
Si chip
Why TSV for 3D integration?
Source : STATS ChipPAC
Chip 3 Interposer 2 Wire bonding Chip 2
Chip 3
TSV
Interposer 1
Chip 2
TSV
Chip 1 Underfill
TSV
Chip 1 Die attach film Substrate
< 3 chips + 2 interposers stack with wire bonding>
Bump
Substrate
< 3 chips stack with TSV >
Pad area for wire bonding
Smaller package size
Long looped Au wire
Short interconnect length
Nano Packaging & Interconnect Lab.
Introduction - Former TSV Interconnection Methods & Limits Chip
TSV Metal bump
< Cu-Cu Metal/polymer hybrid bonding> TSV
Chip
Metal bump
Substrate chip
TSV
Dielectric polymer
Chip
Metal bump Chip
TSV Metal bump
TSV
Chip
Metal bump
Dielectric polymer
Underfill Substrate chip
Voids
Substrate chip
Cracks
• Long bonding time(< minutes)
• Long bonding time(30min)
• Repeat of under-fill
• Additional polymer patterning
• Void trap during under-fill
• Semi-solid state after polymer patterning
Nano Packaging & Interconnect Lab.
Introduction - Why TSV Conducting Adhesives(TCAs)/Solder Joint? What is TCA?
TSV
+
Conducting
+
Adhesive • Substitution of underfill
TSV Solder bump
Cu pillar
• No need of patterning
Chip
Bonding process with TCA TCA
Pressure & temperature
Si chip TSV TCA
TSV & bumped wafer Silicon wafer
Si chip with TCA
*Wafer-level lamination Dicing of TCA-applied of TCA on the wafer wafer TCA coated on releasing film
*Patent issued : US6518097
Nano Packaging & Interconnect Lab.
Si wafer
Chip to wafer bonding using TCA/solder joint
Introduction - Why TCA/solder Hybrid Joint? Features of TCAs TSV TCA
Chip Solder bump
TSV TCA
Chip Solder bump Substrate chip
Curing temperature
No need of underfill & patterning Gap filling by resin flow Short bonding time
Nano Packaging & Interconnect Lab.
Substrate chip
• Joint stability Viscosity • Joint formation
Experiments – Test Vehicles (TSV simulated SnAg coated Cu post bump) Micro-bumped chip Substrate chip design
Single Bump Joint resistance At the corner
• Dimension : 13 mm X 13 mm • Pads : 5 daisy resistance & 4 joint resistance circuits
Daisy resistance
Bonding chip design • Dimension : 6 mm X 6 mm • Bump
Successful bonding of 40 μm pitch TCA/solder hybrid joints in 10 sec! Nano Packaging & Interconnect Lab.
Result – Humidity Test TCA 1 (160 oC, 450 Pa·s @ 130 oC) Pressure : 16.32 MPa Temperature : 40~250 oC (5 oC/s)
85 oC/85 %RH test
Cumulative distribution (%)
100
0h 300 h 500 h
80 60 40 20 0 0
20
40
60
Joint resistance (m )
80
100
< Cross-sectioned image of the bumps after 500 hours of 85 oC/85 %RH test>
No failure was found until 300 h of the humidity test for TCA/solder hybrid joints. Nano Packaging & Interconnect Lab.
Conclusion & Ongoing Works Conclusion 1. TCA/solder hybrid joint was demonstrated for TSV interconnection using new TCA materials. 2. TCA material properties was designed for joint interconnection. Curing temperature → joint stability Viscosity → joint interconnection @ 600 Pa·s
3. 40 μm fine pitch capability was demonstrated in 10s bonding time.
Ongoing works 1. Void elimination 2. Optimization of the TCA materials ◎ Curing agent, epoxy, & thermo-plastic polymers
3. 3D TSV chip stacking using TCAs ◎ Process & TCA properties optimization
TCA/solder as a new solution for the 3D-TSV vertical interconnection Nano Packaging & Interconnect Lab.
