IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 5, MAY 2010
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Investigation of State Stability of Low-Resistance State in Resistive Memory Jubong Park, Minseok Jo, El Mostafa Bourim, Jaesik Yoon, Dong-Jun Seong, Joonmyoung Lee, Wootae Lee, and Hyunsang Hwang
Abstract—We investigated the state stability of the lowresistance state (LRS) in a resistive switching memory having a Pt/Cu : MoOx /GdOx /Pt structure. Various resistance values of LRS were accurately controlled using an external load resistor connected in series with the resistive memory device. We found that the retention time decreased with an increase in the resistance of LRS. We performed accelerating tests for resistance transition from a low- to a high-resistance state under temperatures ranging from 200 ◦ C to 250 ◦ C. A predicted resistance of LRS for a ten-year retention period at 85 ◦ C was determined based on the Arrhenius law. Index Terms—Resistance random access memory (ReRAM), resistive memory, retention.
I. I NTRODUCTION
R
ECENTLY, resistance random access memory (ReRAM) has been extensively studied for applications in nextgeneration nonvolatile memory due to its characteristics of low power consumption, high-speed operation, ease of fabrication, and high-density integration. Among the several types of resistive switching mechanisms that have been suggested, switching based on the formation and rupture of a conducting filament (CF) has several advantages such as high-speed operation and a large resistance ratio that allows for multibit data storage and high scalability because of the area-independent property. However, problems arising from switching fatigue, such as degradation of switching durability and reproducibility under continuous probing, and nonuniform distribution of switching parameters remain unresolved. These problems indicate randomly formed filament buildup while switching from a highresistance state (HRS) to a low-resistance state (LRS). Hence, the control and optimization of CF is essential for the practi-
Manuscript received January 8, 2010. Date of publication March 18, 2010; date of current version April 23, 2010. This work was supported in part by the National Research Program of the 0.1-Terabit Nonvolatile Memory Development Project, by the National Research Laboratory Programs of the Korea Science and Engineering Foundation, by the World Class University Program of the Ministry of Education, Science and Technology of Korea, and by Hynix. The review of this letter was arranged by Editor S. Kawamura. J. Park, M. Jo, J. Yoon, D.-J. Seong, J. Lee, and W. Lee are with the Department of Materials Science and Engineering, Gwangju Institute of Science and Technology, Gwangju 500-712, Korea. E. M. Bourim is with the Department of Nanobio Materials and Electronics, Gwangju Institute of Science and Technology, Gwangju 500-712, Korea. H. Hwang is with the Department of Materials Science and Engineering and the Department of Nanobio Materials and Electronics, Gwangju Institute of Science and Technology, Gwangju 500-712, Korea (e-mail:
[email protected]). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2010.2042677
Fig. 1. (a) Schematic diagram of the Pt/Cu : MoOx /GdOx /Pt structure. (b) Area-independent properties of the LRS resistance and reset current. (c) Temperature dependence of RLRS .
cal application of filament-conduction-based resistive memory. Recently, many research groups have proposed the feasibility of multibit operation, which is achieved by controlling the resistance of LRS (RLRS ) [1]–[5]. In addition, some groups have investigated the effect of RLRS on the retention property under stress bias [6]–[8]. In this letter, we investigates the effect of RLRS on the retention characteristics of a Pt/Cu : MoOx /GdOx /Pt memory cell. We analyzed the retention time accelerated under different temperatures for various RLRS controlled by associating an external load resistor (Rex ). Accordingly, we deduced a maximal RLRS to guarantee ten years of retention at 85 ◦ C while simultaneously preserving a wide window for multilevel operation, based on the Arrhenius law. II. E XPERIMENTS The Pt/Cu : MoOx /GdOx /Pt memory cell structure was fabricated following the scheme shown in Fig. 1(a). The detailed fabrication process has been explained in our previous study [9]. The LRS was programmed at room temperature (RT) with various Rex in series with the memory cell to obtain various RLRS . After programming at RT, temperature-accelerated retention tests were performed under temperatures ranging from 200 ◦ C to 250 ◦ C. To avoid the effect of stress bias on the retention characteristics [6]–[8], the bias was applied only at read operations.
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IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 5, MAY 2010
Fig. 3. (a) Evaluation of the activation energy by temperature-dependent retention characteristics. (b) Expected retention time at 85 ◦ C according to the different intermediate resistance states.
Fig. 2. (a) Dependence of MTTF on the LRS resistance and temperature. (b) Typical trace of the retention characteristics. The retention property degrades with an increase in the LRS resistance and temperature.
III. R ESULTS AND D ISCUSSION Initially, the device is in HRS. To form the initial CF, the device requires a higher voltage (6–8 V) than the typical set voltage. This is called the forming process. After the forming process, the device exhibits repetitive switching of a bipolar nature (not shown here). To verify the filament-conduction-based switching mechanism, we measured the absence of the area scaling of RLRS and the reset current (Ireset ), as shown in Fig. 1(b). The device areas are 10 × 10, 50 × 50, 70 × 70, 120 × 120, 200 × 200, and 320 × 320 μm2 . For consistency of results, we maintained a constant compliance current of 200 μA. Therefore, based on the absence of the area scaling of RLRS and Ireset , conducting AFM study [10], the resistance switching behavior in the duallayered Pt/Cu : MoOx /GdOx /Pt structure corresponds to the formation and rupture of a Cu filament. The detailed switching mechanism and switching characteristics have been reported in our previous study [9], [10]. To achieve high-density data storage implementation in a ReRAM device, multilevel operation based on the modulation of RLRS to different magnitudes during set operation is a potential technical solution. However, the instability of the LRS caused by the resistance drifts needs to be investigated to improve device reliability and performance [6]–[8]. Various RLRS could be controlled by connecting Rex at set operation. RLRS below critical RLRS exhibits metallic behavior [RLRS ∝ temperature (T )], whereas that above RLRS exhibits semiconducting behavior (RLRS ∝ 1/T ), as shown in Fig. 1(c). Despite the LRS, semiconducting behavior is observed because of the lower density of the Cu elements, which contributes to the magnitude of RLRS [11]. Fig. 2(a) shows the mean time to failure (MTTF) under different temperatures (200 ◦ C to 250 ◦ C)
for memory cells in LRS with various RLRS . To confirm the reproducibility of the retention measurements, we checked the plotted data five times on five identical cells for each temperature. It should be noted that the retention time exhibits a large fluctuation due to the random shapes of the CF. These fluctuations are currently being investigated. For greater clarity, one of the results was shown in Fig. 2(b). We set the retention failure time (tfailure ) as the time at which the current falls below 10 nA. This current is ten times higher than the HRS current. Initially, the decrease in current occurs because of accelerated ion migration caused by thermal stress. It should be noted that the bias was applied only for the reading operation during the acceleration test. Therefore, the effect of stress bias on the retention characteristics can be ignored. At the onset of complete dissolution, the current is decreased abruptly. Two tendencies are observed in our results. One is the exponential dependence of tfailure on the temperature for a given RLRS , and the other is accelerated degradation of state stability as RLRS is increased. This instability is attributed to the acceleration of the Cu ion migration rate due to the increased thermal stress and is consistent with previous results [1], [6]–[8], [13]–[15]. Hence, a continuous reduction in Cu impurity density that determines RLRS is likely to be the origin of stability degradation. Based on the experimental result shown in Fig. 2(a), we plotted the measured retention time versus the reciprocal test temperatures, as shown in Fig. 3(a). The Arrhenius behavior [1], [12]–[14] is expressed as follows: Ea
tfailure ∝ e kB T where tfailure is the failure time of data retention, Ea is the activation energy of RLRS in the absence of an electric field, kB is the Boltzmann constant, and T is the constant kelvin temperature. The Ea values extracted from each RLRS magnitude were practically similar and were 1.3–1.4 eV. This similar value of Ea implies that the migration rate of Cu ions remains unchanged although RLRS has different values. In order to predict the maximal value of RLRS whose tfailure can last for ten years at 85 ◦ C, we determined tfailure at different investigated RLRS by an extrapolation method from Fig. 3(a). As shown in Fig. 3(b), we extracted an optimal value of RLRS , which can guarantee ten years of retention. It can be observed
PARK et al.: INVESTIGATION OF STATE STABILITY
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Fig. 4. Acceleration test at the estimated 9-kΩ filament. The results satisfy the predicted results extrapolated from the Arrhenius plot.
that there exists linear dependence between 1/RLRS and tfailure with a slope of one tfailure ∝
1 . RLRS
Therefore, these results support our hypothesis that the reduction in the density of Cu ions that controls the magnitude of RLRS could be the main reason for the degradation of retention properties. To confirm our prediction that 9-kΩ RLRS could guarantee ten-year retention at 85 ◦ C, we performed an acceleration test at the estimated 9-kΩ RLRS , as shown in Fig. 4, which satisfies the predicted results determined previously from the Arrhenius plots. IV. C ONCLUSION By controlling different LRS in memory cells having a Pt/Cu : MoOx /GdOx /Pt structure, we have investigated the degradation in retention time by accelerating tests. The reduction in the Cu element that contributes to the magnitude of RLRS leads to the LRS degradation. We obtained an activation energy Ea of 1.3–1.4 eV that is independent of the different RLRS . From the Arrhenius plots, we have predicted the maximal and optimal RLRS that should be set at the LRS for guaranteeing a retention time of over ten years at 85 ◦ C. Thus, the investigation and analysis carried out in this enable the limit for multilevel memory applications to be defined.
[1] S. H. Jo, K.-H. Kim, and Wei Lu, “Programmable resistance switching in nanoscale two-terminal devices,” Nano Lett., vol. 9, no. 1, pp. 496–500, Jan. 2009. [2] Y. Sato, K. Tsunoda, K. Kinoshita, H. Noshiro, M. Aoki, and Y. Sugiyama, “ Sub-100 μA reset current of nickel oxide resistive memory through control of filamentary conductance by current limit of MOSFET,” IEEE Trans. Electron Devices, vol. 55, no. 5, pp. 1185–1190, May 2008. [3] H. Shima, F. Takano, H. Muramatsu, H. Akinaga, Y. Tamai, I. H. Inque, and H. Takagi, “Voltage polarity dependent low-power and high-speed resistance switching in CoO resistance random access memory with Ta electrode,” Appl. Phys. Lett., vol. 93, no. 11, p. 113504, Sep. 2003. [4] H. Sim, H. Choi, D. Lee, M. Chang, D. Choi, Y. Son, E.-H. Lee, W. Kin, Y. Park, I.-K. Yoo, and H. Hwang, “Excellent resistance switching characteristics of Pt/SrTiO3 Schottky junction for multi-bit nonvolatile memory application,” in IEDM Tech. Dig., 2005, pp. 777–780. [5] M. Liu, Z. Abid, W. Wang, X. He, Q. Liu, and W. Guan, “Multilevel resistive switching with ionic and metallic filament,” Appl. Phys. Lett., vol. 94, no. 23, p. 233106, Jun. 2009. [6] R. Symanczyk, R. Bruchhaus, R. Gittrich, and M. Kund, “Investigation of the reliability behavior of conductive-bridge memory cells,” IEEE Electron Device Lett., vol. 30, no. 8, pp. 876–878, Aug. 2009. [7] D. Kamalanathan, U. Russo, D. Ielmini, and M. N. Kozicki, “Voltagedriven ON–OFF transition and tradeoff with program and erase current in programmable metallization cell (PMC) memory,” IEEE Electron Device Lett., vol. 30, no. 5, pp. 553–555, May 2009. [8] N. Banno, T. Sakamoto, S. Fujieda, and M. Aono, “ON-state reliability of solid-electrolyte switch,” in Proc. IEEE 46th Annu. Int. Rel. Phys. Symp., 2008, pp. 707–708. [9] J. Yoon, H. Choi, D. Lee, J.-B. Park, J. Lee, D.-J. Seong, Y. Ju, M. Chang, S. Jung, and H. Hwang, “Excellent switching uniformity of Cu-doped MoOx /GdOx bilayer for nonvolatile memory applications,” IEEE Electron Device Lett., vol. 30, no. 5, pp. 457–459, May 2009. [10] J. Yoon, J. Lee, H. Choi, J. Park, D.-J. Seong, W. Lee, C. Cho, S. Kim, and H. Hwang, “Analysis of copper ion filaments and retention of duallayered devices for resistance random access memory applications,” Microelectron. Eng., vol. 86, no. 7–9, pp. 1929–1932, Mar. 2009. [11] D. Ielmini, F. Nardi, A. Vigani, E. Cianci, and S. Spiga, “Read-disturb limited reliability of multilevel NiO-based resistive switching memory,” in Proc. IEEE SISC, Arlington, VA, 2009. [12] D. Lee, D.-J. Seong, H. J. Choi, I. Jo, R. Dong, W. Xiang, S. Oh, M. Pyun, S.-o. Seo, S. Heo, M. Jo, D.-K. Hwang, H. K. Park, M. Chang, M. Hasan, and H. Hwang, “Excellent uniformity and reproducible resistance switching of doped binary metal oxides for non-volatile resistance memory application,” in IEDM Tech. Dig., 2006, pp. 797–800. [13] H. B. Lv, M. Yin, X. F. Fu, Y. L. Song, L. Tang, P. Zhou, C. H. Zhao, T. A. Tang, B. A. Chen, and Y. Y. Lin, “Resistive memory switching of Cux O films for a nonvolatile memory application,” IEEE Electron Device Lett., vol. 29, no. 4, pp. 309–311, Apr. 2008. [14] A. Pirovano, A. Redaelli, F. Pellizzer, F. Ottogalli, M. Tosi, D. Ielmini, A. L. Lacaita, and R. Bez, “Reliability study of phase-change nonvolatile memories,” IEEE Trans. Device Mater. Rel., vol. 4, no. 3, pp. 1185–1190, May 2008. [15] U. Russo, D. Ielmini, C. Cagli, and L. Lacaita, “Filament conduction and reset mechanism in NiO-based resistive-switching memory (RRAM) devices,” IEEE Trans. Electron Devices, vol. 56, no. 2, pp. 186–192, Feb. 2009.
