Investigation on the clamping voltage self-balancing of the ... - Ivo Barbi

46 downloads 324 Views 528KB Size Report
Phone: +41- 1-632-6973 Fax: +41- 1-632- 1212 ... switches S2/D, and S3/D3 are blocked by the clamping diodes ... the second switching cell (cell 2: S2/S3).
Investigation on the Clamping Voltage Self-Balancing of the Three-Level Capacitor Clamping Inverter Xiaoming Yuan, Herbert Stemmler and Ivo Barb? Power Electronics and Electrometrology Laboratory Swiss Federal Institute of Technology Zurich ETH-Zentrum / ETL, CH-8092 Zurich, Switzerland e-mail: yuan(stemmler)@lem.ee.ethz.ch Phone: +41- 1-632-6973 Fax: +41- 1-632-1212

#Power Electronics Institute Federal University of Santa Catarina P. 0. Box: 5119,88040-970, Florianopolis-SC, Brazil e-mail: ivo @ inep.ufsc.br Phone: +55-48-33 1-9204 Fax: +55-48-234-5422

Abstract -- This paper deals with the self-balancing quality of the clamping voltage in the three-level capacitor clamping inverter due to the spontaneous clamping capacitor current control loop in the circuit. Self-balancing quality of the three-level capacitor clamping inverter under sub-harmonic PWM modulation is analyzed in details. Self-balancing mechanism in the multilevel capacitor clamping inverter (M>3) under sub-harmonic PWM modulation is also discussed. Test results regarding the self-balancing quality from a half-bridge three-level capacitor clamping inverter prototype under sub-harmonic PWM modulation is given in the end.

I. INTRODUCTION The recent decade has seen increasing application in industry [ 11 of the Neutral-Point-Clamped (NPC) inverter [2], as shown in Fig. 1, mainly because of the possibility for high voltage operation at the DC link without the problematic device series connection, as well as the improved spectrum and reduced du/dt at the output. However, the NPC inverter has the following drawbacks: 1) It requires two extra clamping diodes (Dcl/Dc~)with identical performance requirements as the fieewheeling diodes (DI-D4) for each half bridge, adding to the cost and complexity of the overall system [3]. 2) Unless two auxiliary switches (S1’/S2’) are added as shown in Fig.1, the clamping paths for the two inner switches S2/D, and S3/D3 are blocked by the clamping diodes DC1and Dc2 respectively. Depending on the neutral bus parasitic inductivity, the inner two switches may see higher blocking voltage than the outer two switches (S1/DI and s a 4 )[41. 3) The two DC link capacitors (C, and Cz) must be large on the one hand to deal with transience from the utility side or the load side, and on the other hand to accommodate the third order current flowing in the neutral line in a three phase NPC inverter system. 4)Unlike the two-level inverter where the redundancy in switching state (l,l,leO,O,O) can be dedicated to DC link voltage utilization [5], in an NPC inverter, such redundancy (l,l,OeO,O,-1, for example) must be attributed to DC link neutral potential stabilization, DC link voltage utilization is not optimized as a result [6] [7]. Instead of two clamping diodes, the three-level capacitor clamping inverter [8] [9], as shown in Fig. 2, utilizes a high frequency small capacitor ( C d for clamping of the two inner devices of a leg. When the clamping capacitor voltage (Vc,,,) is stable at Vd,/2, all the four devices will be tightly clamped 0-7803-5421-4/99/$10.00 0 1999 IEEE

as the two-level case, making the capacitor clamping inverter an interesting alternative for three-level conversion. Besides, like the two-level inverter, the redundancy in switching state in a three-level capacitor clamping inverter (l,l,OeO,O,-I, for example) can be dedicated to DC link voltage utilization, while the controlling of the clamping voltage when necessary can be left to the redundancy in switch combination for the zero switching state of each leg (S ,/s+SZ/S4). The drawbacks with the NPC inverter and the benefits with the three-level capacitor clamping inverter remain true as the number of level increases. For conversion above threelevel, the use of the capacitor clamping inverter becomes more rewarding.

1059

Fig. 1. Structure of a leg in the NPC inverter.

I

I

A

I

Fig. 2. Structure of a leg in the three-level capacitor clamping inverter

11. CLAMPING VOLTAGE SELF-BALANCING IN THREE-LEVEL CAPACITOR CLAMPING INVERTER UNDER SUB-HARMONIC P w M MODULATION A . Sub-Harmonic PWM Modulation f o r the Three-Level Capacitor Clamping Inverter A three-level capacitor clamping inverter leg consists of two switching cells. To maintain steady state stability of the clamping voltage, the instantaneous duty cycle of the control signal for the first switching cell (cell 1: SJSI ) must be equal to the instantaneous duty cycle of the control signal for the second switching cell (cell 2: S2/S3). On the other hand, to maintain optimum output voltage spectrum, the two control signals for the two switching cells must be phaseshifted by IC to each other [ IO]. Such control sequence can be created by the conventional sub-harmonic PWM modulation, as shown in Fig. 3.

the clamping capacitor will be charged or discharged leading to load voltage variation, load current variation and in turn DC component variation in the clamping capacitor current, discharging or charging the clamping capacitor until the DC component in the clamping capacitor current returns to zero. As a result of the clamping voltage variation (V,,3) may no longer be first order. Each clamping voltage may see a damped resonance process before reaching its steady state.

switching frequency representing the switching frequency component in the switching functions of the (k-l)-th and k-th is load impedance amplitude and switching cells, zm&qkdfC angle at the switching frequency, and &&si

a vector

rotating at the switching frequency representing the switching frequency component in the load current variation. From (17) and (18), the k-th clamping capacitor voltage will be charged when the two vectors ~ q ~ and- ~ , are ~

~i~~ ~ ~

phase shifted within 90 degrees, will be discharged when phase shifted beyond 90 degrees, and will be kept when phase shifted at 90 degrees. The vector again is determined by the vector

Sqrl)r,c together

with the initial

state of the clamping voltages as well as the load properties. As long as the load is not pure-reactive, for any initial state in the clamping voltages, the following will happen: Group A: some overcharged capacitors are discharged Group B: some overcharged capacitors are charged; Group C: some undercharged capacitors are charged; Group D: some undercharged capacitors are discharged.

(a) formation of the switching frequency vectors SW 113 and

(b) formation of the load current variation vector A;

W?,
3), the current control loop for an individual clamping capacitor is coupled with the remaining control loops for the remaining clamping capacitors by the load current. Consequently, when the clamping voltages are still self-balancing under nonpure-reactive load with sub-harmonic PWM modulation, the response of an individual clamping voltage to perturbation(s) on any clamping voltage(s) may appear to be a damped resonance rather than simply one order like the three-level case. 3) Due to the dependency of the self-balancing quality on the modulation pattern as well as the load property, due also to the steady state drift of each clamping voltage from its nominal value in an asymmetrical circuit as a result of the self-balancing quality, the need for an external control loop for each clamping voltage may arise fiom time to time. The coordination of such external loop with the self-balancing quality will be an interesting challenge for the future.

,....I

:

.

?

.

.j

[I] H. Stemmler, “High-Power Industrial Drives”, Proceedings of the IEEE, Vol. 82, NO. 8, pp. 1266-1286, August 1994. [2] A. Nabae, I. Takahashi, and A. Akagi, “A New Neutral-Point Clamped PWM Inverter”, IEEE Trans. Ind. App., Vol. 19, No. 5, SepJOct. 1981, pp. 518-523. [3] A. Steimel, “Electric Railway Traction in Europe”, IEEE Industry Applications Magazine, Nov./Dec. 1996, pp. 7-1 7. [4] Xiaoming Yuan and Ivo Barbi, “A New Diode Clamping Multilevel Inverter”, Record of IEEE APEC, 1999, pp. 495-501. [5] H. W. Van Der Broeck, H. W. Skudely and G. V. Stanke, ‘‘ Analysis and Realization of A Pulsewidth Modulator Based on Voltage Space Vector”, IEEE Trans. on Ind. Appl., Vol. 24, No. I, Jan./Feb. 1988, pp. 142-150. [6] Y. Tadros, S. Salama, and R. Hof, “Three Level IGBT Inverter”, Record of IEEE PESC, 1992, pp. 46-52. [7] J. Steinke, “Switching Frequency Optimal PWM Control of a Three Level Inverter”, IEEE Trans. on Power Electronics”, Vol. 7, No. 3, July 1992, pp. 481-496. [8] T. Maruyama and M. Kumano, “New PWM Control for A Three-Level Inverter”, Record of IPEC, 1990, pp. 870-877. [9] T. Meynard and H. Foch, “Multi-Level Conversion: High Voltage Choppers and Voltage Source Inverters”, Record of IEEE PESC, 1992, pp. 397403. [IO] P. Cadre. T. Meynard and J. P. Lavieville, “4000V-300A Eight-Level IGBT Inverter Leg”, Record of EPE Conference, 1995, pp. 1106-1 1 11. [Ill C. Hochgraf, R. Lasseter, D. Divan and T. Lipo, “Comparison of Multilevel Inverters for Static Var Compensation”, Record of IEEE IAS, 1994, pp. 921 -928.

..........

........,.. ..,.,............ . ........, .......,..._,..

, . ............j........... i:.............. , .................

:

.....

.

.......

5 0 V lDiv 500mS/Div

(d) DC supply switched on, load resistance %=7 5.Q Fig. 8. Clamping voltage self-balancing with different load resistance when the DC supply is switched off and on.

1064