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Isolated Boost Converters Yungtaek Jang and Milan M. Jovanović Power Electronics Laboratory Delta Products Corporation P.O. Box 12173, 5101 Davis Drive Research Triangle Park, NC 27709 inductance is achieved by clamping the voltages of the primary switches and rectifiers to the voltage of the primaryside energy-storage capacitor and clamping the voltage across the secondary-side rectifiers to the output filter capacitor.
Abstract — Two implementations of the isolated boost converter that exhibit no parasitic voltage ringing across all semiconductor devices on the primary and secondary sides of the transformer are introduced. Ringing-free operation is achieved by clamping the voltages of the primary switches and rectifiers to the voltage of the primary-side energy-storage capacitor and clamping the voltage across the secondary-side rectifiers to the output filter capacitor. The performance of the proposed topology was verified on a dual ac-input, 900-W experimental prototype operating at 100 kHz.
I. INTRODUCTION The conventional non-isolated boost converter topology has been extensively used in various ac/dc and dc/dc applications. In fact, the front end of today’s ac/dc power supplies with power-factor correction (PFC) is almost exclusively implemented with the boost topology. The boost topology is also used in numerous battery-powered applications to generate a high output voltage from a relatively low battery voltage. However in some applications, it may be advantageous to use a boost converter with a galvanically isolated input and output. For example, fault tolerant power systems that use a dual ac-input architecture can be implemented with isolated boost converters, , . In fact, the isolated-boost-converter implementation offers a reduced number of components compared to the implementations with non-isolated boost converters in applications which require dual ac input . Also, in applications where a power supply with both ac and dc inputs is required, the isolated boost converter can be applied to provide safety-required isolation between the inputs. So far, a number of boost topologies utilizing an isolation transformer have been proposed, -. Generally, these circuits exhibit increased voltage stresses on the switches and/or diodes due to the parasitic ringing of the leakage inductance of the transformer with the output capacitances of the switching devices. To control the parasitic ringing voltage, these converters rely on various snubbers, which have detrimental effect on their efficiency and also limit their switching frequency. In this paper, a two-switch implementation and a threeswitch implementation of an isolated boost converter that exhibits voltage waveforms without parasitic voltage ringing across all semiconductor devices on the primary and secondary sides of the transformer are introduced. Ringingfree operation in the presence of the transformer’s leakage
0-7803-9547-6/06/$20.00 ©2006 IEEE.
II. ISOLATED BOOST CONVERTERS The circuit diagram of the proposed two-switch isolated boost converter is shown in Fig. 1. The primary side consists of boost inductor LB, switches S1 and S2, primary-side energy-storage capacitor CB, rectifiers D1 through D4, and the primary winding of transformer TR. The output side of the circuit consists of the secondary winding of transformer TR connected to the full-bridge rectifier implemented with rectifiers DR1 through DR4, and capacitive filter CF connected across load RL. To facilitate the explanation of the circuit operation, Fig. 2 shows a simplified circuit diagram of the circuit in Fig. 1. In the simplified circuit, energy-storage capacitor CB and filter capacitor CF are modeled by voltage sources VB and VO, respectively, by assuming that the values of capacitors CB and CF are large enough so that the voltage ripple across the capacitors are small compared to their dc voltages. In addition, isolation transformer TR is modeled by leakage inductance LLK, magnetizing inductance LM, and an ideal transformer with turns ratio n=NP/NS, where NP is the number of turns of the primary winding and NS is the number of turns of the secondary winding. Finally, in this analysis it is also assumed that all semiconductor components represent zero impedances in the on state and infinite impedances in the off state. To further facilitate the analysis of operation, Fig. 3 shows the topological stages of the circuit in Fig. 1 during a switching cycle, whereas Fig. 4 shows its key waveforms assuming that the inductance of boost inductor LB is large enough to keep input current iIN continuously flowing. The
D R3 CF
NS D R2
Fig. 1. Proposed two-switch implementation of isolated boost converter.
iPRIM and secondary current iSEC start to flow because voltage source VB appears in parallel with the primary of the transformer when switches S1 and S2 are closed and diode D3 is forward biased, i.e., VPRIM=VB. Since during the [T1 – T2] interval secondary voltage VSEC is positive, secondary current iSEC is carried by rectifiers DR1 and DR4. From Fig. 3(b), secondary current iSEC during the [T1 – T2] interval can be calculated as i SEC = n ⋅ [i PRIM − i M ] , (2) where primary current iPRIM and magnetizing current iM are
LB i D3
D1 i D1
V D1 V S2
+ V S1
n:1 i SEC
L LK LM iM
1 i n SEC
+ V SEC D R2
Fig. 2. Simplified circuit diagram of proposed converter with reference directions of voltage and currents.
i PRIM =
reference directions of currents and voltages plotted in Fig. 4 are shown in Fig. 2. As can be seen from the timing diagram of the control signals for switches S1 and S2 shown in Fig. 4, switches S1 and S2 of the proposed circuit are simultaneously turned on and off. The on time of the switches defines duty cycle D of the converter, as indicated in Fig. 4. During the time interval when switches S1 and S2 are open, input current iIN flows through diodes D1 and D2, as shown in Fig. 3(a). Assuming that at t=T0, transformer TR is completely reset, i.e., magnetizing current iM(t=T0)=0, no other current is flowing in the circuit during the time interval from t=T0 until switches S1 and S2 are turned on at t=T1. Since voltage VB is always greater than input voltage VIN (since it is the boost topology), input current iIN is decreasing with a constant slope during the [T0 – T1] interval, as shown in Fig. 4. As a result, diode currents iD1 and iD2 are also decreasing, i.e., di D1 di D 2 di IN VIN − VB = = =