Isolated DC-DC Converter for Bidirectional Power

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Mar 2, 2017 - Abstract: In this paper, a novel isolated bidirectional DC-DC converter is proposed, which is able to accomplish high step-up/down voltage ...

energies Article

Isolated DC-DC Converter for Bidirectional Power Flow Controlling with Soft-Switching Feature and High Step-Up/Down Voltage Conversion Chih-Lung Shen 1, *, You-Sheng Shen 1 and Cheng-Tao Tsai 2 1 2

*

Department of Electronic Engineering, National Kaohsiung First University of Science and Technology, Kaohsiung 82445, Taiwan; [email protected] Department of Electrical Engineering, National Chin-Yi University of Technology, Taichung 41170, Taiwan; [email protected] Correspondence: [email protected]; Tel.: +886-7-601-1000; Fax: +886-7-601-1386

Academic Editor: Jayanta Deb Mondol Received: 29 December 2016; Accepted: 27 February 2017; Published: 2 March 2017

Abstract: In this paper, a novel isolated bidirectional DC-DC converter is proposed, which is able to accomplish high step-up/down voltage conversion. Therefore, it is suitable for hybrid electric vehicle, fuel cell vehicle, energy backup system, and grid-system applications. The proposed converter incorporates a coupled inductor to behave forward-and-flyback energy conversion for high voltage ratio and provide galvanic isolation. The energy stored in the leakage inductor of the coupled inductor can be recycled without the use of additional snubber mechanism or clamped circuit. No matter in step-up or step-down mode, all power switches can operate with soft switching. Moreover, there is a inherit feature that metal–oxide–semiconductor field-effect transistors (MOSFETs) with smaller on-state resistance can be adopted because of lower voltage endurance at primary side. Operation principle, voltage ratio derivation, and inductor design are thoroughly described in this paper. In addition, a 1-kW prototype is implemented to validate the feasibility and correctness of the converter. Experimental results indicate that the peak efficiencies in step-up and step-down modes can be up to 95.4% and 93.6%, respectively. Keywords: bidirectional DC-DC converter; high voltage conversion ratio; galvanic isolation; soft-switching feature

1. Introduction In order to reduce carbon emission and mitigate global warming, green energies, such as photovoltaic (PV) panel, fuel cells, and wind turbine, attract a great deal of interest and have a high rate of growth in installed capacity. A complete configuration of distributed generation system (DGS), as shown in Figure 1, not only includes green-energy sources but also combines an energy storage system for power conditioning to use electricity optimally. For grid connection, a DC-bus voltage up to around 400 V is required, which is much higher than a battery voltage. Therefore, a bidirectional DC-DC converter (BDC) with high voltage ratio to charge/discharge battery is mandatory in the DGS. Conventional high step-up converters used in PV panel and fuel cells can boost a low voltage to a higher level to serve as an interface between the distributed generator and the DC bus [1–3]. Nevertheless, they only control power flow in unique direction. Bidirectional power flow control is necessary for battery system. A solution is to adopt two high-voltage-ratio converters. One is high-step-up converter for battery discharging and the other is high-step-down converter for charging, but this approach increases cost significantly. Therefore, BDC is the current design trend, which is

Energies 2017, 10, 296; doi:10.3390/en10030296

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which capable of governing in either power flow by direction a single converter. can capableisof governing energy inenergy either power flow direction a singlebyconverter. BDCs can BDCs be simply be simplyas classified as non-isolated typeisolated [4–6] and isolated classified non-isolated type [4–6] and type [7,8]. type [7,8]. VB

iB

Signals

DC-Bus

Bidirectional DC-DC Converter

Battery Bank vpv ipv

High Step-up DC/DC Converter PV Module

VLoad

DC Load

iLoad

DC/AC Inverter

vpv ipv VB iB VLoad iLoad Signals

Utility

AC Load

Controller

Figure 1. Configuration of distributed generation system.

Increasing switching frequency of a power converter can reduce the size of magnetic and Increasing switching frequency of a power converter can reduce the size of magnetic and capacitive elements and thus has the benefit of achieving high power density. However, the higher capacitive elements and thus has the benefit of achieving high power density. However, the higher switch frequency is, the lower conversion efficiency will be. In order to eliminate switching loss, switch frequency is, the lower conversion efficiency will be. In order to eliminate switching loss, employing resonant unit with auxiliary switches for soft-switching achievement is a common employing resonant unit with auxiliary switches for soft-switching achievement is a common approach [9–11]. In literature [12], the authors develop a dual-bridge converter to fulfill bidirectional approach [9–11]. In literature [12], the authors develop a dual-bridge converter to fulfill bidirectional power flow controlling along with zero voltage switching (ZVS) at main switch, in which even power flow controlling along with zero voltage switching (ZVS) at main switch, in which even resonant resonant tank is utilized but the use of additional auxiliary switch can be avoided. Nevertheless, a tank is utilized but the use of additional auxiliary switch can be avoided. Nevertheless, a great many great many switches are needed and its voltage ratio is incapable of high step-up/down applications. switches are needed and its voltage ratio is incapable of high step-up/down applications. The open H-bridge converter can function as a non-isolated BDC [13]. Even though this The open H-bridge converter can function as a non-isolated BDC [13]. Even though this converter converter can achieve ZVS feature and possesses simple structure, its voltage gain is less than 2 at can achieve ZVS feature and possesses simple structure, its voltage gain is less than 2 at the duty the duty ratio of 0.5. For higher voltage ratio, heavy switch duty cycle is the only solution to this ratio of 0.5. For higher voltage ratio, heavy switch duty cycle is the only solution to this problem, problem, but this approach will degrade converter efficiency. To avoid excessive duty cycle but this approach will degrade converter efficiency. To avoid excessive duty cycle operation, switched operation, switched capacitor technology will be an alternative for high voltage-gain conversion [14]. capacitor technology will be an alternative for high voltage-gain conversion [14]. However, current However, current spike that occurs at the switching transients confines its applications and spike that occurs at the switching transients confines its applications and accompanies electromagnetic accompanies electromagnetic interference (EMI) problem, especially in high power rating. interference (EMI) problem, especially in high power rating. Incorporating switched capacitor along Incorporating switched capacitor along with coupled inductor into a power converter is a key to with coupled inductor into a power converter is a key to suppressing inrush current and obtaining suppressing inrush current and obtaining enough voltage conversion ratio [15–18]. Since the enough voltage conversion ratio [15–18]. Since the coupled inductor can also feature electrical isolation, coupled inductor can also feature electrical isolation, a BDC including coupled inductor is the major a BDC including coupled inductor is the major development. However, the energy dissipation caused development. However, the energy dissipation caused from leakage inductor will degrade converter from leakage inductor will degrade converter efficiency [19,20]. That is, clamped circuit or snubber efficiency [19,20]. That is, clamped circuit or snubber mechanism for leakage energy harvesting is mechanism for leakage energy harvesting is imperative. Isolated BDCs based on H-bridge topology imperative. Isolated BDCs based on H-bridge topology have been proposed in the literature [21,22], have been proposed in the literature [21,22], which can achieve ZVS feature inherently, avoiding which can achieve ZVS feature inherently, avoiding additional device usage. Nevertheless, low additional device usage. Nevertheless, low voltage ratio and more power switches required become voltage ratio and more power switches required become their disadvantages. In [23], another their disadvantages. In [23], another isolated BDC which accomplishes leakage-energy recycling and isolated BDC which accomplishes leakage-energy recycling and can obtain high voltage-ratio can obtain high voltage-ratio conversion is presented. Nevertheless, some limitations still exist, such conversion is presented. Nevertheless, some limitations still exist, such as ZVS only occurs at as ZVS only occurs at high-voltage side and duty ratio has to be greater than 0.5. high-voltage side and duty ratio has to be greater than 0.5. In this paper, a novel BDC is proposed, which has the advantages of galvanic isolation, high In this paper, a novel BDC is proposed, which has the advantages of galvanic isolation, high voltage conversion ratio, soft-switching feature at all power switches, high efficiency, being suitable voltage conversion ratio, soft-switching feature at all power switches, high efficiency, being suitable for high power applications, and low component count. Figure 2 shows its configuration of the power for high power applications, and low component count. Figure 2 shows its configuration of the stage. The symbols in the circuit are summarized in the followings. VL and VH denote the terminal power stage. The symbols in the circuit are summarized in the followings. VL and VH denote the voltages at low-voltage side and high-voltage side, respectively; L1 is a choke inductor; S1 , S2 , S3 , S4 , S5 , terminal voltages at low-voltage side and high-voltage side, respectively; L1 is a choke inductor; S1, and S6 are active switches, while DS1 –DS6 and CS1 –CS6 express their related anti-parallel body diodes S2, S3, S4, S5, and S6 are active switches, while DS1–DS6 and CS1–CS6 express their related anti-parallel and parasitic capacitors; the magnetically-coupled device has winding N1 , magnetizing inductor Lm1 , body diodes and parasitic capacitors; the magnetically-coupled device has winding N1, magnetizing inductor Lm1, and leakage inductor Lk1 at low-voltage side, meanwhile N2, Lm2, and Lk2, respectively, at

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Energies 2017, 10, 296 and leakage inductor L

3 of 23 at low-voltage side, meanwhile N2 , Lm2 , and Lk2 , respectively, at high-voltage side; Cb1 and Cb2 are low-voltage capacitors; and Co1 and Co2 are high-voltage capacitors. The conversion high-voltage side; Cb1 and Cb2 are low-voltage capacitors; and Co1 and Co2 are high-voltage capacitors. efficiency of proposed BDC can be improved because of the following reasons: The conversion efficiency of proposed BDC can be improved because of the following reasons: k1

(1) No No matter matter in in buck buck or or boost boost mode, and L k2,, can can be be (1) mode, the the energy energy stored stored in in leakage leakage inductors, inductors, LLk1 k1 and Lk2 recycled without any snubber mechanism or clamped circuit. recycled without any snubber mechanism or clamped circuit. (2) All All active active semiconductor bebe switched with ZVSZVS or zero current switching (ZCS) (2) semiconductorcomponents componentscan can switched with or zero current switching to eliminate switching losses. (ZCS) to eliminate switching losses. Switches SS11–S –S4 4endure endureaalow low voltage voltage stress stress so that semiconductor (3) Switches semiconductor device device with with aasmaller smallerRRds(on) ds(on) canbe be chosen chosen to to reduce reduce conduction conduction losses. losses. can High-Voltage Side

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Figure 2. 2. Schematic Schematic of of the the proposed proposed bidirectional bidirectional converter. converter. Figure

described in Section 1, this1,paper is organized as follows. operation Following the theintroduction introduction described in Section this paper is organized as The follows. The principle ofprinciple the proposed converter is explained in Section 2. Section 3 presents steady-state analysis. operation of the proposed converter is explained in Section 2. the Section 3 presents the steady-state Experimental measuredare from a 1-kWand prototype illustrated and Experimentalanalysis. results measured from aresults 1-kW prototype illustrated discussedare in Section 4, while discussed 4, while conclusioninisSection summarized in conclusion Section 5. is summarized in Section 5. 2. Operation Operation Principle Principle of of the the Proposed Proposed Converter Converter 2. As shown shown in in Figure Figure 2, 2, the the direction direction of of energy energy flow flow can can be be handled by controlling controlling the the active active As handled by switches so so that that the the converter In step-up step-up switches converter can can operate operate in in either either step-up step-up mode mode or or step-down step-down mode. mode. In mode, main main switches switches S and SS44 are are in in switching switching pattern pattern while while SS55 and and SS66 are are in in charge charge of of mode, S11,, SS22,, SS33, , and rectifying. At this mode, S and S operate complementarily and so do both switches S and S 1 2 rectifying. At this mode, S1 and S2 operate complementarily and so do both switches S3 and3 S4. The4 . The voltage the ratio duty of ratio of S1 . respect With respect to step-down H is determined voltage gain gain of VLoftoVVLHto is V determined by theby duty S1. With to step-down mode,mode, main main switches S , S , S , and S will be in switching pattern and the rest of main switches serve as 4 S56 will be6 in switching pattern and the rest of main switches serve as rectifier. switches S2, S4, S25, and rectifier. In addition, S , S , and S are turned on and off simultaneously and complementary to S 4 turned 5 on and off simultaneously and complementary to S6. The duty 6. In addition, S2, S4, and 2S5 are The duty of S6 dominates voltage gain step-down mode. the To operation describe the H to VL inmode. ratio of S6 ratio dominates the voltagethe gain of VH to VL of in V step-down To describe of operation of the converter, some assumptions are made as follows: the converter, some assumptions are made as follows:

(1) of C Cb1 b1,, C (1) In In Figure Figure 2, 2, capacitances capacitances of Cb2b2, ,CCo1o1, ,and andCCo2o2are arelarge largeenough enoughso sothat thatall allthe the voltages voltages across across them themcan can be be regarded regarded as as constant constant in in aa switching switching cycle. cycle. (2) but thethe internal resistance is (2) Parasitic Parasiticcapacitor capacitorand andbody bodydiode diodeofofeach eachswitch switchare areconsidered, considered, but internal resistance neglected. is neglected. (3) The (3) Theleakage leakage inductance inductance of of the the coupled coupled inductor inductor is is much much less less than than magnetizing magnetizing inductance. inductance. (4) All the magnetic components are designed in continuous conduction mode (CCM). (4) All the magnetic components are designed in continuous conduction mode (CCM). (5) The turns ratio of secondary to primary of the coupled inductor, N2/N1, is defined as n. (5) The turns ratio of secondary to primary of the coupled inductor, N2 /N1 , is defined as n.

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2.1. Step-Up Mode The converter operation in step-up mode is divided into nine main stages over one switching cycle, which are discussed stage by stage below. The equivalents of the nine stages are depicted in Figure 3, while Figure 4 illustrates the corresponding conceptual waveforms. Stage 1 [t0 , t1 ]: In this stage, referring to Figure 3a, all the switches are in off state. The energy stored in the parasitic capacitor CS3 is drawn out but capacitor Cb1 is charged, as referred to the red dashed line in Figure 3a. Meanwhile, energy of L0 m1 is forwarded to capacitor Co2 and the output VH , where L0 m1 stands for the total amount of magnetizing inductance seen looking into the primary (at low-voltage side) of the coupled inductor. After the voltage across CS3 drops to zero, the body diode DS3 conducts to continue the currents flowing through L1 and Lk1 thus to create ZVS turn-on condition for S3 . Stage 2 [t1 , t2 ]: This stage begins at the moment the switches S1 and S3 are turned on. The S3 is turned on with ZVS. During this time interval, S2 , S4 , S5 , and S6 are still in off-state. The voltage of the parasitic capacitor CS1 drops. After the voltage vds1 is less than input voltage VL , inductor L1 will absorb energy from VL and the current iL1 increases, as referred to the blue dashed line in Figure 3b. In stage 2, the energy of Lk1 is continuously releasing to Cb1 . The equivalent circuit of this stage is illustrated in Figure 3b. When the current iLk1 falls to zero, this mode ends. Stage 3 [t2 , t3 ]: Figure 3c depicts the equivalent circuit of this stage, in which all the switch have the same statuses as in Stage 2. Inductor L1 continuously absorbs the energy from VL . Capacitor Cb1 transmits energy to Lk1 , L0 m1 and the secondary (at high-voltage side) of the coupled inductor, of which current path is indicated by the red dashed line in Figure 3c. The currents iLk1 and iLm1 increase. In the high-voltage side, Co1 is charged via the loop of N2 -DS6 -Co1 -Lk2 but Co2 discharges via the loop of Lk2 -N2 -DS6 -VH -Co2 . This mode ends when S3 is turned off. Stage 4 [t3 , t4 ]: This stage begins at time t = t3 , and the equivalent circuit is illustrated in Figure 3d. During this time interval, all the switches are in off state except S1 . Input VL and capacitor Cb1 charge inductor L1 and capacitor Cb2 , respectively. In addition, Cb1 forwards energy to high-voltage side via the coupled inductor to charge Co1 . The CS4 releases energy. That is, vds4 decreases. The body diode of S4 will be forward biased after vds4 drops to zero, which provides ZVS condition for S4 . The associated current path is referred to the red dashed line in Figure 3d. The leakage energy in Lk2 is recycling to Co1 over the interval of Stage 4. Stage 5 [t4 , t5 ]: When S4 is turned on, the operation of the converter enters into Stage 5. As shown in Figure 3e, in this stage switches S1 and S4 are closed, whereas S2 , S3 , S5 , and S6 are open. The voltage polarity of Lk1 is reversed and the current iLk1 begins decreasing. Capacitor Cb2 is charged by Lk1 and Cb1 and the current flowing through S4 is decreased, as referred to the red dashed line in Figure 3e. The energy in Lk2 is kept on recycling to Co1 , which is the same as in Stage 4. At the moment that iLk2 equals zero, this stage ends and DS6 is reversely biased. Stage 6 [t5 , t6 ]: During the time interval of Stage 6, the switches S1 and S4 are still in on state and S2 , S3 , S5 , and S6 in off state. Figure 3f is the corresponding equivalent, in which Cb1 charges Lk1 , L0 m1 , and Cb2 , as referred to the red dashed line. The currents flowing through Lk1 and L0 m1 are identical and increase simultaneously. With respect to current iL1 , since the voltage across L1 is VL , the current iL1 continues linearly increasing. This stage continues until S1 is turned off. Stage 7 [t6 , t7 ]: Figure 3g depicts the equivalent circuit of Stage 7, in which all switches are open except S4 . There are two loops, VL -L1 -Cb1 -CS2 and Lk1 -L0 m1 -S4 -Cb2 -CS2 , to draw the energy stored in the parasitic capacitor of S2 . When the voltage across CS2 falls to zero, the body diode of S2 conducts and S2 can achieve ZVS, as referred to the both dashed lines in red and blue in Figure 3g. In the high-voltage side of the converter, the both in-series capacitors Co1 and Co2 supply power to output.

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Stage 8 [t7 , t8 ]: After the time t = t7 , switches S2 and S4 are in on state but S1 , S3 , S5 , and S6 are in off state. The equivalent circuit is illustrated in Figure 3h. As referred to the both red and purple dashed line in Figure 3h, capacitor Cb1 is charged by VL and L1 , while the Cb2 absorbs energy from L0 m1 and Lk1 . All the currents iL1 , iLk1 and iLm1 decrease. In addition, the energy stored in magnetizing inductor is 10, forwarded to the secondary of the coupled inductor to charge Co2 . This stage ends as Energies 2017, 296 5 ofthe 23 current iLk1 falls to zero. Stage 9 [t [t88,,tt9]: Duringthe thetime time interval Stage 9, the switches S2 and S4 still are still on state interval of of Stage 9, the switches S2 and S4 are in oninstate and 9 ]:During and , 5S, 3and , S5 , Sand off state. The equivalent circuit is illustrated in Figure 3i. Capacitor Cb1 is S1, SS 3,1S 6 in Soff The equivalent circuit is illustrated in Figure 3i. Capacitor Cb1 is still 6 instate. still charged VL L and L1 . Additionally, capacitor Cb2 pumps energy to inductor via switches charged by Vby L and 1. Additionally, capacitor Cb2 pumps energy to inductor Lk1 viaLk1 switches S4, as S the dashed red dashed in Figure The energy storedininthe themagnetizing magnetizing inductor inductor is referred to thetored line line in Figure 3i. 3i. The energy stored 4 , as referred transferred to the secondary secondary to to charge charge CCo2 o2 and power the output. output. In In this this stage, stage, inductor inductor currents currents iiL1 L1 and iLm1 decrease but but iLk1 and i increase. When switches S and S are turned off at = , this Lm1 decrease and i Lk2 increase. When switches S 2 and S 4 are turned off at t t 9 , this stage 2 4 9 Lk1 Lk2 ends. The operation in step-up mode over one switching cycle is completed. S6

S6

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(i) Figure 3. Equivalent circuit of proposed bidirectional converter in step-up mode: (a) Stage 1; (b) Figure 3. Equivalent circuit of proposed bidirectional converter in step-up mode: (a) Stage 1; (b) Stage 2; Stage 2; (c) Stage 3; (d) Stage 4; (e) Stage 5; (f) Stage 6; (g) Stage 7; (h) Stage 8; and (i) Stage 9. (c) Stage 3; (d) Stage 4; (e) Stage 5; (f) Stage 6; (g) Stage 7; (h) Stage 8; and (i) Stage 9.

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Ts

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Figure 4. 4. Key Key waveforms waveforms of of the the proposed proposed converter converter in in step-up step-up mode. mode. Figure

Step-Down Mode Mode 2.2. Step-Down and SS55are arecontrolled controlledat at high high switching switching pattern pattern and and complementary complementary In step-down mode, S22,, SS44,,and to SW66,, while while SW SW11and andSW SW33serve serveas asrectifiers. rectifiers.The Theconverter converteroperation operation over over one one switching switching cycle cycle in in to step-down mode mode can can be be divided divided into into 12 12 stages, stages, which which are are described describedstage stageby bystage stagein inthe thefollowing. following. step-down The related equivalents and corresponding waveforms are depicted depicted in in Figures Figures 55 and and 6, 6, respectively. respectively. Stage 11 [t[t00, ,t1t]: ReferringtotoFigure Figure 5a, the switches state. Since S5 has been turned Stage 5a, allall the switches areare in in offoff state. Since S5 has been turned off, 1 ]:Referring 0 off, voltage the voltage CS5 increases. Accordingly, the voltage across (the inductance looking the of Cof S5 increases. Accordingly, the voltage across L'm2 L (the seen seen looking into m2 inductance intohigh-voltage the high-voltage of the coupled inductor) andLk2 L,k2which , whichisisequal equal to vvCo2 decreases; the sideside of the coupled inductor) and Co2 − − vds5 ds5, , decreases; 0 In. energy stored in the parasitic parasitic capacitor capacitor of of SS66 releases releasesvia viathe theloop loopof ofCCS6S6 meanwhile the energy -C-C o1o1 -L-L k2-L′ m2. m2 k2 -L In low voltage side, body diodesofofS2Sand areforward forwardbiased biasedbecause becauseof of the the continuity continuity of iLk1 low voltage side, thethe body diodes Lk1.. 2 andS4S4are −VVL.L .Since SincevvCb1 is larger than V , the current i increases negatively, The voltage voltage across acrossLL11 equals equalsvvCb1 Cb1 − is larger than V L , the current i L1 increases negatively, L L1 Cb1 via the the coupled coupled as referred to the red dashed dashed line line in in Figure Figure 5a. 5a. During During this this stage, stage,CCo2 o2 will energize Cb2 b2 via -N11-D -DS4S4 -D . This mode ends at the moment v reaches the magnitude inductor and the loop Lk1 k1-N -C-C b2-D S2 . This mode ends at the moment v ds5 reaches the magnitude of b2 S2 ds5 of V . That is, S is completely turned off and its blocking voltage is clamped to V . VH. That is, S5 is 5completely turned off and its blocking voltage is clamped to VH. H H Stage 2 [t11,, tt22]:]: During Duringthis this time time interval, interval, all all the the switches switches still still stay stay in off state. The equivalent equivalent Stage 0 m2 and L k2 reverses reverses and the the circuit of this stage is illustrated illustrated in in Figure Figure5b. 5b. The The voltage voltagepolarity polarityacross acrossLL′ and m2 k2 0 +vvLk2 equalto tovvCo1 . Thatis,is,magnetizing magnetizinginductor inductor L′ L m2 andleakage leakage inductor inductor Lk2 release value of vvLm2 Lm2 + . That k2 release m2and Co1 Lk2isisequal and V VHHvia viabody bodydiode diode D DS6S6, ,asasindicated indicatedby bythe thepurple purpledashed dashed line line in in Figure Figure 5b. Since energy to Co1 o1 and voltage polarity of the coupled inductor has been changed, the body diode DS2 will be reversely

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voltage polarity of the coupled inductor has been changed, the body diode DS2 will be reversely biased and the parasitic capacitor CS1 releases energy to VL . In stage 2, the current flowing Lk1 almost equals that in L1 . Therefore, switch S2 is turned off at ZCS. When S6 is turned on with ZVS, the operation of the converter enters into next stage. Stage 3 [t2 , t3 ]: In this stage, switch S6 is closed. L0 m2 and Lk2 proceed with energy releasing toward Co1 and VH , and leakage energy in Lk1 is dumped to Cb2 at the same time. Accordingly, all the currents in them decrease. As referred to the blue dashed line in Figure 5c, the current of L1 draws out the stored energy in CS1 and then force the parasitic diode DS1 in forward bias. The L1 delivers energy to VL and its current decreases linearly. In stage 3, the current flowing through Lk2 is greater than that in L0 m2 but its magnitude drops much steeper. This stage continues until iLk1 drops to zero. Figure 5c shows the equivalent circuit of this stage. Stage 4 [t3 , t4 ]: This stage begins at time t = t3 , and the equivalent circuit is illustrated in Figure 5d. During this time interval, all switches are still in turn-off condition except S6 . Magnetizing inductor L0 m2 forwards energy to Co1 and Cb1 via switch S6 and the ideal transformer, respectively. The current direction of Lk1 changes, which results in energy releasing of CS3 and the charging of CS4 . Associated current path is shown as the red dashed line in Figure 5d. The leakage inductor Lk1 will confine the charge current of CS4 , resulting in ZCS turn-off at S4 . When the voltage vds4 rises to vCb2 , Stage 5 begins. Stage 5 [t4 , t5 ]: The equivalent circuit of this stage is illustrated in Figure 5e, in which all the switches are turned off except S6 . Capacitor Co1 still absorbs energy from L0 m2 and Lk2 . In addition, L0 m2 forwards energy to Cb1 by the ideal transformer and via the loop of N1 -Lk1 -DS1 -Cb1 -DS3 . This current path is referred to the red dashed line in Figure 5e. The current flowing through Lk2 keeps on decreasing. This stage ends at the time that iLk2 is zero. That is, energy in Lk2 is completely recycled. Stage 6 [t5 , t6 ]: Figure 5f depicts the equivalent circuit of this mode, in which all switches have the same statuses as in Stage 5. The current direction of iLk2 changes at t = t5 , and Lk2 absorbs energy from Co1 , as referred to the green dashed line in Figure 5f. The circuit operation in low voltage side is identical to that in Stage 5. Therefore, the inductor L1 keeps on energy supplying toward VL and its current decreases linearly. Stage 6 continues until switch S6 is turned off at t = t6 . Stage 7 [t6 , t7 ]: During the interval that S6 is open, the voltage vds6 increases. Therefore, the voltage, vLm2 + vLk2 , drops and the parasitic capacitor CS5 dumps its stored energy, as referred to the green dashed line in Figure 5g. The circuit operation in low-voltage side behaves identically to Stage 6. When the energy in CS5 is drawn out completely and vds6 rises to VH , this stage stops. Figure 5g expresses the operation of the converter in Stage 7. Stage 8 [t7 , t8 ]: In Stage 8, the body diode DS5 is in forward bias, which provides a ZVS condition for S5 . The green dashed line in Figure 5h shows this current path. Leakage energy in inductors Lk2 and Lk1 is recycled to Co2 and Cb1 . In addition, L1 proceeds with energy releasing to VL while L0 m2 still forwards energy to low voltage side via the ideal transformer. When switches S2 , S4 , and S5 are turned on simultaneously, this stage ends. The corresponding equivalent circuit is depicted in Figure 5h. Stage 9 [t8 , t9 ]: At t = t8 , the operation of the converter enters into Stage 9. Figure 5i is the equivalent. The voltage polarity of the ideal transformer reverses because S2 and S4 are closed. Over the time interval of Stage 9, Lk2 and Lk1 continuously dump their stored energy and thus the currents iLk1 and iLk2 reduce. Additionally, the voltage level of vCb1 is higher than VL , which results that the inductor L1 absorbs energy from Cb1 and its current increases negatively and linearly, as referred to the blue dashed line in Figure 5i. This stage lasts until iLk2 drops to zero. Stage 10 [t9 , t10 ]: After the time t = t9 , the current direction of Lk2 changes and iLk2 increases. Switch statues in Stage 9 are identical to that in Stage 10. That is, S2 , S4 , and S5 are in on state, whereas S1 , S3 , and S6 stay in off state. The equivalent circuit is shown in Figure 5j, in which the L0 m2 draws energy from Co2 and the voltage across L1 is still kept at VCb1 − VL . As the red dashed line in Figure 5j indicates, leakage inductor Lk1 continues releasing energy and iLk1 decreases. When iLk1 is zero at t = t10 , this stage ends.

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Stage 11 [t10 , t11 ]: Figure 5k shows the equivalent circuit of this stage, in which the statuses of all switches are kept as in Stage 10. During this time interval, Cb1 continuously supplies energy to VL and L1 by the loop of 296 Cb1 -L1 -VL -S2 , of which current path is referred to the blue dashed line in Figure Energies 2017, 10, 8 of 23 5k. The current directions of N1 and N2 reverse and the current iLk1 rises positively. Meanwhile, capacitor The current of N1 and N2 reverse and the current iLk1 rises positively. Meanwhile, capacitor Cb2 charges anddirections Co2 discharges. CStage b2 charges and Co2 discharges. 12 [t11 , t12 ]: From the equivalent circuit depicted in Figure 5l, switches S2 , S4 , and S5 remain Stage 12 [t11, t12]: From the equivalent circuit depicted in Figure 5l, 0switches S2, S4, and S5 remain closed, while S1 , S3 , and S6 are open. In Stage 12, inductors Lk2 and L m2 are magnetized by Co2 with closed, while S1, S3, and S6 are open. In Stage 12, inductors Lk2 and L′m2 are magnetized by Co2 with the the same circuit behavior in Stage 11. Since the magnitude of iLk1 is greater than iL1 , the current flowing same circuit behavior in Stage 11. Since the magnitude of iLk1 is greater than iL1, the current flowing through S2 becomes reverse, and then S2 achieves ZCS at turn-off transition, as referred to the red through S2 becomes reverse, and then S2 achieves ZCS at turn-off transition, as referred to the red dashed lineline in Figure 5l.5l. The operation overone oneswitching switching cycle is completed when dashed in Figure The operationof ofthe the converter converter over cycle is completed when the switches S2 , SS24, ,Sand S are turned off simultaneously. the switches 4, and 5S5 are turned off simultaneously. S6

S6

DS6 L1

VL CS1 DS1

S4

N1

S2

S3

CS2

DS3 CS4 CS3

CS6 L'm2

DS6 L1

Co1

DS4

VL CS1

Lk2 S5

DS2

S1 Cb1

Lk1

N2

DS1

CS5 DS5

VH

Cb2

S4

N1

S2

S3

CS2

(a)

DS3 CS4 CS3

CS6 L'm2

DS4

CS5 DS5

VH

Cb2

Co2

(b) S6

S6

DS6 L1

VL CS1 DS1

N2 S4

N1

S2

S3

CS2

DS3 CS4 CS3

CS6 L'm2

DS6 L1

Co1

DS4

VL CS1

Lk2 S5

DS2

S1 Cb1

Lk1

DS1

CS5 DS5

VH

Cb2

N1

S2

S3

CS2

DS3 CS4 CS3

CS6 L'm2

DS4

CS5 DS5

VH

Cb2

Co2

(d) S6

S6

DS6 VL CS1 DS1

S2

S3

CS2

DS3 CS4 CS3

CS6 L'm2

DS6 L1

Co1

DS4

VL CS1

Lk2 S5

DS2

S1 Cb1

Lk1

N2 S4

N1

DS1

CS5 DS5

VH

Cb2

S2

S3

CS2

DS3 CS4 CS3

CS6 L'm2

DS4

CS5 DS5

VH

Cb2

Co2

(f) S6

S6

DS6 VL CS1 DS1

N2 S4

N1

S2

S3

CS2

DS3 CS4 CS3

CS6 L'm2

DS6 L1

Co1

DS4

VL CS1

Lk2 S5

DS2

S1 Cb1

Lk1

DS1

CS5 DS5

VH

Cb2

S4

N1

S2

S3

CS2

DS3 CS4 CS3

CS6 L'm2

DS4

CS5 DS5

VH

Cb2

Co2

(h) S6

S6

DS6 VL CS1 DS1

S2

S3

CS2

DS3 CS4 CS3

CS6 L'm2

DS6 L1

Co1

DS4

VL CS1

Lk2 S5

DS2

S1 Cb1

Lk1

N2 S4

N1

DS1

CS5 DS5

VH

Cb2

S2

S3

CS2

DS3 CS4 CS3

CS6 L'm2

DS4

CS5 DS5

VH

Cb2

Co2

(j) S6

S6

DS6

DS6

CS6 VL CS1 DS1

N2 S4

N1

S2

CS2

S3

DS3 CS4 CS3

L'm2

L1

Co1

DS4

(k)

DS1

CS5 DS5

Cb2

VL CS1

Lk2 S5

DS2

S1 Cb1

Lk1

Co1

Lk2 S5

DS2

S1 Cb1

Co2

Lk1

N2 S4

N1

(i) L1

Co1

Lk2 S5

DS2

S1 Cb1

Co2

Lk1

N2

(g) L1

Co1

Lk2 S5

DS2

S1 Cb1

Co2

Lk1

N2 S4

N1

(e) L1

Co1

Lk2 S5

DS2

S1 Cb1

Co2

Lk1

N2 S4

(c) L1

Co1

Lk2 S5

DS2

S1 Cb1

Co2

Lk1

N2

VH Co2

S4

N1

S2

CS2

S3

DS3 CS4 CS3

Co1

Lk2 S5

DS2

S1 Cb1

Lk1

N2

CS6 L'm2

DS4

CS5 DS5

Cb2

VH Co2

(l)

Figure 5. Equivalent circuit of proposed bidirectional converter in step-down mode. (a) Stage 1; (b)

Figure 5. Equivalent circuit of proposed bidirectional converter in step-down mode. (a) Stage 1; Stage 2; (c) Stage 3; (d) Stage 4; (e) Stage 5; (f) Stage 6; (g) Stage 7; (h) Stage 8; (i) Stage 9; (j) Stage 10; (b) Stage 2; (c) Stage 3; (d) Stage 4; (e) Stage 5; (f) Stage 6; (g) Stage 7; (h) Stage 8; (i) Stage 9; (j) Stage 10; (k) Stage 11; and (l) Stage 12. (k) Stage 11; and (l) Stage 12.

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Ts

vgs6

D6Ts

t

vgs2, vgs4,vgs5

D5Ts

S1

t

vds1 t

ids1 S2

vds2 ids2 t

vds3

S3

t

ids3 vds4 ids4

S4

t

vds5 S5

ids5 t

vds6 ids6

S6

t

iL1 iLk1 iLk2

iLk2

t

iLk1

iL1

iLm2 t Stage 1 Stage 2 Stage 3 Stage 4 Stage 5 Stage 6 Stage 7 Stage 8 Stage 9 Stage 10 Stage 11 Stage 12

t0

t1

t2

t3

t4

t5

t6

t7

t8

t9

t10

t11

t12

Figure 6. Key Key waveforms waveforms of of the the proposed proposed converter in step-down mode. Figure

According According to to the the aforementioned aforementioned operation operation principle, principle, the the switching switching characteristics characteristics of of all all power power switches are summarized in Table 1. switches are summarized in Table 1. Table Table 1. The The switching characteristics of the proposed converter.

Main Circuit Main Circuit Low-Voltage Side High-Voltage Side Low-Voltage Side High-Voltage Side S1 S2 S3 S4 S5 S6 S2 S5 S6 4 Step-up S1ZVS ZVS ZVSS3 ZVS Snone none Step-up ZVS none ZVSZCS ZVS Step-downZVS none ZCS ZVS none ZVS none ModeMode

Step-down

none

ZCS

none

ZCS

ZVS

ZVS

3. Steady-State Analysis 3. Steady-State Analysis In this section, the steady-state analysis of the BDC includes voltage conversion ratio, voltage this section, themagnetic steady-state analysis of the includes voltage the conversion ratio,made voltage stressInderivation, and element design. To BDC simplify the analysis, assumptions in stress derivation, and magnetic element design. To simplify the analysis, the assumptions made in Section 2 are considered except the neglect of leakage inductors. In addition, the phenomenon that Sectionat2 switching are considered except the ignored. neglect of leakage inductors. In addition, the phenomenon that occurs transient is also occurs at switching transient is also ignored.

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3.1. Step-Up Mode Voltage gain of the converter in step-up mode is first investigated. Because the output voltage VH is the sum of VCo1 and VCo2 , the relationships of VCo1 to VL and VCo2 to VL have to be found in advance. The voltage VCo1 is n times the magnitude of VCb1 and VCo2 is n times the VCb2 under the condition that leakage inductor is neglected. Accordingly, VCb1 and VCb2 in terms of VL should be determined before the finding for VCo1 and VCo2 . Since S1 and S2 are switched complementarily, the input voltage VL can be boosted via inductor L1 . As a result, the voltage across Cb1 is given by VCb1 =

VL , 1 − D1

(1)

where D1 is the duty ratio of S1 . Refer to Figure 4 at any time there are two switches in closed state simultaneously over one switching cycle. While S1 and S3 are on, the voltage across L0 m1 is VCb1 and thus the amount of current increase can be estimated by ∆i Lm1,S3on =

VCb1 D3 Ts L0 m1

(2)

In Equation (2), the D3 denotes the duty ratio of S3 . After S3 is turned off, switch S4 will be turned on. That is, the both switches S1 and S4 are in on state. The voltage across L0 m1 becomes VCb1 − VCb2 . If VCb1 is greater than VCb2 , the L0 m1 will proceed with current increasing. The increment can be expressed as (V − V ) ∆i Lm1,S3o f f = Cb1 0 Cb2 ( D1 − D3 ) Ts (3) L m1 The switch S2 will be turned on when switch S1 is turned off. That is, S2 and S4 are in on state simultaneously and the voltage across L0 m1 is −VCb2 . The current flowing through L0 m1 decreases, which is given by V ∆i Lm1,S1o f f = 0Cb2 (1 − D1 ) Ts (4) L m1 In steady state, the net current change on L0 m1 is equal to zero. From Equations (2)–(4), the following relationship can be derived VCb1 (V − V ) V D3 Ts + Cb1 0 Cb2 ( D1 − D3 ) Ts − 0Cb2 (1 − D1 ) Ts = 0 L0 m1 L m1 L m1

(5)

Substituting Equation (1) into Equation (5) becomes VCb2 =

D1 V (1 − D1 )(1 − D3 ) L

(6)

The output voltage VH = VCo1 + VCo2 , which can be also obtained from VH = n(VCb1 + VCb2 )

(7)

Therefore, the conversion ratio of output voltage to input voltage in step-up mode, Mstep-up , can be found by V n(1 + D1 − D3 ) Mstep-up = H = (8) VL (1 − D1 )(1 − D3 ) As referring to the switching sequence in step-up mode, during the interval that S2 and S4 are open but S1 and S3 are closed, the S2 and S4 endure the voltages of VCb1 and VCb2 , respectively. After the above switch status, S2 and S3 will be open but S1 and S4 are closed. The blocking voltages at S2 and S3 are VCb1 and VCb2 , respectively. The switch status that S1 and S3 are off but S2 and S4 are on

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proceeds the converter operation. The voltages across S1 and S3 in this time interval are also VCb1 and VCb2 in turn. In brief, the voltage stresses with respect to S1 , S2 , S3 and S4 can be determined as follows: VL 1 − D1

(9)

D1 V (1 − D1 )(1 − D3 ) L

(10)

vS1-stress = vS2-stress = vS3-stress = vS4-stress =

At high-voltage side, the switch S5 will withstand a voltage of at least VH when the intrinsic diode of S6 is forward biased. Similarly, S6 also endures a reverse voltage up to VH during the interval that the diode DS6 is on. That is, n(1 + D1 − D3 ) vds5 = vds6 = V (11) (1 − D1 )(1 − D3 ) L With respect to inductance design, the average current carried by magnetic component has to be calculated in advance. For L0 m1 , the application of amp-second balance criterion (ASBC) at Cb2 can give an assistance to the finding for the average of iLm1 . The Cb2 charges during the time interval [t5 , t6 ], in which S1 and S4 are in on state. On the contrary, Cb2 discharges during [t8 , t9 ], while S2 and S4 are closed. The charging current of Cb2 is equal to iLm1 and discharging current will be iLm1 + nids5 . Thus, the following relationship holds: i Lm1 ( D1 − D3 ) Ts + (i Lm1 −

n i H )(1 − D1 ) Ts = 0 1 − D1

(12)

From Equation (12), the average current carried by L0 m1 can be given as ILm1 =

n IH 1 − D3

(13)

If the voltage across Cb1 is close to VCb2 , the current iLm1 can be regard as constant in Stage 6. This phenomenon can be found in Figure 4. Assume that L0 m1 is in BCM. The following relationship can be found: [( D1 − D3 ) Ts + Ts ] VL0Cb1 D3 Ts n m1 = IH (14) 2Ts 1 − D3 Solving for L0 m1 results: L0 m1,min =

D3 (1 − D3 )2 R H 2n2 f s

(15)

where L0 m 1,min is the minimum inductance of L0 m1 for CCM operation, RH stands for load resistance at high-voltage side, and fs is switch frequency. To determine the minimum inductance of L1 , L1,min , for CCM operation, average current of iL1 has to be contacted. This average current can be found by applying ASBC to Cb1 . Capacitor Cb1 charges during the time interval [t7 , t9 ], in which both switches S2 and S4 are closed. There are two intervals to discharge the energy in Cb1 . One is [t2 , t4 ], in which S1 and S3 are closed, and the other is and [t4 , t7 ], in which S4 and S1 are in on state. Based on ASBC, the following relationship holds:

(−

n i H − i Lm1 ) D3 Ts + i Lm1 ( D3 − D1 ) Ts + i L1 (1 − D1 ) Ts = 0 D3

(16)

Using Equation (13) and substituting for iLm1 , the average current flowing through L1 can be represented as n(1 + D1 − D3 ) IL1 = I (17) (1 − D1 )(1 − D3 ) H

Using Equation (13) and substituting for iLm1, the average current flowing through L1 can be represented as

n(1  D1  D3 ) IH (1  D1 )(1  D3 )

I L1 

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The current increment on L1, ΔiL1, is estimated by The current increment on L1 , ∆iL1 , is estimated by

V i  VLL DD1TTs s LL11 1

(18) (18)

L1 = ∆i L1

L1,, IIL1,min , is, isgiven givenbyby Hence, the minimum of iL1 L1,min

IILL1,min = 1, min 

nn(1 (1+D D11  −D D33)) VVL T1sTs IIHH − L D1D (1−D D11)(1 )(1−D D33)) 2L (1 2L 11

(19) (19)

At BCM, IIL1,min Solvingfor forL1Lyields 1 yields L1,min == 0.0.Solving

 LL1,min 1, min =

D1 ((11  RHH D −D D11))2 (1 (1  −D D33))2 R 2

2

(20) (20)

1+ −D D33 )2 ffss 22n n22((1  D11 

70

L' m1, min

120

Inductance L1 (μH)

Inductance L' m1 (μH)

in which is the the minimum inductance which LL1,min 1,min is inductanceof ofLL11 for forCCM. CCM.IfIfRRHH== 640 640Ω, Ω,ffss == 40 kHz, kHz, nn == 3, 3, and and D D11 = D33.. Figure 7a depicts depicts the the relationships relationships between between inductance inductance LL′0 m1 m1 and duty ratio D1 1 while Figure 7b is for inductance L11 versus D11..

100 80 60

DCM

CCM

40 20 0

0

0.2

0.4 0.6 0.8 Duty Cycle (D1 = D3)

60 40 30

CCM

DCM

20 10 0

1

L1, min

50

0

(a)

0.2

0.4 0.6 0.8 Duty Cycle (D1 = D3)

1

(b)

Figure7.7.Magnetic Magneticcomponent componentdesign designfor for(a) (a)LL′ and (b) (b) LL1 under the duty ratio D1 = D3. 0 m1 and Figure m1 1 under the duty ratio D1 = D3 .

3.2. Step-Down Step-Down Mode Mode 3.2. All the the assumptions assumptions in in the the above above subsection subsection are are also also adopted adopted for for the the steady-state steady-state analysis analysis in in All step-down mode. The switches S 2, S4, and S5 are controlled simultaneously and complementary to S6. step-down mode. The switches S2 , S4 , and S5 are controlled simultaneously and complementary to S6 . During the the interval interval that that SS6 is is in in turned-on turned-on state state and and SS2,, SS4,, and S5 are in turned-off state, the voltage During 6 2 4 and S5 are in turned-off state, the voltage V Co1 will directly impose on the high-voltage side of the transformer. Then, the body diodes Ds1 and VCo1 will directly impose on the high-voltage side of the transformer. Then, the body diodes Ds1 and Ds3 forward conduct and the voltage VCb1 will be equal to VCo1/n. The inductor L1 supplies energy to D s3 forward conduct and the voltage VCb1 will be equal to VCo1 /n. The inductor L1 supplies energy to VL.. This state will last for D6Ts. During the interval (1 − D6)Ts, S6 becomes off but S2, S4, and S5 are on. V L This state will last for D6 Ts . During the interval (1 − D6 )Ts , S6 becomes off but S2 , S4 , and S5 are on. The voltage polarity of of the the coupled coupled inductor inductor at at high-voltage high-voltage side side reverses reverses and and its its magnitude magnitude equals equals The voltage polarity VCo2. . In addition, the voltage across inductor L1 is VCb1 − VL while VCb2 equals VCo2/n. Applying V Co2 In addition, the voltage across inductor L1 is VCb1 − VL while VCb2 equals VCo2 /n. Applying volt-second balance criterion criterion (VSBC) (VSBC) to to LL1 yields yields volt-second balance 1

VVL =  ((11 − DD6))VVCb1 L

6

Cb1

(21) (21)

Equation (21) can also be expressed as VL =

(1 − D6 )VCo1 n

(22)

Similarly, applying VSBC to magnetizing inductor L0 m2 , the following relationships can be found: VCo1 = (1 − D6 )VH

(23)

n Similarly, applying VSBC to magnetizing inductor L′m2, the following relationships can be found:

VCo1  (1  D6 )VH

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and and

 DV

V

(24) (24)

Co 2 = D66VH VCo2 H

Substituting Equation (23) (23) into into Equation Equation (22) (22) has has the the result: result: Substituting Equation

)2 VL ((11  −D D66 )2 V L  M  step  down = Mstep-down VHH = V nn

(25) (25)

in which which M Mstep-down step-down stands standsfor forthe theratio ratioof of output output to to input input voltage voltage as as in step-down mode. Figure 8a shows the the curves curvesof ofM Mstep-up step-up versus ratio D D11, while while M Mstep-down step-down versus versus duty ratio versusduty dutyratio ratio D D66 isis illustrated illustrated in Figure 8b. 30

1

0.8 Voltage Gain (VL/VH)

Voltage Gain (VH/VL)

25

20 15 n=4

10

n=3

n=1

0

0.2

0.4 0.6 Duty Cycle (D1 = D3)

n=1 n=2

0.4

0

0.8

VL = 48 V VH = 400 V

n=3

0.2

VL = 48 V VH = 400 V

5 0

n=2

0.6

n=4

0

0.2

(a)

0.4 0.6 Duty Cycle (D6)

0.8

(b)

Figure converter: (a)(a) step-up mode; andand (b) Figure 8. 8. Voltage Voltageconversion conversionratio ratioofofthe theproposed proposedbidirectional bidirectional converter: step-up mode; step-down mode. (b) step-down mode.

The discussion relating to the voltage stresses of the semiconductor devices is followed up. The discussion relating to the voltage stresses of the semiconductor devices is followed up. Because the diode DS1 and switch S2 conduct complementarily, from the mesh of Cb1-S1-S2, it can be Because the diode DS1 and switch S2 conduct complementarily, from the mesh of Cb1 -S1 -S2 , it can be found that voltage stress of S1 is identical to that of S2 and equals VCb1. Similarly, DS3 and S4 are in found that voltage stress of S is identical to that of S2 and equals VCb1 . Similarly, DS3 and S4 are in complementary conduction, 1and the voltage stresses of S3 and S4 will be equal to VCb2. At complementary conduction, and the voltage stresses of S3 and S4 will be equal to VCb2 . At high-voltage high-voltage side, from the outermost loop, S5-S6-VH, the input voltage VH will impose on S5 and S6 side, from the outermost loop, S5 -S6 -VH , the input voltage VH will impose on S5 and S6 alternately. alternately. That is, S5 and S6 have to stand a voltage of VH. That is, S5 and S6 have to stand a voltage of VH . The current gain of the converter is a reciprocal of the voltage ratio shown in Equation (25). The current gain of the converter is a reciprocal of the voltage ratio shown in Equation (25). Therefore, the input current IH is given by Therefore, the input current IH is given by

(1  D )2 (1  D )2V I H  (1 − D66 )2 I L (1 − D6 )62 VL L IH = IL = n nRL n

nR L

(26) (26)

where RL denotes the load resistance at low-voltage side. From Figure 5f, the average current of where RL denotes the load resistance at −𝑖low-voltage side. From Figure 5f, the average current of 𝑑𝑠3 magnetizing inductance L L′0m2 isisequals , which magnetizing inductance equalsto to −𝑛inds3 −−ids6 ids6 , whichcan canbebefurther furtherestimated estimatedbyby m2 ILm2 =

I (1 − D6 ) IL − H nD6 D6

(27)

In addition, the current decrement on L0 m2 over one switching cycle, ∆iLm2 , can be expressed as ∆i Lm2 =

D6 Ts VCo1 L0 m2

(28)

Using Equation (23) and Equation (25) to substitute for VCo1 yields ∆i Lm2 =

D6 Ts nVL (1 − D6 ) L0 m2

(29)

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The minimum value of iLm2 can be calculated by ILm2 − ILm2,min =

∆i Lm2 2

and is computed as

(1 − D6 )VL D6 Ts nVL − nR L 2(1 − D6 ) L0 m2

(30)

At boundary, ILm2,min = 0. Then, solving for L0 m2 can obtain the following relation for determining the minimum inductance for CCM: L0 m2,min =

n2 D6 R L

(31)

2(1 − D6 )2 f s

In order to find the minimum value of L1 for continuous current operation, L1,min , the average current of L1 , IL1 , has to be found. The IL1 is equal to the output current IL , which is given by IL1 =

VL RL

(32)

The change on inductor current iL1 can be computed from ∆i L1 =

D6 Ts VL L1

(33)

Accordingly, minimum of IL1 is IL1,min =

VL D Ts VL − 6 RL 2L1

(34)

Let IL1,min = 0 and solving for L1 can obtains: L1,min =

D6 R L 2 fs

(35)

Assume that RL is 9.216 Ω, fs is 40 kHz, and n = 3. Figure 9a depicts the relationship between D6 and L0 m2 , while L1 versus D6 is illustrated in Figure 9b. Energies 2017, 10, 296 15 of 23

1.5 1

L' m2, min CCM DCM

0.5 0

Inductance L1 (μH)

Inductance L' m2 (mH)

2

0

0.1

0.2 0.3 Duty Cycle (D6)

0.4

0.5

50

L1, min

40 30

CCM

20

DCM

10 0

0

0.1

(a)

0.2 0.3 Duty Cycle (D6)

0.4

0.5

(b)

Figure 9. The relationship between the inductance and duty ratio D6: (a) L′m2; and (b) L1. Figure 9. The relationship between the inductance and duty ratio D6 : (a) L0 m2 ; and (b) L1 .

Figure 10 is the equivalent circuit of proposed converter considering non-ideal parameters, in Figure 10 is thethe equivalent of proposed considering non-ideal which rL1 represents inductor circuit resistance at the lowconverter voltage side and rds1, rds2 , rds3, rds4,parameters, rds5, and rds6 in which r represents the inductor resistance at the low voltage side and r , rds3r, lk2rds4 , rds5 L1 ds1 , rrds2 are the on-state resistance of switches S1, S2, S3, S4, S5, and S6, respectively; and lk1 and are the, and r are the on-state resistance of switches S , S , S , S , S , and S , respectively; and r and r 1 one 2 3respectively. 4 5 6 using VSBC and lk1 ds6 winding resistances and the secondary lk2 primary By ASBC, the are the primary winding resistances and the secondary one respectively. By using VSBC and ASBC, non-ideal voltage conversion ratio M′step-up and conversion efficiency ηstep-up in step-up mode can be 0 the non-ideal obtained as voltage conversion ratio M step-up and conversion efficiency η step-up in step-up mode can be obtained as M'Step -up =

-n(-2(1+D1 -D3 )f s Lm +(-1+D3 )D3 (-2rds4 +(-3+2D3 )rlk1 )) r r - ds5 + ds6 +4rlk2 n 2 ((-1+D1 ) 2 D1rds3 +D33 (rds1 +D1rL1 )-2D3 2 ((1+D1 )rds1 +D1 (rds2 -D1rds2 +rL1 +D1rL1 +(-1+D1 ) 2 rlk1 ))+D3 ((1+D1 ) 2rds1 +D1 (-3(-1+D1 )rds2 +(1+D1 ) 2 rL1 +3(-1+D1 ) 2 rlk1 ))) -1+D1 D3 2(-1+D1 )(-1+D3 )f s Lm (1+ + ) 2 2 (-1+D1 ) D1 (-1+D3 ) D3 RH RH





(36)

Figure 10 is the equivalent circuit of proposed converter considering non-ideal parameters, in which rL1 represents the inductor resistance at the low voltage side and rds1, rds2, rds3, rds4, rds5, and rds6 are the on-state resistance of switches S1, S2, S3, S4, S5, and S6, respectively; and rlk1 and rlk2 are the primary winding resistances and the secondary one respectively. By using VSBC and ASBC, the non-ideal voltage conversion ratio M′step-up and conversion efficiency ηstep-up in step-up mode can be Energies 2017, 10, 296 15 of 23 obtained as

M0 Step-up =

-n(-2(1+D1 -D3 )f s Lm +(-1+D3 )D3 (-2rds4 +(-3+2D3 )rlk1 )) −n(−2(1+ D M'Step -up = 1 − D3 ) f s Lm +(−1+ D3 ) D3 (−2rds4 +(−3+2D3 )rlk1 )) rds5 2 rds6 r rds6 2 2 2 2 +4rlk2 − −1ds5 + D3 3 (3 rds1 + D1 r L1 )−2D23 2 ( (1+ D1 )rds1 + D1 (rds2 − D1 rds2 +r L1 + D1 r L1 +(2−1+ D1 ) rlk1 ))+2D3 ( (1+ D1 ) rds1 + D1 (−3(−1+ D21 )rds2 +(1+ D12) r L1 +3(-−1+ D1 )+ rlk1 ))) n2 ( ( − 1+ D ) D r + D1 + D3 +4rlk2 n 2 ((-1+1D1 ) 21Dds3 D1 ) rlk1 ))+D ((1+D1 ) rds1 +D1 (-3(-1+D1 )rds2 +(1+D1 ) rL1 +3(-1+D1 ) rlk1 ))) -1+D1 D3 +) ) 2(−1+ D12( )(− +D 1 rds3 +D3 (rds1 +D1rL1 )-2D3 ((1+D1 )rds1 +D1 (rds2 -D1rds2 +rL1 +D1rL1 +(-1+ 3 ) f s L m (1+ 23 2 RH -1+1D + −1+ D1 ) D1 (2 −1+ D3 ) D3 R H 1 )(-1+D3 )f s Lm (1+ (-1+D1() 2 D1 (-1+ D3 ) D3 RH RH

(36)

  (1 − D1 )(1 − D3 ) ηStep-up = M0 Step-up 1+  (1  Dn1()(1  DD3 )1 − D3 ) (37) Step-up  M'Step-up   D1 efficiency D3 )  In addition, step-down voltage ratio M0 step-down η step-down are estimated by  n(1 and  step-down voltage ratio M′step-down and efficiency ηstep-down are estimated by In addition, (−1+ D6 )2 D6 nR L M0 Step-down = 3  2 (1  D ) 2 D nR



6 +r lk1 6 +LD6 (r ds2 − D6 r ds2 +(−2+ D6 )r ds3 + R L +r L1 +(−2+ D6 )r lk1 )) (−1+ D6 ) (−rds6 + D6 (rds5 +rds6 ))+n (rds1 +rds3 M'Step-down    (38) 3 2  (1  D6 ) (rds 6  D6 (rds 5  rds 6 ))  n (rds1  rds 3  rlk1  D6 (rds 2  D6 rds 2  (2  D6 )rds 3  RL  rL1  ( 2  D6 )rlk1 )) 

"

#

n

(36)

(37)

(38)

 n ηStep-down = M Step-down (39) (39) Step-down  M'Step-down  (1 − D2 )2 6 (1  D ) 6   Based Based on Equations (36) to (39), relationships of voltage gain versus duty ratios D and D3 on Equations (36) to (39), relationships of voltage gain versus duty ratios D1 and D3 1in in step-up mode are depicted in Figure 11a,b, respectively; meanwhile, do Figure 11c,d for step-up mode are depicted in Figure 11a,b, respectively; meanwhile, so dosoFigure 11c,d for step-down operation. Figure 12 12 shows voltage gain in step-up different step-down operation. Figure showsthe thenon-ideal non-ideal voltage gain in step-up modemode underunder different choke resistances. choke resistances. 0

High-Voltage Side

Low-Voltage Side

rL1

rds6

L1

N2

VL rlk1

rds1 S1

Lk1

N1

S2

Lm1

rds4

S4

rds2

Lm2

Cb2 rds3

Co1 rlk2

Lk2

S5

S3

Cb1

S6

VH

Co2

rds5

Figure non-idealequivalent equivalent circuit of of thethe converter. Figure 10. 10. TheThe non-ideal circuit converter. Energies 2017, 10, 296

0 50 45 40 35 30 25 20 15 10 5 0

0

0.1

0.2

rL1=13 mΩ, rds1=rds2=9 mΩ rds3=rds4=8 mΩ, rds5=rds6=0.12 Ω rlk1=33.125 mΩ, rlk2=100 mΩ RH=160 Ω

1.0

) (D 3 ycle 0.5

3) 1.0 le (D Cyc Duty 0.5

rL1=13 mΩ, rds1=rds2=9 mΩ rds3=rds4=8 mΩ, rds5=rds6=0.12 Ω rlk1=33.125 mΩ, rlk2=100 mΩ RH=160 Ω

Efficiency(ƞ)

Voltage Gain (VH/VL)

yC D ut

16 of 23

0.3

0.4

0.5

0.6

0.7

0.8

Duty Cycle (D1)

0.9

0 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 00

0.1 0.2 0.3

0.4 0.5 0.6 Duty Cycle (D1)

1.0

(a)

0.7

0.8

0.9

1.0

(b)

0.25

Efficiency(ƞ)

rL1=13 mΩ

1

Voltage Gain (VL/VH)

rds1=rds2=9 mΩ

0.20

rds3=rds4=8 mΩ rds5=rds6=0.12 Ω rlk1=33.125 mΩ, rlk2=100 mΩ RL=2.304 Ω

0.15

0.8

rL1=13 mΩ rds1=rds2=9 mΩ

0.6

rds3=rds4=8 mΩ rds5=rds6=0.12 Ω

0.10

0.4

0.05

0.2

rlk1=33.125 mΩ, rlk2=100 mΩ RL=2.304 Ω

0

0

0.2

0

0.4

0.6

0.8 1.0 Duty Cycle (D6)

(c)

0

0.2

0.4

0.6

0.8 1.0 Duty Cycle (D6)

(d)

Figure 11. The relationships of voltage gain versus duty ratio and efficiency versus duty ratio while

Figure 11. The relationships of voltage gain versus duty ratio and efficiency versus duty ratio while considering non-ideal effect: (a) M′step-up; (b) ηstep-up; (c) M′step-down; and (d) ηstep-down. considering non-ideal effect: (a) M0 step-up ; (b) η step-up ; (c) M0 step-down ; and (d) η step-down . MStep-up 50

40

30

20

Ideal 13 mΩ 160 mΩ 240 mΩ 320 mΩ

Ideal

0

0

0.2

0.4

0.6

0

0.8 1.0 Duty Cycle (D6)

0.2

0.4

(c)

0.6

0.8 1.0 Duty Cycle (D6)

(d)

Figure 11. The relationships of voltage gain versus duty ratio and efficiency versus duty ratio while Energies 2017, 10, 296 16 of 23 considering non-ideal effect: (a) M′step-up; (b) ηstep-up; (c) M′step-down; and (d) ηstep-down. MStep-up 50 Ideal 13 mΩ 160 mΩ 240 mΩ 320 mΩ

40

Ideal

30

20

10

0

0.2

0

0.4

0.6

0.8

1.0

Duty cycle (D1=D3)

Figure 12. The step-up voltage gain under different choke resistances.

Figure 12. The step-up voltage gain under different choke resistances. Among all power switches, the main switch S1 will endure the maximum current stress no matter Among all power switches, the main switch S1 will endure the maximum current stress no in step-up or step-down mode. Thereby, the current stress determination is focused on S1 . This current matter in step-up or step-down mode. Thereby, the current stress determination is focused on S1. stress can be estimated by the sum of the valley current of inductor L1 and the peak current of leakage This current stress can be estimated by the sum of the valley current of inductor L1 and the peak inductance Lk1 . That is, current of leakage inductance Lk1. That is, IL (2 − D6 ) VL D6 Ids1,peak =



D6

I (2  D )

(40)

2 f s L1

VD

L 6 L 6 As for the current stresses of other active switches in step-down mode, the ASBC should be (40) I dsthe  1, peak  2 f L applied to capacitors Co1 , Co2 , Cb2 , and Cb1 , whichD yields 6 s 1

2− D6 V D As for the current stresses of the Iother active switches be − Lin 6step-down mode, the ASBC should (41) ds2,peak = IL D 2 f L s 1 6 applied to capacitors Co1, Co2, Cb2, and Cb1, which yields I (1 − D6 ) 2 = D = Ids4,peak 2 6L VL D6 IIdsds3,peak  I D6 2, peak L D 2 f s L1 nD V I (1 − D )(26+ D )

Ids5,peak = Ids6,peak =

6

L

6

nD6



6 L

2(1 − D6 ) f s L0 m2

(42) (43)

Similarly, in step-up mode, current stresses of switches can be expressed as

Ids1,peak =

h i nIH 2(1 − D1 + D1 D3 ) − D3 2 D3 (1 − D1 )(1 − D3 )

Ids2,peak = nIH

+

VL D3 2 f s L1

2 − D3 V D + L 1 (1 − D1 )(1 − D3 ) 2 f s L1

Ids3,peak = Ids4,peak = nIH

2 − D3 VL D3 + D3 (1 − D3 ) 2 f s L0 m1 (1 − D1 )

Ids5,peak =

(44)

(45) (46)

2IH (1 − D1 )

(47)

2IH D3

(48)

Ids6,peak = 4. Experimental Results

To validate the proposed BDC, a 1-kW prototype is built with the specifications and components summarized in Table 2. If a converter operates in discontinuous conduction mode (DCM), it can easily avoid switching loss. However, during the interval of high power loading, serious conduction loss will result in unacceptable efficiency. The proposed converter intrinsically has the outstanding feature of

(41)

Energies 2017, 10, 296

17 of 23

soft switching at all power switches even in CCM. Therefore, we design the converter operation from DCM into CCM at 250-W power loading for overall efficiency consideration. Accordingly, a Toroids 55195-A2 MPP core and an EE-55 core are adopted to form main inductor and coupled inductor, respectively. To make sure the CCM and DCM operate, as mentioned, the main inductance L1 should be 46 µH and magnetizing inductance L0 m1 is 130 µH with a turns ratio of n = 3. Table 2. Specifications and components used in experimentations. Symbols

Values & Types

VL (Low voltage) VH (High voltage) Po (Output power) fs (Switching frequency) L1 (Filter inductance) L0 m1 (Magnetizing inductance) Lk1 (Leakage inductance) Lk2 (Leakage inductance) n (Transformer turns ratio) Cb1 and Cb2 (Capacitances) Co1 and Co2 (Capacitances) S1 and S2 (Switches) S3 and S4 (Switches) S5 and S6 (Switches)

48 V 400 V 1 kW 40 kHz 46.2 µH 130 µH 2.07 µH 18.82 µH 3 33 µF 220 µF IXFH160N15T2 IXTP160N075T IXFH52N50P2

According to the discussion in Section 3, voltage and current stresses of all active switches can be specified, which offers us a benefit to choose appropriate semiconductor devices for prototype constructing. Since a lower Rds(on) can achieve a higher conversion efficiency, active switches which meet the power rating and have conduction resistance as low as possible are considered. At low-voltage side, power MOSFETs IXFH160N15T2 with on-state resistance Rds(on) of 9 mΩ is chosen as S1 and S2 , while IXTP160N075T with 6 mΩ Rds(on) as S3 and S4 . With regard to the active switches S5 and S6 at high-voltage side, power MOSFET IXFH52N50P2 is considered, of which Rds(on) is 0.12 Ω. Microcontroller ATMEGA328P-PU is in charge of the converter controlling. Additionally, PV simulator Chroma 62050H-600S, high voltage power supply IDRC CDSP-500-010C, electronic load Chroma 63202 are adopted for terminal source or load. All waveforms are measured by oscilloscope KEYSIGHT DSOX4024A. Figure 12 shows the voltage and current waveforms measured from switches S1 –S6 , while D1 = 0.44 and D3 = 0.3. In Figure 13a, the first trace and second trace are the switch voltage and current of S1 , respectively, whereas the third and fourth traces depict the measurements of S2 . From Figure 13a, it can be found that S1 endures a voltage of around 100 V. This value is consistent with the estimation in Equation (9). The measured ids1 matches the conceptual waveform in Figure 4. In addition, the waveforms of vds2 and ids2 release that ZCS turn-off feature is achieved at S2 . Figure 13b presents the practical measurements of vds3 , ids3 , vds4 , and ids4 , which illustrates that both switches S3 and S4 can be turned on with ZVS. While operated in step-up mode, S5 and S6 of the converter are in the role of rectifier. Figure 13c presents the zoomed-in waveforms of S1 and S2 , and Figure 13d is for S3 and S4 . The blocking voltages of vds5 and vds6 are both equal to 400 V, as shown in Figure 13e, which conforms to the calculation of Equation (11). Figure 13f confirms a stable output and CCM operation in L1 ; moreover, the measurements of iLk1 and iLk2 are consistent with the waveforms in Figure 4.

illustrates that both switches S3 and S4 can be turned on with ZVS. While operated in step-up mode, S5 and S6 of the converter are in the role of rectifier. Figure 13c presents the zoomed-in waveforms of S1 and S2, and Figure 13d is for S3 and S4. The blocking voltages of vds5 and vds6 are both equal to 400 V, as shown in Figure 13e, which conforms to the calculation of Equation (11). Figure 13f confirms a stable 2017, output and CCM operation in L1; moreover, the measurements of iLk1 and iLk2 are consistent Energies 10, 296 18 of 23 with the waveforms in Figure 4.

vds1: 100 V/div vds3: 100 V/div ids3: 50 A/div

ids1: 50 A/div ZVS turn-on vds4: 100 V/div

ZVS turn-on

vds2: 100 V/div

ids4: 50 A/div

ids2: 100 A/div

ZVS turn-on

ZVS turn-on

(a)

(b) vds1: 100 V/div

ZVS turn-on

ids1: 50 A/div

vds3: 100 V/div ids3: 50 A/div

ZVS turn-on

vds4: 100 V/div vds2: 100 V/div

ZVS turn-on

ids4: 50 A/div

ZVS turn-on

ids2: 100 A/div Energies 2017, 10, 296

(c)

vds5: 500 V/div

(d)

19 of 23

VH: 500 V/div iL1: 20 A/div

ids5: 10 A/div vds6: 500 V/div

iLk1: 50 A/div

iLk2: 20 A/div

ids6: 10 A/div

(e)

(f)

Figure 13. 13. Experimental 1 kW: (a)(a) measurements from S1 Figure Experimentalresults resultsininstep-up step-upmode modeoperation operationatatPoP=o = 1 kW: measurements from and S 2; (b) measurements from S3 and S4; (c) zoomed-in waveforms measured from S1 and S2; (d) S1 and S2 ; (b) measurements from S3 and S4 ; (c) zoomed-in waveforms measured from S1 and S2 ; zoomed-in waveforms of S3ofand S4; (e) from from S5 andS Sand 6; and (f) waveforms of VH, iL1, iLk1, (d) zoomed-in waveforms S3 and S4measurements ; (e) measurements S6 ; and (f) waveforms of VH , 5 and i Lk2. iL1 , iLk1 , and iLk2 .

While operating in step-down mode with D6 = 0.37, related practical waveforms are shown in While operating in step-down mode with D6 = 0.37, related practical waveforms are shown in Figure 14. From Figure 14a,b, it can be seen that both switches S1 and S3 are just in charge of Figure 14. From Figure 14a,b, it can be seen that both switches S1 and S3 are just in charge of rectifying rectifying whereas S2 and S4 can accomplish ZCS turn-off feature. Figure 14c reveals that S5 and S6 whereas S2 and S4 can accomplish ZCS turn-off feature. Figure 14c reveals that S5 and S6 are turned are turned on with ZVS and their voltage stresses are about 400 V. The output voltage at low-voltage on with ZVS and their voltage stresses are about 400 V. The output voltage at low-voltage side and the side and the currents of L1, Lk1, and Lk2 are also given in Figure 14d, in which a constant 48 V output currents of L1 , Lk1 , and Lk2 are also given in Figure 14d, in which a constant 48 V output and CCM and CCM operation in L1 are illustrated. operation in L1 are illustrated. vds1: 100 V/div

vds3: 100 V/div

ids1: 100 A/div

ids3: 100 A/div

vds2: 100 V/div

vds4: 50 V/div

While operating in step-down mode with D6 = 0.37, related practical waveforms are shown in Figure 14. From Figure 14a,b, it can be seen that both switches S1 and S3 are just in charge of rectifying whereas S2 and S4 can accomplish ZCS turn-off feature. Figure 14c reveals that S5 and S6 are turned on with ZVS and their voltage stresses are about 400 V. The output voltage at low-voltage side and the10,currents of L1, Lk1, and Lk2 are also given in Figure 14d, in which a constant 48 V output Energies 2017, 296 19 of 23 and CCM operation in L1 are illustrated.

vds1: 100 V/div

vds3: 100 V/div

ids1: 100 A/div

ids3: 100 A/div

vds2: 100 V/div

vds4: 50 V/div

ids2: 100 A/div

ZCS turn-off

ZCS turn-off

ids4: 100 A/div

(a)

(b) VL: 50 V/div

vds5: 500 V/div

ids5: 100 A/div

ZVS turn-on

iL1: 100 A/div iLk1: 100 A/div

vds6: 500 V/div

iLk2: 100 A/div

ids6: 20 A/div ZVS turn-on

(c)

(d)

Figure 14. 14. Experimental results in in step-down step-down mode mode operation operation at at PPo = = 1 kW: (a) measurements from S1 Figure Experimental results o 1 kW: (a) measurements from S1 and S 2; (b) S3 and S4; and (c) S5 and S6; and (d) the waveforms of VL, iL1, iLk1, and iLk2. and S2 ; (b) S3 and S4 ; and (c) S5 and S6 ; and (d) the waveforms of VL , iL1 , iLk1 , and iLk2 .

Efficiency (%)

Figure 15 depicts measured efficiency of the prototype. The maximum values of the practical Figure 15 depicts measured efficiency of the prototype. The maximum values of the practical efficiency in step-up and step-down modes are up to 95.4% and 93.6%, respectively, while Po is equal Energies 2017, 10, 20 of 23 efficiency in 296 step-up and step-down modes are up to 95.4% and 93.6%, respectively, while Po is equal to 1 kW. The efficiency values are measured after 1hr burn-in test and the maximum temperature of to 1 kW. The efficiency values are measured after 1hr burn-in test and the maximum temperature of ◦ C.Figure allall active components the photo photoof ofthe theprototype, prototype,where where length, active componentsisisaround around56 56°C. Figure 16 16 shows shows the itsits length, width, and height are kW/m33..In width, and height are17.2, 17.2,14.6, 14.6,and and4.2 4.2cm cmininturn. turn.Therefore, Therefore,its itspower power density density is is 948.13 948.13 kW/m addition, the converter’s weight is 0.985 kg.kg. That is, is, specific power isis1.015 In addition, the converter’s weight is 0.985 That specific power 1.015kW/kg. kW/kg. 96 95 94 93 92 91 90 89 88

Step-Up Mode Step-Down Mode

100 200 300 400 500 600 700 800 900 1000 Power (W) Figure 15. bidirectionalDC-DC DC-DCconverter. converter. Figure 15.Measured Measuredefficiency efficiency of of the the proposed proposed bidirectional High-Voltage Side

Main Circuit

5.775 inches

Controller

E

90 89 88

Step-Up Mode Step-Down Mode

100 200 300 400 500 600 700 800 900 1000 Power (W) Energies 2017, 10, 296

Figure 15. Measured efficiency of the proposed bidirectional DC-DC converter. High-Voltage Side

20 of 23

5.775 inches

Main Circuit

Controller

Auxiliary Circuit

Low-Voltage Side

Figure 16. 16. The The photo photo of of the the experimental experimental setup. setup. Figure

Table summarizes comparison the proposed converter with other bidirectional Table 33summarizes thethe comparison of theofproposed converter with other bidirectional converters converters [24–27]. Theconverter proposed has converter has features the better features such asisolation, galvanicsoft isolation, soft in [24–27]. in The proposed the better such as galvanic switching switching at all switches, no any diode required, and high voltage-ratio conversion. For example, in at all switches, no any diode required, and high voltage-ratio conversion. For example, in step-up step-up mode and under the conditions that n = 3 and duty cycle is 0.5 (in addition, D 1 = D 3 in the mode and under the conditions that n = 3 and duty cycle is 0.5 (in addition, D1 = D3 in the proposed proposed theone proposed one can achieve a much higher upthose to 12inwhile those converter),converter), the proposed can achieve a much higher voltage gainvoltage up to 12gain while [24–27] are in [24–27] are 11, 3, 6, and 12, respectively. For clearer presentation, the plots to express the 11, 3, 6, and 12, respectively. For clearer presentation, the plots to express the comparison result among comparison result among are the shown mentioned converters are shown in Figure In high conversion ratio the mentioned converters in Figure 17. In high conversion ratio17. converters, current-sharing converters, current-sharing path structure with interleaved controland canthen suppress path structure along with interleaved controlalong can suppress current ripples lowers current current ripples and then lowers current stress and conduction loss [27–30]. However, bi-directional stress and conduction loss [27–30]. However, bi-directional power flow controlling or more power power flow controlling or more power components components needed are still their demerits. needed are still their demerits. Table 3. Performance Table 3. Performance comparisons comparisons of of proposed proposed BDC BDC with with other other bidirectional bidirectional DC-DC DC-DC converters converters proposed in [25–27]. proposed in [25–27]. References References Topology Topology ratio in Voltage conversion

[24] [24] Non-Isolated Non-Isolated [(1 + n)/(1 − D)] + n

[25] Isolated Isolated n [25]

[26] Isolated Isolated n/(1 − D) [26]

[27] [27] Isolated Isolated 2n/(1 − D)

Proposed Isolated Isolated [n(1 + D1 − D 3)]/[(1 − D1)(1 − D3)] Proposed

Voltage conversion ratio in step-up mode (VH /VL )

[(1 + n)/(1 − D)] + n

n

n/(1 − D)

2n/(1 − D)

[n(1 + D1 − D3 )]/[(1 − D1 )(1 − D3 )]

Voltage conversion ratio in step-down mode (VL /VH )

D/(1 + n + nD)

1/n

(1 − D)/n

(1 − D)/2n

(1 − D6 )2 /n 1 kW

Output power

200 W

500 W

1 kW

1.5 kW

Number of MOSFETs

5

8

4

8

6

Number of diodes

0

0

2

0

0

Number of inductors

0

1

1

0

1

Number of coupled inductors

1

1

1

2

1

Number of capacitors

3

1

4

5

4

Full-load efficiency (Step-up/step-down)

93%/90%

92.4%/91.7%

85%/89%

96.5%/95.8%

94.1%/91%

Number of diodes Number of inductors Number of coupled inductors Number of capacitors Full-load efficiency Energies 2017, 10, 296 (Step-up/step-down)

0 0

0 1

2 1

0 0

0 1

1

1

1

2

1

3

1

4

5

4

93%/90%

92.4%/91.7%

85%/89%

96.5%/95.8%

94.1%/91%

MStep-up

Proposed [25] [26] [27] [28]

120 100 Proposed

80

MStep-down

21 of 23

Proposed [25] [26] [27] [28]

0.33 0.30 0.25 0.20

60

0.15 40

0.10 20

0.05

3 0.4

Proposed 0.5

0.6

0.7

Duty cycle (D1)

(a)

0.8

0.9

1.0

0.4

0.45

0.5

0.55

0.6

0.65

0.7

Duty cycle (D6)

(b)

Figure Figure 17. 17. The Thecomparison comparison plots plots of of conversion conversion ratio: ratio: (a) (a)step-up step-up mode; mode; and and (b) (b) step-down step-down mode. mode.

5. Conclusions 5. Conclusions This paper has proposed a high efficiency and high voltage-ratio isolated bidirectional DC-DC This paper has proposed a high efficiency and high voltage-ratio isolated bidirectional DC-DC converter. A coupled inductor is employed for achieving galvanic isolation, in which the energy converter. A coupled inductor is employed for achieving galvanic isolation, in which the energy stored stored in leakage inductor can be recycled without additional components. The main contribution of in leakage inductor can be recycled without additional components. The main contribution of this this paper is that voltage stress across semiconductor devices can be lowered by adjusting duty ratio, paper is that voltage stress across semiconductor devices can be lowered by adjusting duty ratio, all all power switches can complete soft switching feature in step-up and step-down modes, and higher power switches can complete soft switching feature in step-up and step-down modes, and higher voltage conversion can inherently be achieved. Because semiconductor device endures low voltage voltage conversion can inherently be achieved. Because semiconductor device endures low voltage stress, MOSFETs with low Rds,on can be employed. Unlike conventional converters whose voltage stress, MOSFETs with low Rds ,on can be employed. Unlike conventional converters whose voltage gain gain is merely determined by a fixed duty ratio, the proposed converter has the ability of is merely determined by a fixed duty ratio, the proposed converter has the ability of compromising the compromising the duty ratios of switches at primary side to meet a certain voltage gain and to find duty ratios of switches at primary side to meet a certain voltage gain and to find an available power an available power component. Operation principle of the circuit and detailed derivation of voltage component. Operation principle of the circuit and detailed derivation of voltage gain, voltage stress, gain, voltage stress, and current stress are carried out. Finally, experimental results measured from a and current stress are carried out. Finally, experimental results measured from a 1-kW prototype have 1-kW prototype have verified the theoretical analysis and feasibility. verified the theoretical analysis and feasibility. Acknowledgments: Acknowledgments: The The authors authors would would like like to to convey convey their their appreciation appreciation for for grant grant support support from from the the Ministry Ministry of of Science and Technology (MOST) of Taiwan under its grant with Reference Number MOST 105-2221-E-327-038. Science and Technology (MOST) of Taiwan under its grant with Reference Number MOST 105-2221-E-327-038. Author Contributions: Chih-Lung Shen andand Cheng-Tao Tsai Tsai conceived and designed the circuit. Author Chih-LungShen, Shen,You-Sheng You-Sheng Shen Cheng-Tao conceived and designed the You-Sheng Shen and Cheng-Tao Tsai performed simulations, carried out the prototype, and analyzed with circuit. You-Sheng Shen and Cheng-Tao Tsai performed simulations, carried out the prototype, and data analyzed guidance from Chih-Lung Shen. Chih-Lung Shen revised the manuscript for submission. data with guidance from Chih-Lung Shen. Chih-Lung Shen revised the manuscript for submission. Conflicts of Interest: The authors declare no conflict of interest. Conflicts of Interest: The authors declare no conflict of interest.

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