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Dec 27, 2017 - Abstract—In this letter, a junctionless (JL) poly-Si thin- film transistor (TFT) with a 3-nm-thick nanosheet channel is successfully fabricated using ...
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IEEE ELECTRON DEVICE LETTERS, VOL. 39, NO. 1, JANUARY 2018

Junctionless Nanosheet (3 nm) Poly-Si TFT: Electrical Characteristics and Superior Positive Gate Bias Stress Reliability Jer-Yi Lin, Student Member, IEEE , Malkundi Puttaveerappa Vijay Kumar , and Tien-Sheng Chao

Abstract — In this letter, a junctionless (JL) poly-Si thinfilm transistor (TFT) with a 3-nm-thick nanosheet channel is successfully fabricated using the low-temperature atomic level etching process. An inversion-mode (IM) TFT is also prepared for performance comparison and reliability investigation of positive gate bias stress (PGBS). In comparison with the IM-TFT, the JL-TFT exhibits superior PGBS reliability. The origin of the difference in degradation rates between the JL and IM-TFTs is ascribed to the different transport mechanisms and different gate dielectric fields under the same gate over-drive stress. Nanosheet JL-TFTs with a 3-nm channel thickness show excellent S.S (69 mV/decade) and extremely low off-current (1.93 fA). Results indicate that it is a promising candidate for low-power 3-D integrated circuits. Index Terms — Junctionless (JL), inversion mode (IM), nanosheet, thin-film transistor (TFT), positive gate bias stress (PGBS).

I. I NTRODUCTION HIN-FILM transistors (TFTs) with poly-crystalline silicon (poly-Si) material are attracting a great deal of attention for application in monolithic three-dimensional integrated circuits (M3D-ICs) [1]–[3], owing to the feasibility of hetero-integration, easy stacking of the active region, and cost-effective fabrication. However, one of the challenges in M3D-ICs is the thermal budget, which degrades the performance of pre-existing devices as a result of lateral dopant diffusion. Fortunately, a heavily doped transistor, called a junctionless (JL) transistor, has been demonstrated [4], [5]. As its name suggests, it does not require a pn-junction. Therefore, dopant diffusion from the source/drain (S/D) to the channel is eliminated. As a result, JL transistors may serve devices in M3D integration. JL-TFTs that have been reported recently have ultra-thin body (UTB) [6]–[10] or nanowire architecture [11]–[13].

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Manuscript received November 13, 2017; revised November 25, 2017; accepted November 29, 2017. Date of publication December 4, 2017; date of current version December 27, 2017.This work was supported in part by the Ministry of Science and Technology, Taiwan, under Contract MOST_103-2221-E-009-182-MY3 and Contract MOST 1062633-E-009-001, and in part by the National Nano Device Laboratories, Taiwan, under Contract JDP 106-Y1-024. The review of this letter was arranged by Editor W. S. Wong. (Corresponding author: Tien-Sheng Chao.) The authors are with the Department of Electrophysics, National Chiao Tung University, Hsinchu 30010, Taiwan (e-mail: [email protected]). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2017.2779451

Compared with nanowire or FinFET, UTB devices have several advantages such as lower 3D parasitics and flexibility in width selection [14]. Moreover, reliability issues of JL devices have also been discussed in single-crystalline Si devices, particularly for hot carrier stress (HCS) of n-MOSFETs and negative bias temperature instability (NBTI) for p-MOSFETs [15]–[21]. Nevertheless, previous reliability studies on poly-Si TFT have mainly focused on the conventional inversion-mode TFTs (IM-TFT) [22]–[25]; it is meaningful to compare IM-TFTs with JL-TFTs for the reliability issue. As far as we know, there are no such correlative comparisons for these nanosheet TFTs. In this letter, poly-Si IM-TFT and JL-TFTs with a channel thickness (TCH ) of 7 nm and less than 7 nm are discussed for their electrical characteristics and positive gate bias stress (PGBS) instability. We demonstrate a novel method for the formation of a nanosheet channel, and explore the impact of PGBS on IM- and JL-TFTs. A JL-TFT with TCH = 3 nm exhibits a steep S.S. and extremely low off-current (IOFF ). The degradation mechanism of PGBS for both modes of these devices is proposed and discussed, and supported with TCAD simulations [26]. II. E XPERIMENT A 3D schematic and cross-sectional views of nanosheet TFT are shown in Fig. 1. The fabrication procedure of IM-TFT is identical to that of JL-TFTs, except for channel doping. First, a 120-nm-thick wet etching stop nitride layer (ESL) was deposited on an oxidized Si wafer using LPCVD. The buffer TEOS layer and amorphous-Si (a-Si) channel layer were then deposited using LPCVD with thicknesses of 45 nm and 16 nm, respectively. The a-Si channel layers for JL- and IM-TFT were deposited using in situ phosphorusdoped and undoped LPCVD, respectively. The doping concentration is 7 × 1019 cm−3 [6] for JL-TFT and 1 × 1010 cm−3 for IM-TFT. The thickness of the ultrathin channel is a critical requirement for better electrical characteristics of JL-TFT [10]. The thermal oxidation thinning method is conventionally used to form the thin poly-Si channel [9]. Even though JL devices can mitigate the thermal impact of source/drain diffusion, it is necessary to maintain the process temperature below 600 °C in order to preserve the performance of bottom-layer FET from any degradation [33]. Thus, a low- temperature process for poly-Si film thinning is necessary for application in M3D-IC. According to that, the nanosheet channel was thinned from

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LIN et al.: JL NANOSHEET (3 nm) POLY-Si TFT: ELECTRICAL CHARACTERISTICS AND SUPERIOR PGBS RELIABILITY

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Fig. 1. (a) 3D schematic of nanosheet poly-Si TFT and cross-sectional views along (b) the A–A cut-plane of the gate direction and (c) the B–B cut-plane of the channel direction.

a thickness of 16 nm to 7 nm for both JL- and IM-TFTs by utilizing a low-temperature atomic-level etching (LT-ALE) process, which may replace the conventional high-temperature oxidation thinning method. The LT-ALE is a wet etching process that uses ammonium hydroxide, hydrogen peroxide, and deionized water in a ratio of 1:4:20. It is the counterpart of industrial standard cleaning and also features a low etching rate of 0.7 nm/min, a low processing temperature of 75 °C, and excellent etching uniformity with near- degradation-free surface roughness. In addition to TCH = 7 nm, some samples of JL-TFTs were further shrunk to TCH = 5 nm and TCH = 3 nm using LT-ALE for better gate electrostatics. After the formation of the channel layer, a TEOS oxide hard mask was deposited and patterned as a channel region with a width of 500 nm. An n + a-Si layer of 100 nm for the raised S/D pad was then deposited. The samples were then annealed in an N2 ambient atmosphere at 600 °C for 24 hours to activate the doping impurities and transform the a-Si into poly-Si. The grain size in this work is estimated to be approximately 100 nm by means of SEM. After S/D pad formation, the oxide hard mask was removed by HF solution. Then, the TEOS gate oxide of 4 nm and n + poly-Si gate of 200 nm were deposited. After the gate formation, all devices were fabricated without the use of hydrogen-related plasma treatments. III. R ESULTS AND D ISCUSSION STEM and TEM images of the fabricated nanosheet JL-TFT with TCH = 7 nm and 3 nm are shown in Fig. 2. Figure 3(a) presents a comparison of the ID − VG characteristics on TFTs with different modes. It can be seen that with TCH = 7 nm, the S.S. is worse and VTH is more negative in JL-TFT, where the S.S. can be optimized through the adjustment of channel doping or channel thickness. VTH can be further tuned by using a gate material with a high workfunction for practical applications. As regards the TCH in JL devices, the channel can be fully depleted and turned off more efficiently with a decrease in TCH , as shown in Fig. 3(b). When TCH was thinned from 7 nm to 3 nm, the S.S. and IOFF of the JL-TFT can be improved from 173 mV/dec. to 69 mV/dec. and 550 fA to 1.93 fA, respectively. However, mobility degradation in the JL-TFT with a thinner TCH is ascribed to the higher S/D resistance from the smaller contact area of its S/D pad connected to the nanosheet. This issue can be resolved by changing the fabrication procedure for making the same contact area. Furthermore, VTH also shifts in a positive direction as TCH decreases, owing to the improvement

Fig. 2. STEM images of poly-Si nanosheet JL-TFTs for (a) TCH = 7 nm and (b) TCH = 3 nm, and TEM images for (c) TCH = 7 nm and (d) TCH = 3 nm.

Fig. 3. ID − VG transfer characteristics of (a) JL- and IM-TFTs with TCH = 7 nm and (b) JL-TFTs with TCH = 3 nm, 5 nm and 7 nm. All the devices were measured with VD = 0.1 V and the LCH is 300 nm.

in S.S. by the enhanced gate controllability and quantum mechanical effect [27]–[29]. Since the VTH of the JL-TFT with TCH = 3 nm is close to that of the IM-TFT with TCH = 7 nm, the following PGBS study is focused on these two devices. Figures 4(a) and (b) show the ID − VG transfer curves with different stress times (tstress) of IM- and JL-TFTs, respectively. A gate overdrive of 5 V (VOD = VG − VT = 5 V) was used to serve as a stress voltage (VG,stress) and the S/D was grounded to 0 V during PGBS. As tstress increased, VTH and S.S. gradually changed for both modes. Figure 4(c) shows the time-dependent degradation trend of the threshold voltage shift, VTH , where VTH is defined as (VTH,stress −VTH,initial). Figure 4(d) shows the time-dependent trend of S.S. degradation, S.S., which is defined as (S.S.stress − S.S.initial). The S.S. in poly-Si TFT is related to the deep-trap at the gate oxide/channel interface [22]. Significantly, the IM-TFT exhibits a severe S.S. degradation compared to JL-TFT. Because the conduction path of the JL device initially occurs at the center of an n + -doped channel, it can be less sensitive to the interface trap [30]. Therefore, the smaller S.S. degradation in JL-TFT leads to a smaller VTH shift, which is shown in Fig. 4(c). Nevertheless, VTH is not only affected by S.S. but also altered by the oxide trap charge. In order to further confirm the origin of the difference in degradation trend between the IM-TFT and the JL-TFT,

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IEEE ELECTRON DEVICE LETTERS, VOL. 39, NO. 1, JANUARY 2018

Fig. 6. Time-dependent degradation rates of (a) Gm and (b) ID extracted from Figs. 4(a) and (b) for the comparison of IM- and JL-TFTs.

Fig. 4. ID − VG transfer characteristics with different PGBS times for (a) IM-TFT and (b) JL-TFT and the VG,stress = VG − VT = 5 V. The time- dependent degradation trend of (c) VTH and (d) S.S. are extracted from (a) and (b) for the comparison of the IM and JL-TFTs.

Fig. 5. Simulated (a) energy band diagram and (b) electric field distribution across the gate oxide direction when VG,stress = 5 V is applied. The JL devices have channel thicknesses of 3 nm, 5 nm and 7 nm, respectively. The IM-device has a channel thickness of 7 nm.

the simulated energy band diagram and electric field (E-field) of these devices are shown in Fig. 5. Obviously, the IM device with TCH = 7 nm shows a larger E-field in the gate oxide as well as in the poly-Si channel, compared to the JL device with TCH = 7 nm. Moreover, the E-field is enhanced as TCH decreases which can be observed in JL devices due to increased gate controllability. It is worth noting that even with TCH = 3 nm, the E-field in the JL device is slightly smaller than in the IM device with TCH = 7 nm. On the basis of the different operating mechanisms, the different E-field in IM and JL device can be understood, and it can explained as follows. The IM device needs to attract inversion carriers by overcoming the flat-band situation in the off-state to the inversion situation in the on-state. In contrast, the JL device needs to squeeze conduction carriers from the flat-band situation in the on-state to the depletion situation in the off-state. Therefore, VFB (i.e., S = 0) is larger than VTH in the JL device and VTH is larger than VFB in the IM device. This implies that the relatively higher E-field occurs in the on-state for IM devices and appears in JL devices in the off-state. Consequently, JL-TFTs have a smaller E-field in the gate oxide as well as in the poly-Si channel during the on-state stressing, leading to smaller generation of interface

trap. In addition, fewer electrons can be injected from the poly-Si channel to the gate oxide, resulting in less oxide trap in the gate oxide. As a result, VTH is suppressed more in JL-TFTs, owing to the advantages of the lower E-field under the same VOD and bulk-transport in the sub-threshold region. We also studied the JL-TFT with TCH = 7 nm under the same PGBS conditions. Results revealed that PGBS instability can be further improved with a thicker TCH (data not shown here). Therefore, there is a trade-off between performance and reliability in terms of channel thickness for JL-TFTs. Figure 6(a) shows the time-dependent degradation trend of the transconductance (G m ). This degradation is associated with the tail-trap generation [22]. JL-TFT has a smaller degradation rate compared to IM-TFT which is shown in Fig. 6(a), owing to the lower E-field in the JL poly-Si channel during the PGBS. Therefore, fewer tail-traps are generated in JL-TFT. Figure 6(b) shows the ID degradation rate during PGBS, where the ID degradation rate is defined as [(ID,stress − ID,0 )/ID,0 ] % and ID is set as the drain current at VG = VOD = 2 V. The ID degradation rate at tstress = 2, 000 s is significantly degraded in IM-TFT and JL-TFT with values of 74% and 21%, respectively. However, the G m degradation rate is only 12% and 9% in IM- and JL-TFT, respectively. Hence, we may conclude that the ID degradation is mainly affected by VTH . The smaller sensitivity of G m after PGBS is ascribed to the quantum confinement effect, in which the density of state is restructured [31], [32]. Most of the carriers transport in the center of the channel, away from the interface in the on-state. Therefore, the influence of tail-traps is reduced. Overall, the results indicate that the JL-TFT exhibits better PGBS immunity than IM-TFT. IV. C ONCLUSIONS In this letter, poly-Si nanosheet TFTs were successfully fabricated using the LT-ALE process. For PGBS instability, the different degradation rates of VTH were explored. It was found that the tail-trap is less sensitive to ID degradation for both IM- and JL-TFTs. JL-TFTs exhibit a superior PGBS reliability compared to IM-TFTs, owing to the different operating principles in the on-state. In addition, nanosheet JL-TFTs show excellent electrical characteristics and better PGBS immunity, which makes them attractive for M3D-IC applications. ACKNOWLEDGMENTS The authors would like to thank Prof. C. Y. Ma, Prof. K. H. Kao, and Dr. P. Y. Kuo for helpful discussions. The authors are grateful to the National Center for High-Performance Computing and calculation resources.

LIN et al.: JL NANOSHEET (3 nm) POLY-Si TFT: ELECTRICAL CHARACTERISTICS AND SUPERIOR PGBS RELIABILITY

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