Lab Manual - 5th Semester

DEPARTMENT OF ELECTRICAL ENGINEERING Bengal Engineering & Science University, Shibpur, Howrah - 711 103.

Circuits Laboratory Solid State Devices & Control System Laboratory Sessional(EE-552) CLASS:

Third Year (5thSem) EE

Date: Expt. No.:

EE552 – S/1a

TITLE OF EXPERIMENT: OBJECT:

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STUDY ON CHARACTERISTICS OF DIODES

To study and plot the forward and reverse VI-characteristics of : (i)

Silicon diode, (ii) Germanium diode & (iii) Zener diodes

REFERENCE: [1] MILLMAN & HALKIAS [2] Y. BAPAT

- Integrated Electronics. - Electronic Devices and Circuits.

APPARATUS: (i) PN Junction Diode Characteristic Trainer Kit , (iii) DC ammeters 0-10mA and 0-100A range (v) C.R.O. (vi) Patch cords etc.

(ii) Zener Diode Characteristic Trainer kit (iv) DC voltmeters 0-1V and 0-10V range (vii) Various types of diodes/ zeners.

PROCEDURE: Step -A. Identify the anode and cathode terminals of the diodes and zener diodes as mounted on the test board. Step -B. Study of Forward Characteristics 1. Switch 'on' the power supply and check the DC source voltage, i.e., 0 to 12V continuously variable. 2. Set the voltage potentiometer ( P1 ) in the minimum position and connect the built in DC source to the input terminals of first circuit ( Fig-1 ) to find forward characteristics. 3. Adjust the input voltage gradually in small incremental steps as shown in Table -1 and measure the forward voltage drop across the diode, Vd and forward current Id to the diode and note down these values in Table - I. 4. Repeat steps 2 and 3 for other diodes (DR25/ 1N4007 / BY127) and zener diodes of different voltage ratings (3.9V /5.1V /8.1 V) also. Step -C. Study of Reverse Characteristics 1. To draw Reverse Characteristics connect the circuit diagram as shown in Fig - 2. 2. Adjust the input voltage in incremental steps as shown in Table -2 and measure the Reverse voltage drop across the diode, VR and Reverse current IR through the diode and note down these values in Table - 2. Use A range for diodes and mA range for zener reverse characteristics. 3. Repeat the step 2 for other diodes and zener diodes also.

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REPORT: 1.

Draw the graphs to compare the Forward and Reverse characteristics of all types of diodes and zener diodes used.

Vd from table – I. Id Vd 3. Compute dynamic Forward Resistance rac  from the graph. I d 2.

Compute static Forward Resistance

rdc 

Fig. 1. Diode/Zener Forward Characteristics

Fig. 2. Diode/Zener Reverse Characteristics Table – I Voltage across Sl.No. Diode/ Zener Vd (Volts) 1 2 3 4 5 6 7 8

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0.0V 0.1V 0.2V 0.3V 0.4V 0.5V 0.6V 0.7V

Table - II Forward current Id (mA)

Reverse Voltage Reverse current Sl. No. across diode/ zener, IR (A/mA) VR (Volts) 1 2 3 4 5 6 7 8 9 10 11 12 13

0.0V 1.0V 2.0V 3.0V 4.0V* 5.0V 6.0V 7.0V 8.0V 9.0V 10.0V 11.0V 12.0V




Date: Expt. No.:

EE552 – S/1b

TITLE OF EXPERIMENT:

OBJECT:

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NAME:

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Co-Workers:

STUDY ON CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTOR (BJT)

(i) To study and plot the input, output and transfer characteristics of a BJT (NPN/PNP) in different configurations. (ii) To find the input impedance, forward current gain, output admittance, reverse voltage gain from the plotted curve.

REFERENCE: [1] MILLMAN & HALKIAS [2] Y. BAPAT

APPARATUS: (i) BJT Trainer Kit , (iii) Patch cords etc. (v) C. R. O.

- Integrated Electronics. - Electronic Devices and Circuits.

(ii) DC voltmeters/DMM, 0-1 V and 0-10V range (iv) DC ammeters 0-10mA and 0-100A range, (vi) Various types of transistors. (CL100/ CK100/ BC107 etc.)

THEORY: A transistor model consists of two junctions. The aim of the experiment is to study the V-I characteristics of a transistor in CE, CB and CC configurations. For this the transistor is considered as a 2-port network. For a transistor to operate in the active region the collector-base has to be reversebiased and the emitter has to be forward-biased. Figure below shows an n-p-n transistor with proper biasing and input/output ports in common emitter (CE) configuration. The V-I (input/output/transfer) characteristics are obtained as listed in the procedure. Precaution: 1. Before switching on correct polarities of dc supply connection are to be ascertained. 2. Check the ranges of the meters used. 3. All the connections shown here are for npn transistor. For pnp, the polarity of VBB and VCC supply have to be reversed in each configuration. CIRCUIT DIAGRAM

PROCEDURE: (a) Output characteristics (IC vs VCE with 1B as parameter)

1. Connect VBB and VCC with proper polarity as shown in figure. Connect micro-ammeter in the base circuit.

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2. Connect 0-10V dc voltmeter across the collector and emitter and a milliammeter in collector circuit. Set VCC so that VCE =0. 3. Set some value of base current (say 5A by adjusting VBB). Change VCC to set VCE at 1V, 2V, 3V etc. in steps of 1V and note down IC in each step. 4. Repeat step 3 for different settings of IB at intervals of 10A. Tabulate the results as shown in Table-I. (b) Transfer Characteristics (IC vs IB with VCE as parameter) 1.

Repeat steps 1-2 above

2.

Set VCE = 2V by VCC control. Keeping VCE constant, change IB from . to 50A in steps of 5A and note

corresponding values of IC. Repeat step 2 for different settings of VCE ( say 5V & 10V). Tabulate the result in Table-II.

3.

(c) Input characteristics (IB vs VBE with VCE as parameter)

SI. No. 1. 2. 3. 4. 5. 6.

1.

Repeat step 1 of (a).

2.

Connect a dc voltmeter 0-1V to measure VBE & connect a 0-10V dc voltmeter to measure VCE; there is no need for measuring IC.

3.

Set VCE =0V by VCC control. Keeping VCE constant, vary VBE (through VBB control) in steps of 0.1 V and note IB IB for each value of VBE. Tabulate the results in table-III.

4.

Repeat step 3 for VCE =5V and 10V.

Table –I: Output Characteristics IB = 0 A IB = 10A IB = 20A VCE volts IC (mA) VBE(mV) IC (mA) VBE(mV) IC (mA) VBE(mV) 0 1 2 3 .. 12

Table –II: Transfer Characteristics VCE = 2V VCE = 5V VCE = 10V IB in SI. No. A IC (mA) IC (mA) IC (mA) 1. 2. 3. 4. 5. 6.

SI. No. 1. 2. 3. 4. 5. 6.

Table –III: Input Characteristics VCE = 5V VCE = 0V VBE volts IB (A) IB (A)

0 5 10 15 20 .. VCE = 10V IB (20A)

0.0 0.1 0.2 0.3 .. ..

REPORT: 1. Plot all the characteristics curves obtained so far. 2. Compute from graph:

3. How will you change the circuit for CB and CC configurations? 4. What are the main application areas of each configuration? 5. Why CE configuration is the most commonly used one? 6. How will you change the circuit to test pnp-transistors? as07/07




Date: Expt. No.:

EE552 – S/2a

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TITLE OF EXPERIMENT: FAMILIARISATION WITH OP-AMP CIRCUITS OBJECT:

To study the linear applications of the Operational Amplifiers as : (i) A voltage follower; (ii) An Amplifier; (iii) An Adder; (iv) A subtractor; (v) An Integrator and (vi) An Adder-cum-Integrator.

REFERENCE: [1] Clayton [2] Gaykwad R.

- Operational Amplifiers. - Theory and Applications of Linear Integrated Circuits

PREAMBLE: OP-AMP is nothing but a high gain direct-coupled amplifier, widely used for analogue computation, control and instrumentation circuits. A typical general purpose operational amplifier is LM741 with offset-voltage null adjustment facility. Different pin configurations of the I.C. are shown in figures 1 (a), (b) and (c).

Fig. 1: Top views of different type of IC LM741.

If the output voltage is fed back to the inverting input terminal as negative feedback, and the input signal is applied to the non-inverting terminal, the circuit finds application as a voltage follower (unity gain buffer); Vo = Vi; with very high input impedance and low output impedance (Fig. 2). The Op-Amp connected in a circuit with an input resistance R1 and feedback resistance R2, as shown in Fig.3, will act as an amplifier whose voltage gain will be (-R2/ R1), the gain can be varied either by varying the value of R2 keeping R1 fixed or by varying R1 keeping R2 constant. This is the Inverting amplifier configuration. The circuit of Fig. 4 shows the Non-inverting amplifier configuration featuring a high input impedance and low output impedance with a positive gain of (1 + R2/ R1).

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If the op-amp is provided with two inputs as shown in Fig.5, an Adder circuit, the output will be given by Vo    R3 V1  R3 V2  .   R2   R1

Fig.6 shows the Subtractor circuit, where the output signal is related to the input signals as: R2  R  R2  R4 R2 Vo    1  V2  V1 for R1  R2 and R3  R4, Vo  R (V2  V1 ). R1 1  R3  R4  R1 OP-AMPs can be used as an Integrator with a resistive input and capacitive feedback (Fig. 7). Using more than one input, the circuit of Fig.8 will integrate the sum of the input voltages (Adder-cumintegrator).

APPARATUS: (Make a table indicating Item, Type/Model, Make, SI.ILab No.) 1. Experimental setup for OP-AMP 741. 3. VTVM or AVO

2. 12 V d.c. regulated power supply. 4. Stopwatch.

5. C.R.O.

PROCEDURE: 1. Study the layout of the setup. 2. Connect as in fig.2 and apply the 12 V dc from a regulated power supply unit. 3. Make the following observations and results for various d.c. signals with different circuit components as you are given. (TABLE-I). 4. Repeat the steps (1) to (3) for the circuits of Fig.3 to fig.6. 5. Connect the op-amp as an integrator (Fig.7). Follow the steps (1) and (2) and complete the observation table (Table-2). 6. Connect the op-amp as an adder-cum-integrator (fig.8) and follow the steps (1), (2) and (5). Table - I Ref. Circuit (Fig. No.)

Obs. No.

Input Resistances

Feedback Resistances

Ref. Circuit (Fig. No.)

Obs. No.

Input Resistances

Feedback Capacitance

Vin

Vout

Gain Theo.

Expt.

Table - II Input voltage{s), Vin

Time required to reach 10 volts (at the output)

REPORT: 1. Calculate the gain of each circuit and compare with its theoretical value. 2. Describe 741 IC with its pin diagrams (see Reference) and the uses of offset-null control terminals of this IC. as07/07




Date: Expt. No.:

EE552 – S/2b

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TITLE OF EXPERIMENT: APPLICATION OF OPERATIONAL AMPLIFIERS OBJECT:

a) To study the input/output characteristics (Dynamic characteristics) of some non-linear applications of Op-Amps as follows: (i) Limiter circuits (ii) Comparators

: Feedback limiter – Symmetrical and asymmetrical; : Zero crossing detector, Comparator with hysteresis. (Schmitt trigger) b) To study the applications an Operational Amplifier as: (i) Multivibrators

: - Astable (Square wave oscillator) ; - Monostable;

(ii) Signal Generators : - Triangle and Square wave output; - Sine wave output (Wein Bridge Oscillator) REFERENCE: [1] Clayton [2] Tobey, Graeme & Huelsman [3] Gaykwad R. -

Operational Amplifiers. Operational Amplifier – Design & Applications. Linear Integrated Circuits

LIST OF APPARATUS & EQUIPMENT: Prepare a List of apparatus and equipment in a tabular form showing Sr. No., Item, Type/Model, Specification/ Range, Make, Lab. No. etc. (1) Experimental set-up (Patch panel) with Op-amp 741. (3) Dual Trace C.R.O. (4) Multimeter

(2) +/-12 d.c. regulated power supply. (5) Function Generator.

PROCEDURE & OBSERVATIONS: 1. Study the set up - PATCH PANNEL. 2. Connect as shown in Fig.1(a) and apply a variable dc signal from a potential divider arrangement to study the output of a symmetrical Feed-back limiter circuit. Repeat the same for asymmetrical limiter circuit of Fig. 1(b). 3. Connect and study the characteristics of the Zero-Crossing-Detector of Fig. 2(a) and the Comparator with Hysteresis of Fig. 2(b). 4. To get the dynamic characteristics of these circuits, feed the circuit from a function generator by a sine wave (or triangle wave) signal 5V p-p. Connect the same signal to the X-input of CRO through a potential divider and connect the output of the 'circuit' under test to the Y-input of the CRO. Adjust the peak value and dc offset of the input signal (through potential divider) and that of Y-amplifier of the CRO to have a display on the screen in X-Y mode, which is the I/O (Transfer) characteristics of the system under test (Fig. 3). 5. Build the respective multivibrator and oscillator circuits (Fig. 4 to 7) on patch panel and note the values of resistors and capacitances used. 6. Observe the output response on the CRO and Measure the magnitude, time period and frequency etc. for different values of resistances. Trace the oscillograms.

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REPORT: (1) (2) (3) (4)

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Draw the relevant circuit diagrams and output characteristics and waveforms. Plot the I/O characteristics on a graph paper. Compare the values, obtained experimentally with the calculated (theoretical) values. Write the operating principle of different oscillators




Date: Expt. No.:

EE552 – S/3a

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TITLE OF EXPERIMENT: STUDIES ON LOGIC FAMILIES OBJECT:

To observe the transfer characteristics of TTL & CMOS families and to find out logical 'low' and 'high' level voltages under worst case, transition region and threshold voltage.

REFERENCE: [1] TTL / CMOS DATA BOOKs

[2] MORRIS & MILLER [3] BARTEE [4] TAUB & SCHILLING

- National Semiconductors / Texas Instruments/ Fairchild Semiconductors / BEL - Design with TTL Integrated Circuits. (pp.23-27). - Digital Computer Fundamentals (pp.203-218). - Digital Integrated Electronics (pp.217 -265).

INTRODUCTION: In digital computers, control and/or instrumentation circuits, the decimal system is replaced by binary system with only two levels of voltages (LOW i.e. '0' and HIGH i.e. '1'). A series of decisions, necessary to obtain the logical answer to a problem having a given set of conditions, etc. is made by logic circuits called "GATES" (e.g. AND, OR, NOT, NAND, NOR, etc.). The gates of the Logic systems are realized with various electronic circuits called LOGIC FAMILIES. The two most widely used circuits available as IC chips are TTL (Transistor Transistor Logic) family and CMOS (Complementary Metal-Oxide Semiconductor) family. APPARATUS & EXCPERIMENTAL SETUP: (i) Circuit blocks (patch panels for TTL & CMOS Gates); (ii) 5V d.c. regulated power supply; (iii) VTVM/ DVM/ CRO; (iv) Equivalent loads & Potentiometer; (v) Sine or Triangle wave Generator. PROCEDURE & REPORT: METHOD-I: Static Characteristics. ( Ref: Fig.1)

1.

Trace the circuit of the setup for TTL and note the values of the components.

2.

Connect the supply voltage of d.c. 5V (regulated)

3. Connect potentiometer fed from the 5V d.c. source, to one of the inputs of the gate and plot the static input vs. output voltage characteristics with the values obtained from VTVM/DVM. 4. Repeat (3) by connecting equivalent of 10-gate loads (a series combination of a resistance and a diode). 5. Draw the transfer characteristics for (3) and (4) above and then calculate the threshold voltage, transition width, worst case 'low' and 'high' level voltages. 6. Repeat the procedure (1) - (5) for the CMOS gate also.

552/S3a .. p2of2 METHOD- II: Dynamic characteristics.( Ref: Fig.2)

1. Connect the output of a Triangle wave generator to the inverting gate (say TTL) as shown in Fig.2. 2. Observe the input and output waveforms of the gate through CRO. 3. Note the input and output voltages at same instants from 'high' to 'low' travel of input and draw the characteristics. 4. To display the Input-Output characteristic on the CRO as Lissa'jouass pattern, connect the CRO in X- Y mode. 5. Repeat the procedure (1) - (4) for the CMOS gate also.

PIN DIAGRAM of: 7404 – TTL Hex Inverter 74C04 – CMOS Hex Inverter CD4069 – CMOS Hex Inverter

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PIN DIAGRAM of: CD4069 – CMOS Hex Inverter (Connect Vcc with Vdd for this Chip)




Date: Expt. No.:

EE552 – S/3b

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TITLE OF EXPERIMENT: STUDY ON COMBINATIONAL LOGIC CIRCUITS OBJECT:

(a) To study the operations and to verify the truth tables of the TTL gates. (b) To be familiarized with the Applications of Logic Gates in different combinational (combinatorial) Circuits.

REFERENCE: [1] [2] [3] [4] [5]

TTL DATA BOOK- National Semiconductors/Texas Instruments/Fairchild/BEL. MALVINO & LEACH Digital Principles & Applications. MALVINODigital Computer Electronics. LEEDigital Circuits and Logic Design. MORRIS & MILLERDesign with TTL Integrated Circuits.

INTRODUCTION: In digital electronics a logic circuit or a gate circuit is one, which has one output and one or more input channels. The signals to the channels are either LOW (logic-0) or HIGH (logic-1) states. The output signal occurs only for certain combination(s) of input signals. A combinational logic circuit is one in which the output(s) obtained from the circuit is solely dependent on the present state of the inputs. The basic gate circuits are NOT (or Inverter), OR and AND gates. Suitable modifications of these gate circuits yield to NOR, NAND, EXOR and EXNOR using variety of circuit elements e.g., diodes, resistors, transistors, etc. Usually these are all available in the form of integrated circuits (I.C.chips) using different combinations of the passive or active devices. One of these combinations is Transistor-Transistor-Logic (TTL) family and this has clearly achieved popularity because of its versatile, economic and reliable uses. NOR and NAND gates are called UNIVERSAL gates. LIST OF APPARATUS & EQUIPMENT: Prepare a List of apparatus and equipment in a tabular form showing Sr. No., Item, Type/Model, Specification/ Range, Make, Lab. No. etc. (i) Patch Panel Set-up or Logic Trainer (iii) 5V dc Regulated Power supply

(ii) TTL ICs (74' series basic gates) (iv) Multimeter /Logic Probe.

PROCEDURE & OBSERVATIONS: 1. Study the set up carefully. 2. Identity the input output terminals inside the Integrated Circuits of following types. Using the regulated 5V dc supply, operate the circuit and verify the TRUTH TABLES (using POSITIVE LOGIC) of the gates. 7400 - Quad 2-in NAND; 7404 - Hex Inverter (NOT);

7402 - Quad 2-in NOR; 7486 - Quad 2-in EXOR Gates

(The Status Switches and the LED's may be used for input and output indications respectively. Also measure the supply voltage (Vcc) and input & output voltages representing HIGH (1) and LOW(0) Logic states)

3. Design each of the following Combinational Logic circuits with the available gates and verify the operations with the help of TRUTH TABLES. a) Simulation of EXOR gate using 7400. b) Majority Circuit. c) Half Adder d) Full Adder/Subtracter e) Word Comparator f) Parity Bit Generator/Checker (EVEN/ODD) g) 2-line to 4-line Decoder

Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. (also realize using universal gates only) Fig. 6. Fig. 7.

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REPORT: (1) Draw the Pin diagram of each IC and the circuit diagram for each test; write down the logic expressions; prepare the Truth Tables. (2) Draw and explain the operation of a Code Converter (e.g., Binary to Gray /Gray to Binary) (3) Design the minimum combinational circuit to realise an output from BCD input to drive any one segment of a common-anode type seven-segment LED display with the help of Karnough-map. (4) Draw the circuit diagrams of a 3-bit MULTIPLEXER & DEMULTIPLEXER.

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Date: Expt. No.:

EE552–S/4a

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TITLE OF EXPERIMENT: STUDY ON FLIP FLOPS & LATCHES OBJECT:

To be familiarized with applications of the Universal gates as Latches and Flip-Flops.

REFERENCE: [1] [2] [3] [4] [5]

TTL DATA BOOK- National Semiconductors/Texas Instruments/Fairchild/BEL. MALVINODigital Computer Electronics. GOTHMAN Digital Electronics. BARTEE Digital Computer Fundamentals. MORRIS & MILLERDesign with TTL Integrated Circuits.

INTRODUCTION: A device that exhibits two different stable states is known as a bi-stable multivibrator or a Flip Flop (F/F) and is extremely useful as a memory element, register, counter, etc. Flip Flops are classified in the following sub-groups. (i)

R-S F/F. (ii) T F/F, (iii) Clocked R-S or RST F/F, (iv) D F/F and (v) J-K Flip Flop.

A logic circuit is called sequential one, where the output is a function of both the present and past inputs. There are two main classes of sequential circuits - synchronous (clocked or strobed) and asynchronous (unclocked or free running). LIST OF APPARATUS & EQUIPMENT: Prepare a List of apparatus and equipment in a tabular form showing Sr. No., Item, Type/Model, Specification/ Range, Make, Lab. No. etc. (i) (ii)

PATCH PANNEL or Logic Trainer TTL IC's (74' series Basic Gates and flip-flops). (iii) 5V dc regulated power supply.

PROCEDURE & OBSERVATIONS: 1. Study the set up and connect the regulated power supply of 5V dc to it. 2. Connect the two NAND gates of 7400 as a flip-flop or LATCH (Fig. 1) (i) Study the operation of the circuit step by step - as for example, for the NAND latch, study the outputs (Table-I) as follows: First inputs 00, then 01, 10, 00, 10, 11, 01, 00 and so on. (ii) Use this NAND Latch circuit as a contact-debouncer (Fig.-1b) for the micro-switch to be used as a manual clock pulse generator. 3. Study the following Flip-Flop IC's and observe their performances using truth-tables, timing waveforms, sequence diagrams etc. (see Excitation Function, Transition Table etc. in Appendix). 7474 - Dual D-F/F with preset & Clear ** 7476 - Dual JK-F/F with preset & Clear ** 4. Connect the flip-flops (7474 and/or 7476) as follows and observe the performance of Interchanging the Flip-Flops using truth tables/ transition tables (Fig. 2). Interchange the following: (i) D to T only

(ii) D to T with T- data

(iii) J-K to D

(iv) J-K to T.

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REPORT: (1) Draw the relevant circuit diagrams, Truth Tables, timing diagram, waveforms etc. for the tests.

** TRUTH TABLES FOR PRESET(SET) & CLEAR(RESET) of IC 7474 & 7476 . (STANDARD Notations & Terminology followed)

Circuit Diagrams




Date: Expt. No.:

EE552 – S/4b

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TITLE OF EXPERIMENT: STUDY ON SEQUENTIAL LOGIC CIRCUITS OBJECT:

To be familiarized with applications of the flip-flops in different sequential circuits.

REFERENCE: [1] [2] [3] [4] [5]

TTL DATA BOOK- National Semiconductors/Texas Instruments/Fairchild/BEL. MALVINODigital Computer Electronics. GOTHMAN Digital Electronics. BARTEE Digital Computer Fundamentals. MORRIS & MILLERDesign with TTL Integrated Circuits.

INTRODUCTION: A device that exhibits two different stable states is known as a bi-stable multi vibrator or a flipflop (F/F) and is extremely useful as a memory element, register, counter, etc. A logic circuit is called sequential one, where the output is a function of both the present inputs and past states. There are two main classes of sequential circuits - synchronous (when all the F/Fs are clocked synchronously) and asynchronous (unclocked or free running i.e no simultaneous clocking). LIST OF APPARATUS & EQUIPMENT: Prepare a List of apparatus and equipment in a tabular form showing Sr. No., Item, Type/Model, Specification/ Range, Make, Lab. No. etc. (i) (ii)

PATCH PANNEL or Logic Trainer TTL IC's (74' series Basic Gates and flip-flops). (iii) 5V dc regulated power supply.

PROCEDURE & OBSERVATIONS: 1. Study the set up and connect the regulated 5V dc supply to it. 2. Keep the contact de-bouncer circuit used in the previous experiment for the micro-switch to be used as a manual clock pulse generator. 3. Study the following Flip-Flop IC's and observe their performances using truth-tables, timing diagrams, sequence diagrams etc. (see Excitation Function, Transition Table etc. in Appendix). 7474 - Dual D -F/F with preset & Clear ** 7476 - Dual JK-F/F with preset & Clear ** 4. Connect the flip-flops (7474 and/or 7476) as follows and observe their performance using truth tables, transition tables: a) Buffer Register & Shift Register.(Fig. 1) b) Simple counter (Fig. 2) (i) 4-bit Ring Counter. (iii) 2-bit Ripple counter

(ii) 4-bit Johnson Counter (iv) 2-bit Synchronous Counter

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REPORT: (1) (2) (3) (4)

Draw the relevant circuit diagrams, Truth Tables waveforms etc. for the tests. What are the functional differences between ripple counter and synchronous counter? Write a short note on the design of a BCD counter. Give an application of shift register.

** TRUTH TABLES FOR PRESET(SET) & CLEAR(RESET) of IC 7474 & 7476 . (STANDARD Notations & Terminology followed) Circuit Diagrams

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Circuit Diagrams:

Fig.1. Simple SHIFT Register (4-bit, Left Shift), SIPO

Fig.2. Simple Counters

DEPARTMENT OF ELECTRICAL ENGINEERING BENGAL ENGINEERING AND SCIENCE UNIVERSITY, SHIBPUR Solid State Devices & Control System Laboratory Sessional(EE-552) 5th Semester Electrical

Control System Laboratory EXPERIMENT. No. EE552-C/1.

I. Title : TRANSIENT AND FREQUENCY RESPONSE OF A R-L-C SERIES CIRCUIT II. Objective : To be familiar with : 1. Transient response of an R-L-C series circuit excited by a step input. 2. Frequency response of an R-L-C series circuit III. Theory: System Description : A second order system is realised by R-L-C series circuit. The resistance can be adjusted to set different damping ratio ( ξ ). Output of an astable multivibrator provides the step input to this system. The High-Low period of the astable output is so designed that the High period is sufficiently large to allow the transient to settle down completely. (In this way the ON period output serves the purpose of a step input). The system is initialized in the Low period. A variable frequency sine-wave oscillator is used to provide constant amplitude sinusoidal excitation to study the frequency response of the system. The values of R1, R2 & R3 are equal to 95 ohms, 564 ohms, 975 ohms respectively. The value of the Capacitance is equal to 0.1 μ F The value of the Inductance is equal to 10 mH. IV. Experiments: 1. Transient Response : 1.1 Procedure : I). All the components are already connected internally and the input is also connected internally to these components. An external connector will only bypass (short) a particular element. II). Set the toggle switch to step input. III). With all the resistances R1, R2 and R3 present, switch on the power supply. Observe the voltage (response) across the capacitance in a CRO. Observe the input excitation. If needed, adjust the frequency adjustment knob to adjust the ON time of the square wave in such a way that the transient response settles completely. IV). Trace the response from the CRO. Measure the following quantities (whichever is possible) directly from the CRO. a) Delay time, td b) Rise time, tr c) Peak time, tp d) Maximum overshoot, Mp e) Setting time, ts . V) Repeat step IV) keeping only R1 & R2 in the circuit and calculate the transient response parameters. Trace the response. IV) Repeat step IV) keeping only R1. Calculate the transient response parameters and trace the response. 1 of 2

1.2 Report : I) Draw the circuit diagram given on the Laboratory-apparatus. II)Calculate theoretically the transient response parameters for different combinations of R1,R2 & R3. III) Compare theoretical and experimental values for the underdamped case only. 2. Frequency Response : 2.1: Procedure : I). Keep R1 in the circuit alone (by connecting a shorting link across R2 & R3). Connect the input and output to two channels of the CRO and adjust voltage scale of the two channels to the same value. Vary the frequency of the input signal by the frequency adjustment knob. Note the change in amplitude of the output. Comment on your findings. Fill up Table I. II). Keeping R1 in circuit adjust the frequency to lowest value, say, f1 = 1 kHz. Take gain and phase difference readings. Now include R1 & R2 in circuit (by adjusting the shorting link) and take readings at same frequency f1. Include R1, R2 & R3 in circuit and take readings at f1. III). Repeat step 2 for other higher frequencies 5, 6, 8 and 10 kHz, approx. Set the highest frequency in such a way that the gain with R1 in circuit reduces to 10 db. Sl No

Freq.

Under damped Gain Phase (abs)

(db)

Table I Critically damped Gain Phase (abs)

(db)

Over damped Gain Phase (abs)

(db)

2.2. Report : On a single semilog graph paper plot both i) gain vs. frequency and ii) phase angle vs. frequency for different combination of R1,R2 & R3 in the same graph paper. 4.Apparatus Required : a) Oscilloscope. b) laboratory setup V. References: 1. Modern Control Systems – K. Ogata 2 of 2

DEPARTMENT OF ELECTRICAL ENGINEERING BENGAL ENGINEERING AND SCIENCE UNIVERSITY, SHIBPUR Solid State Devices & Control System Laboratory Sessional(EE-552) 5th Semester Electrical

Control System Laboratory EXPERIMENT. No. EE552-C/2 I. TITLE: DESIGN OF PID CONTROLLERS

II. OBJECTIVE: To learn how to design PID controllers A. based on Zeigler-Nichols tuning rules for second order plants with time delay B. for a third order unstable plant using simulation techniques. Part A Design of PID Controllers using Ziegler-Nichols Method IIIa. EXPERIMENTAL UNIT: The laboratory apparatus, “PID CONTROLLER”, consists of (i) a plant, (ii) a controller, (iii) an error detector, (iv) an amplifier and (v) signal sources. Each of them is realized using OPAMP’s and is described below. (i) Plant or Process: There are basic building blocks which may be connected suitably to from different processes or systems. The blocks are: (a) Integrator: Having an approximate transfer function of 10/s. (b) Simple pole: Two identical units, each having a transfer function of 1/ (1+0.0155s) (c) Pure time delay: A time delay of about 5.64 millisecond All the above blocks, except the pure time delay, have 180° phase shift between input and output (-1 gain to be included each time). (ii) Controller: The controller is an analogue proportional-integral-derivative (PID) circuit in which the P, I, and D parameters are adjustable. The values may be set within the following ranges through 10 turn calibrated potentiometers. Proportional Gain, Kc : 0 to 20 Integral time constant, Ti : 5 to 100 msec, thus the integral constant Ki : 0 to 1000 Derivative time constant, Td : 0 to 20msec, thus the derivative constant Kd : 0 to 0.01 The PID block has a phase angle of zero degree between its input and output. (iii) Error Detector: The error detector is a unity gain inverting adder which adds the reference signal with the feedback signal. To ensure negative feedback it would therefore be necessary to have (2n+1)π phase shift in the forward path, for n=0,1,2….. (iv) Amplifier: It is a unity gain inverting amplifier (gain = -1). This may be inserted in the loop, if required to ensure a proper phase between the input and the output. (v) Signal Sources: The signal source comprises of a low frequency square and triangular wave generator having adjustable amplitude and frequency. The square wave is used as a reference signal to the system. Power Supply and DVM:. A 3.5 digit DVM of (+19.19 to -19.19) volt range is mounted on the panel and may be used for d.c. measurements. Also a variable d.c. in the range (+1 to -1) volt (min) available on the panel may be used as a d.c. input or set point. 1 of 8

IVa. THEORY: T The transfer t func ction of a PID D controller is i given by: ………… ………………… ……………………………… ………….(1) ……………… ……………………………… ………………… …..(2)

The above a contro oller is usua ally attached in the forwa ard path in cascade c with h the plant as a show wn in Fig. A. Controlle er K(s)

Pllant G G(s)

Fig. A Block B Diagra am of a Close ed Loop Systtem

Ziegle er and Nicho ols [1] proposed rules for f determiniing values of the proporttional gain Kp integral time Ti , and derivatiive time Td , based on th he transient response characteristiccs of a given g plant. There are two t methods called Zie egler-Nicholss tuning rule es: (i) the firsst method and (ii) th he second method. m (i) First Method or Process s Reaction Curve Metthod: In thiss method, we w first obtaiin experimentally th he response e of the ope en loop plan nt to a unit--step input, as shown in i Figurre 1. If the plant p involves a time dellay but neith her integrato or nor domin nant complexxconju ugate poles,, then a un nit-step resp ponse curve e may look S-shaped, as shown in i Figurre 2.This me ethod appliess if the respo onse to a ste ep input exhibits an S-sh haped curve.

The S-shaped S cu urve is charracterized byy two constants, (Fig. 2) 2 delay time L and tim me consttant T. Thes se are deterrmined by drrawing a tan ngent line at the inflection point of th he S-sha aped curve and determining the inttersections of o the tangent line with the time axis and line c(t) = K, K as show wn in Fig. 2. The transfer function C(s)/U(s) may m then be b appro oximated by a first-orderr system with h a transporrt lag as follo ows: 2 of 8

Ziegle er and Nicho ols suggeste ed to set the values of Kp, Ti, and Td according to t the formu ula shown in n Table 1. TABLE 1: Ziegler-Nich Z hols Tuning g Rule Base ed on Step Response R o Plant of pe of Controller Typ P PI PID

Kp T/L 0.9(T/L) 1.2(T/L)

Ti ∞ L/0.3 2L

Td 0 0 0.5L

IVa. PROCEDUR P RE: (To dessign a PID co ontroller for a 2nd order system s with a time delayy) 1. On the PID P CONTRO OLLER setu up, connect the blocks: a time dela ay along witth two time constants to t make an open loop plant (Figu ure 3). The PID block is bypassed d by setting g integral constant c and d derivative e constant as a zero an nd proportion nal constant as one. The e connection n diagram is as shown in n Figure 4. 2. Connect the t input to channel 1 and a the output to channe el 2 of the CRO C to obtaiin the step response. r 3. Trace the e response. Select an inflection po oint in the liinear region n and draw a tangent th hrough it. (A A typical natu ure of the experimental curve c is give en in Fig. 5.) 4. Determine e the param meters L and d T by exten nding the tangent to intersect the XX axis. Fill in Table 2. 5. Determine e the valuess of the PID D controller with the he elp of Table e 1 and fill in i Table 3. v from Table 3 in n the experimental set up using th he respectivve 6. Set the values knobs to test the con ntroller. Closse the loop with negativve feedbackk as shown in i Figure 6, and obtain the closed loop responsse. The con nnection diag gram is give en he closed loo op response e is shown in n figure 8.) in Figure 7. (A typical nature of th e response obtained o in step 6. 7. Trace the

Figure 3: Open loo op system to o obtain step p response 3 of 8

Figure 4: Connectiion diagram for open loo op system to o obtain step p response

Figure e 5: Open lo oop system step s responsse

Fig gure 6: Closed loop systtem with con ntroller

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Fig gure 7: Conn nection Diag gram for clossed loop systtem with con ntroller

Fiigure 8: Clossed loop sysstem step ressponse with controller Va. RESULTS: R 1. Attach the e traced resp ponse obtain ned in Step 3. 2. TABLE 2 : Open O loop re esponse Rise Tim me ope, S Delay D time, L Time constant, c T Slo (sec)

TA ABLE 3 : Co ontroller Para ameters Ti Kp 1.2(T/L) 2L

3: Tyype of Contro oller PID Kp

Ki

Kd

Rise Time (sec)

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Stteady state error

Td 0.5L

Stteady state e error

Part B Design of PID Parameters using MATLAB Simulation In the 2nd part of the experiment, a PID controller will be designed for a third order type “1” plant given by:

.

.

…………………………………………………(3)

The controller transfer function K(s) is as given by (1) and (2). The block diagram of the closed loop system is in Fig. A. The tuning rules used in Part A cannot be used here as there is no definite analytical method other than trial and error, to tune the P, I, D gains (in (1)). Therefore we employ simulation techniques using MATLAB to tune the controller parameters. What is MATLAB? MATLAB is a high-level technical computing language and interactive environment for numeric computation. MATLAB provides tools for automatically choosing optimal PID gains which makes the trial and error process unnecessary. The PID tuning algorithm can be accessed directly using the MATLAB command “pidtune” or through a graphical user interface (GUI) using “pidtool”. The PID Tuner automatically designs a controller for the plant. The controller type (P, I, PI, PD, PDF, PID, PIDF) and form (parallel or standard) needs to be specified. The design is analysed using a variety of response plots, and interactively adjusting the design to meet performance requirements. IVb. PROCEDURE: (To design a PID controller for a 3nd order system with “pidtool”) Procedure to evoke MATLAB: 1. Switch on the PC (to be done strictly in the presence of the teacher-in-charge). Wait for the booting to complete. 2. Search for the shortcut to MATLAB on the desktop. 3. Double-click with the left button on the shortcut. 4. MATLAB screen appears with the following MATLAB prompt, (waiting to execute any MATLAB command): >> 5. Input the open loop transfer function G(s) (in (3)) as: >> num = 10; (Enter) >> den = conv(conv([0.0015 1], [0.0015 1]),[1 0]); (Enter) >> g = tf (num,den) (Enter) 6. From it obtain the closed loop transfer using MATLAB command feedback as: >> gcl = feedback(g,1) (Enter)

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7. To launch the PID Tuner, use the pidtool command: >> pidtool(gcl) The pidtool GUI window, like shown overleaf (Fig .9), should appear.

Figure 9: 8. Change the type of the controller to PID.

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9. Click on the right arrow beside “Show Parameters” to obtain the screen below:

Figure 10: Now the tuning parameters can be adjusted to modify the response in the GUI by dragging the slider at the bottom. 10. Drag the slider to the left and right and note down the changes in response. 11. Adjust the slider to obtain a “settling time” equal to 0.35 secs. Fill in Table 4. Draw a rough sketch of the response. Vb. RESULTS: 1. Attach the step response of the closed loop system obtained in step 11. 2. TABLE 4: Controller Parameters

Kp

Ki

Kd

Settling Time (sec)

VI. REFERENCES: [1] Modern Control Engineering, K. Ogata. [2] Control Tutorials for MATLAB and Simulink [3] www.mathworks.in/help/control/getstart/designing-pid-controllers-with-the-pid-tunergui.html

ASG-07/2008

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DEPARTMENT OF ELECTRICAL ENGINEERING BENGAL ENGINEERING AND SCIENCE UNIVERSITY, SHIBPUR Solid State Devices & Control System Laboratory Sessional(EE-552) Control System Laboratory 5th Semester Electrical EXPERIMENT. No. EE552-C/3 I. Title : Introduction to MATLAB II. Object: To learn the use of the software package MATLAB which contains many builtin subroutines, which in turn can do complex mathematical operations. You will use MATLAB to solve common problems in Control System Design. PROCEDURE TO EVOKE MATLAB: 12. Switch on the PC (to be done strictly in the presence of the teacher-in-charge). Wait for the booting to complete. 13. Search for the shortcut to MATLAB on the desktop. 14. Double-click twice with the left button on the shortcut. 15. MATLAB screen appears with the following MATLAB prompt, waiting to execute a MATLAB command: >> 16. Change your directory using MATLAB command: >> chdir d:\users\uglab 6. Use any MATLAB command as listed in the discussion below. III. Foreword: 1. You do not have to declare variables in MATLAB. It automatically takes each variable as a floating point. All variables are considered to be matrices (MATLAB: MATrix LABoratory). So you do not have to define matrices too. Working will make things more clear. 2. Complex numbers may be entered as x = 4+7i: >> x = -4+7i 3. To add two complex numbers – x = -4+7i and y = -5 + 6i and keep the result in a third variable z, you simply enter: >> z = (-4 +7i) + (-5+6i) 4. Similarly to multiply two complex numbers: >> p = (-4 + 7i) * (-5+6i) 1 of 6

5. A polynomial p1 = s3 +7s2 - 3s + 23 may be expressed by a row vector containing the coefficients arranged in the descending power of s. So to enter p1 = s3 +7s2 - 3s + 23 you type: >> p1 = [1 7 –3 23] 6. To enter: p2 = (s+2)(s+5)(s+6) you type >> p2 = poly([-2 -5 -6]) i.e. you have to give the roots of the first order factors and the polynomial is automatically formed. 7. To display a product of two polynomials (not first order one) , e.g. p3 = (s3 +7s2 + 10s + 9)( s4-3 s3 +6s2 +2s + 1 ) you enter: >> p3 = conv([1 7 10 9],[1 –3 6 2 1]) 8. You may find a partial fraction expansion (PFE) at one go using the function “residue” which works as described below : Say you want to find the PFE of F(s) = B(s)/A(s). You already know how to enter the polynomials A and B. The command is: >> [R,P,K] = RESIDUE(B,A) It finds the residues, poles and the direct term of a partial fraction expansion of the ratio of two polynomials B(s)/A(s). If there are no multiple roots, B(s) R(1) R(2) R(n) ---- = -------- + -------- + ... + -------- + K(s) A(s) s - P(1) s - P(2) s - P(n) The residues are returned in the column vector R, the pole locations in column vector P, and the direct terms in row vector K. The number of poles is n = length(A)-1 = length(R) = length(P). The direct term coefficient vector is empty if length(B) < length(A), otherwise length(K) = length(B)-length(A)+1. To find the PFE of: (7s2 + 9s + 12) F(s) = ---------------------------s(s+7) (s2 + 10s + 100) enter: >> num = [7 9 12] >> den = conv([poly([0 -7])],[1 10 100]) >>[K,p,k] = residue(num,den) 8. To enter a transfer function in the “workspace” of MATLAB you have to enter the coefficients of the numerator and the denominator polynomials in the descending power of “s”. To enter the transfer function: 2 of 6

(s2 + 2s + 3) G(s) = ------------------(5s2 + 6s + 7) At the MATLAB prompt you have to type: >>N = [1 2 3] (Press enter) >>D = [5 6 7] (Press enter) >>G = tf(N,D) The variables “N” and “D” (you can of course choose the name of your own variables) will contain the coefficients of the numerator and the denominator polynomials resp. 9. Obviously “D” contains the coefficients of the characteristic polynomial also. Hence the poles of the system can be found by finding the roots of “D” for which the MATLAB command is: >>R = roots(D) (Press enter) The variable “R” is a column vector containing the poles of the system. So here you use built-in MATLAB subroutine “roots”. 10. You can find the response of the system specified in “N” and “D” to a unit step using the MATLAB subroutine “step”. First you specify the time through which you want to observe the response in the vector “T”. Say you want to observe the response for 0 to 10 secs at an interval of 0.5 sec. Then type: >>T= 0: 0.5 : 10 To get the step response type: >>Y = step(N,D,T) 11. To “plot” a graph of the response against “T” type: >>plot(T,Y) You are using the built-in routine “plot”. Now since you are familiar with some of the commands of MATLAB it will be useful if you also can access an unknown routine using the on-line help in MATLAB. So for the following functions you are requested to learn the usage from the available on-line help. 12. You can find the BODE plot of a transfer function already specified by its numerator “N” and denominator “D”. You have to use the routine “bode”. To learn its usage type: 3 of 6

>>help bode It will tell you what commands to use and also how to create logarithmically spaced frequency points. 13. You may draw the Nyquist plot of a system. Typing: “help nyquist” will tell you the usage. TO SAVE YOUR WORKSPACE: If you want to save all the variables that are currently in use in your “workspace” to recall them later type: save filename. You may name the file as cx1, cx 2 or cy1 cy2 etc. according to your group number. This file will contain all the variables in your workspace and will store it in a file “filename.mat”. To recall the variables type: load filename and all the stored variables will again be available for use. To see all the variables in your workspace type:

who

To read a particular variable simply type the name of that particular variable. To see all the names of the subroutines type And you will know how to use the online help.

help help

IV. EXPERIMENTS: PROBLEM 1. Find the Partial Fraction Expansion (PFE) of: (7s2 + 9s + 12) F(s) = ---------------------------s(s+7) (s2 + 10s + 100) Verify the above results by doing theoretical calculations. PROBLEM 2: Given the transfer function described by:

x2 G(s) = ------------------(s2 + 0.4s + x2)

where x is your group no. 1. Enter the transfer function in the MATLAB workspace. 2. Find the poles of the system. 3. Obtain the unit step response of the system. (Adjust the final time and time intervals to obtain a smooth plot which has nearly “settled” with time) 4. Plot the above response against time. 5. Draw the Bode plot of the system. 6. Verify all the above results by doing theoretical calculations (Then you will appreciate how much labour MATLAB saves!). 4 of 6

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PROBLEM 4: Given the fact that the Nyquist path is drawn with the convention that CW encirclement is considered positive,draw the Nyquist plot of the transfer function: 1 G(s) = ------------------s (s + 1) and hence comment on the stability of the closed-loop system. PROBLEM 5: The root locus of a system can be obtained by the routines “rlocus” and “rlocfind”. Using these draw the rootlocus of the system K G(s) = ------------------s (s2 +4s + 13) Also find: i) ii) iii) iv)

Centroid, number and angles of Asymptotes, Break away point, if any Angle of departure from poles Value of K and co-ordinates of ‘s’ for which the root loci crosses the imaginary axis.

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DEPARTMENT OF ELECTRICAL ENGINEERING BENGAL ENGINEERING AND SCIENCE UNIVERSITY, SHIBPUR Solid State Devices & Control System Laboratory Sessional(EE-552)

Control System Laboratory EXPERIMENT. No. EE552-C/4 I. TITLE: LINEAR SYSTEM SIMULATOR

5th Semester Electrical

II. OBJECTIVE: To study the change in time response of systems with varying order and type to standard test inputs and correlate the results with theoretical predictions. III. Apparatus: Linear System Simulator (LSS), Oscilloscope and an A. C. Power Supply IV. THEORY: Time Response [1] of systems is the first step in control system analysis. It is carried out in order to get ourselves acquainted with the system. The system, here, is represented by its transfer function, G(s). Time response is a plot of the system output against time when the system is fed with a standard test input – step, ramp or parabolic input.

Y Transient

Steady state

Fig. 1 Time Response of a system 1 of 18

Controller

Plant G(s)

Fig. 2 Block-diagram of a Closed Loop System with unity feedback The time response of a few systems will be examined on the Linear System simulator. The objective of the experiment is to demonstrate that the nature of the time response of any particular system is dependent on i)

Application of feedback

ii)

Order of the transfer function: 1st, 2nd and 3rd

iii)

Type of the transfer function: 0 and 1

iv)

Nature of the input applied: Step and Ramp

The time response of i) first order, ii) second order and iii) third order closed loop systems with unity feedback will be examined for i) type 0 and type 1 cases. Step and Ramp inputs will be applied. (To observe the responses on CROs the inputs are made periodic, i.e, a step and ramp input is applied in the form of a periodic square wave and triangular wave respectively.) The description of the equipment and the background theory is given in the attached sheets. V. EXPERIMENTS: In all the experiments below a CRO is to be used. Adjust the “Level” and “Freq” on the LSS to obtain a square wave of 1 V pk-pk, about 14 Hz. This input will be applied in Expts. 1-5. This square wave resembles a “step” input. It is mandatory to give a periodic input in order to observe the response on a CRO. Experiment 1. Step response of a first order, type 0 system in open loop and closed loop. Wire up the system as in Fig. 4.1. Do not connect the “Feedback” point now. The system is in open loop. K is the “Gain” in the forward path set by the POT. The value of K is given in Table I. 2 of 18

1. Apply the square wave. Observe the responses at points ‘A’ and ‘B’ on a CRO. Fill in relevant columns in Table I. Draw a rough sketch of the response. 2. Now connect the “Feedback” point as in Fig. 4.1. As each of the blocks are realized by inverting OPAMPS, in this circuit the “Amplifier” block is included to produce negative feedback.

3. The square wave is applied. Observe the responses at points ‘A’ and ‘D’ on a CRO. Fill in relevant columns in Table I. Draw a rough sketch of the response. 4. Fill in the G(s) used: G(s) = (------------------------------) Table I Sl

K

No. 1.

Rise Time

Steady State Error

Open

Closed

loop

loop

Open loop

Remarks

Closed loop

0.1 5. Roughly sketch the responses obtained in steps 2 and 4 on the same axes.

Experiment 2. Step response of a 1st and 2nd order type 0 system in closed loop. 1. Wire up the system as in Fig 4.2. The system is in closed loop now. Note the exclusion of the “amplifier” block. 2. Square wave is applied. Observe the responses at points ‘A’ and ‘D’. Fill in relevant columns in Table II. Fill up: G(s) = (------------------------------) Table II Sl

K

Rise Time

Steady State

Remarks

No.

1.

0.1

2.

0.5

3.

1.0

3. Roughly sketch all the responses obtained in step 2 on the same axes. Experiment 3.

Effect of varying forward path gain on the step response of a

second order type 0 system in closed loop. 1. Keep the system wired up as in Fig. 4.2. 3 of 18

2. For K = 1, 4, 6 observe the responses at points ‘A’ and ‘D’ on a CRO. 3. Draw rough sketches of the waveforms on a common axes. Experiment 4. Step response of a third order closed loop system 1. Wire up the system as in Fig. 4.3. The system is in closed loop now. 2

Observe the responses at points ‘A’ and ‘D’ on a CRO. Fill in in Table III.

3

Fill up: G(s) = (------------------------------) Table III Sl

K

No of peaks

No. 1.

1.0

2.

1.6

3.

2.0

Experiment 5. Effect of system `type’ on steady state error: 1. Make suitable circuits (from a knowledge of previous experiments carried out) to fill in Table IV (ess denotes steady state error). 2. Observe the responses at points “A” and “D” on a CRO. Draw rough sketches of the responses obtained. Table IV Sl

Type

Input

No.

1st Order K

ess

G(s)

2nd Order Theor.

K

1.

0

Step

0.18

0.02

2.

1

Step

10

1

ess

G(s)

Theor.

VI. Report. 1. Comment on the effect of increasing “K” in Experiment 2. 2. Comment on the change in response with change in system type and input. 3. Attach all the rough sketches done in Expts. 1-4 VII. References: 1. Control Systems Engineering – N. Nise 2. Control Systems Engineering – Nagrath and Gopal. Preliminary Background [1,2] Definitions of: Open loop/closed systems, Time Response, transient/steady state response, stable/unstable response, first/second/third order systems, type 0, type 1 systems, step/parabolic inputs, time response specifications: rise time, peak overshoot, steady state error, Laplace transform of standard time functions, Inverse Laplace transform. 4

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