LDD and Back-Gate Engineering for Fully Depleted ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 6, JUNE 2010

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LDD and Back-Gate Engineering for Fully Depleted Planar SOI Transistors with Thin Buried Oxide Ran Yan, Russell Duane, Pedram Razavi, Aryan Afzalian, Member, IEEE, Isabelle Ferain, Chi-Woo Lee, Nima Dehdashti Akhavan, Bich-Yen Nguyen, Member, IEEE, Konstantin K. Bourdelle, and Jean-Pierre Colinge, Fellow, IEEE

Abstract—We investigate planar fully depleted silicon-oninsulator (SOI) MOSFETs with a thin buried oxide (BOX) and a ground plane (GP). To study the depletion effects in the lightly doped drain (LDD) and substrate, we compare different BOX/GP/ LDD structure combinations. A novel GP back-gate engineering approach is introduced to improve both short-channel effects (SCEs) and LDD resistance. In this technique, an LDD/channel/ LDD mirror doping structure is reproduced in the back gate underneath the thin BOX. It is shown that SCEs are rather insensitive to SOI layer thickness variations and remain well controlled for gate lengths down to 15 nm for both nMOS and pMOS transistors due to outstanding electrostatic control: 63 mV/dec subthreshold swing and 7 mV/V drain-induced barrier lowering at Vdd = 1 V. The shift of the threshold voltage ΔVth with silicon film thickness Tsi down to 0.5 mV/nm is obtained. Simulations show that a 20% reduction in LDD resistance can be achieved in thin BOX devices with an optimized GP, as compared with thick BOX transistors. In addition, an improvement in drive current is also reported. Index Terms—Back-gate engineering, fully depleted siliconon-insulator (FDSOI) MOSFET, lightly doped drain (LDD) depletion effect, thin buried oxide (BOX).

I. I NTRODUCTION

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HE FULLY depleted planar silicon-on-insulator device architecture (FDSOI) is a promising candidate for technology nodes of 22 nm and below. It has been shown that decreasing the thickness of the buried oxide (BOX) TBOX (to