Lecture 0. Overview

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Textbook and References. ▫ Textbook: Advanced Digital Design with the Verilog HDL , 2nd edition,. Michael D. Ciletti, Prentice Hall, 2009. ▫ References: ▫ 1.
CSCE 3953 System Synthesis and Modeling

Lecture 0 Course Overview Instructor: Dr. Jia Di

Course Details ƒ This course is for junior level students from Computer Engineering, Computer Science, and Electrical Engineering. ƒ This course will teach students the knowledge of modeling digital systems using HDLs, synthesizing HDL designs using commercial CAD tools under various constraints, performing pre- and post-synthesis tasks, and applying HDLs to design digital systems. ƒ This course prerequisites CSCE 2114 Digital Design

Textbook and References

ƒ Textbook: Advanced Digital Design with the Verilog HDL , 2nd edition, Michael D. Ciletti, Prentice Hall, 2009 ƒ References: ƒ 1. Any HDL books and online resources ƒ 2. Research papers (IEEE, ACM,…)

Topics Covered ƒ Digital Design Methodology and Process ƒ Brief Review of Combinational and Sequential Logic Design ƒ Introduction of Verilog ƒ Behavioral and Structural Models of Combinational and Sequential Logic in Verilog and VHDL ƒ Synthesis of Combinational Logic ƒ Synthesis of Sequential Logic ƒ Synthesis under Constraints ƒ Pipeline and Clock ƒ Post-Synthesis Design Tasks

Projects ƒ HDL design, synthesis, and simulation tool: Synopsys and Mentor Graphics Toolset ƒ Project objective ƒ Design method/theory ƒ Simulation method/procedure ƒ Results ƒ Analysis ƒ Presentation

Grade Evaluation ƒ ƒ ƒ ƒ

Homework: 10% Midterm Test: 25% Regular Project: 35% Final Project: 30%

Contact Information ƒ ƒ ƒ ƒ ƒ

Dr. Jia Di JBHT 523 575-5728 [email protected] Office Hour: 10:30-11:30 am Tuesday and Thursday; other time by appointment only ƒ Course website: http://comp.uark.edu/~jdi/CSCE3953.htm