Textbook and References. ▫ Textbook: Advanced Digital Design with the Verilog
HDL , 2nd edition,. Michael D. Ciletti, Prentice Hall, 2009. ▫ References: ▫ 1.
CSCE 3953 System Synthesis and Modeling
Lecture 0 Course Overview Instructor: Dr. Jia Di
Course Details This course is for junior level students from Computer Engineering, Computer Science, and Electrical Engineering. This course will teach students the knowledge of modeling digital systems using HDLs, synthesizing HDL designs using commercial CAD tools under various constraints, performing pre- and post-synthesis tasks, and applying HDLs to design digital systems. This course prerequisites CSCE 2114 Digital Design
Textbook and References
Textbook: Advanced Digital Design with the Verilog HDL , 2nd edition, Michael D. Ciletti, Prentice Hall, 2009 References: 1. Any HDL books and online resources 2. Research papers (IEEE, ACM,…)
Topics Covered Digital Design Methodology and Process Brief Review of Combinational and Sequential Logic Design Introduction of Verilog Behavioral and Structural Models of Combinational and Sequential Logic in Verilog and VHDL Synthesis of Combinational Logic Synthesis of Sequential Logic Synthesis under Constraints Pipeline and Clock Post-Synthesis Design Tasks
Projects HDL design, synthesis, and simulation tool: Synopsys and Mentor Graphics Toolset Project objective Design method/theory Simulation method/procedure Results Analysis Presentation
Grade Evaluation
Homework: 10% Midterm Test: 25% Regular Project: 35% Final Project: 30%
Contact Information
Dr. Jia Di JBHT 523 575-5728
[email protected] Office Hour: 10:30-11:30 am Tuesday and Thursday; other time by appointment only Course website: http://comp.uark.edu/~jdi/CSCE3953.htm