Will be covered in more detail with sequential VHDL design ...... td l i t (7 d t 0)
signal a : std_logic_vector(7 downto 0);. ▫Another form (less desired, do not use).
Lectures 22-4: Introduction to System design, g , VHDL Basics TKT-1212 Digitaalijärjestelmien toteutus TKTErno Salminen Tampere university of technology Spring 2012 sel ENTITY ifmultiplexer IS port ( a, b, sel : IN STD_LOGIC; z : OUT STD_LOGIC); STD LOGIC); END ifmultiplexer; ARCHITECTURE syn OF ifmultiplexer IS BEGIN -- Syn PROCESS (a, b, sel) BEGIN -- PROCESS IF (sel = ’1’) THEN z others=>'0'); 0 );
