Line-Interactive UPS System Applied to Three-Phase Four-Wire Systems with Universal Filtering Capabilities Rodrigo A. Modesto 1 Sérgio A. Oliveira da Silva 1
Azauri Albano de Oliveira Júnior 2
Department of Electrical Engineering Federal Technological University of Paraná – UTFPR1 Cornélio Procópio – PR, Brazil
[email protected] 1
[email protected] 1
Department of Electrical Engineering University of São Paulo – USP 2 São Carlos – SP, Brazil
[email protected] 2
Abstract—This paper proposes a three-phase line-interactive Uninterruptible Power Supply (UPS) scheme, which is applied to three-phase four-wire systems, allowing harmonic suppression and reactive power compensation of the load, resulting effective power factor correction. The proposed UPS system is composed of two PWM converters, where one of them is placed in parallel with the load and the other one is placed in series between the power source and the load. Both the converters share the same DC-bus, which is composed of a battery bank. The parallel converter is implemented by using a four-leg VSI topology and it is controlled to operate as a sinusoidal voltage source, while the series converter is implemented by means of a three-leg topology and it is controlled to operate as a sinusoidal current source. The proposed scheme allows the voltage level reduction of the DC bus, when compared to the use of two three-leg split-capacitor topologies for performing the series-parallel conditioning. In addition, the number of switches is also reduced when it is compared to the use of two four-leg topologies. Both the UPS voltage and current controllers are implemented in the synchronous rotating reference frame (dq0-axes), and the PWM converters are modulated by using three-dimensional space vector modulation. Simulation results are presented in order to validate the theoretical development and confirm the performance of the UPS system. Keywords—harmonic suppression; reactive compensation; three-phase four-wire systems; UPS system
I.
INTRODUCTION
Nowadays, the increasing use of non-linear loads by industrial, commercial and residential consumers, which drain distorted currents from the utility grid, has contributed to worsen the power quality (PQ) at the point of common coupling (PCC). Thus, the interaction between the harmonic currents and the utility impedance can contribute to cause distortions in the utility voltage. On the other hand, the effects caused by the harmonic currents flowing at PCC have been mitigated by means of power quality conditioners, such as parallel and series active power filters (APFs), unified power quality conditioners (UPQCs), and others [1-17]. Usually, parallel APFs have been employed to mitigate the effects caused by the circulation of the harmonic currents on the power system [1-3], while the series APFs have been used
978-1-4799-2399-1/14/$31.00 ©2014 IEEE
to compensate utility voltage disturbances, such as voltage sags, voltage swells and voltage harmonics [4, 5]. On the other hand, both series and parallel active power-line filtering capabilities can be simultaneously provided by means of the unified power quality conditioners (UPQCs) [6-17]. Uninterruptible power supply (UPS) systems have been employed in several applications in order to ensure uninterrupted power to critical loads, such as medical equipment, computers, and others. Besides, the UPS systems have also been used for power-line conditioning in three-phase systems [10-13], performing protection against power supply disturbances and providing clean and uninterruptible power to critical loads. Therefore, power quality improvement is carried out in the electrical systems. Under normal and abnormal incoming power conditions, the line-interactive UPS systems presented in [11, 12] were implemented for making balanced and sinusoidal the threephase currents drained from the utility grid. Besides, balanced, regulated, and sinusoidal output voltages were provided to the load. The referred UPS systems operate similarly to UPQC performing the series and parallel active power line conditioning when they are working in the standby operation mode. Normally, the most usual UPQC arrangements consist in back-to-back converter topology sharing a common DC-bus capacitor. In this case, the parallel converter operates as a shunt APF eliminating any non-sinusoidal harmonic currents of the nonlinear loads, while the series converter operates as series APF eliminating the disturbances of the utility grid voltages [6, 7, 14-17]. In this case, both the voltages and the currents synthesized by the series and the parallel PWM converters are non-sinusoidal. On the other hand, the UPQC can also operate using a dual control, which can be implemented by means of the same arrangement [8, 9]. In this dual control strategy, the series PWM converter operates as a sinusoidal current source, while the parallel PWM converter operates as a sinusoidal voltage source. Both the PWM converters are controlled to operate in phase with the input voltage. The fact that both the voltage and current references are sinusoidal, this dual strategy brings several advantages
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when compared with the traditional control strategy. One of them is due to the fact that the parallel converter operates as a sinusoidal voltage source. In this case, the calculations of any compensation series voltages are not needed. Therefore, the utility voltage disturbances are indirectly compensated and naturally absorbed by the series transformer [8-12].
necessary for the proper operation of the parallel 4-L inverter is lower than that needed for operation the 3-L split-capacitor topology. It is noticed that the amplitude of the DC-bus voltage must be higher than the peak amplitude of the line-to-line utility voltage. On the other hand, for a proper operation of the structure shown in Fig. 1 (a), the DC-bus voltage must, necessarily, be higher than twice the maximum amplitude of the phase-to-neutral mains voltage.
The line-interactive UPS system presented in this paper operates similarly to a dual UPQC performing the series and parallel active power line conditioning when it is working in the standby operation mode. Working as a dual UPQC, in [10] and [12] the UPS systems were implemented for three-phase four-wire systems applications.
It should be noted that, although the series PWM converter shown in Fig. 1 (c) uses the 3-L split-capacitor topology, its DC-bus voltage can be enough reduced in order to synthesize the sinusoidal currents imposed into the grid (Fig. 1 (c)). Besides, the reduced number of switches represents another important advantage when the UPS topology shown in Fig. 1 (c) is compared with the UPS scheme presented in Fig. 1 (b).
In order to perform the series and the parallel power-line conditioning, in [12] two three-leg (3-L) PWM converters were used as presented in the Fig. 1 (a), while in [10] two four-leg (4-L) converters were used as shown in Fig. 1 (b).
This paper is organized as follows: Section II describes the
the structure of the proposed line-interactive UPS system
In this paper the both the 3-L and the 4-L converters, which are used to compose the proposed UPS system, are presented in Fig. 1 (c).
and its main features. In Section III, the state feedback current and voltage controllers are presented, while the strategies used to generate the sinusoidal UPS voltage and current references are presented in Section IV. In Section V the simulation results of the UPS are shown and, finally, Section VI presents the conclusions.
The proposed scheme allows the voltage level reduction of the DC bus, when compared to the 3-L split-capacitor topologies used for performing the series-parallel conditioning (Fig. 1 (a)). This happens because the DC bus voltage level Lsa vsa Lsb vsb Lsc vsc
isa
sw
isb isc
vLa
vLb
vLc
Lsa vsa Lsb vsb Lsc vsc
iLa
iLb iLc
sw
isa
vLa
isb
vLb
isc
vLc
iL 0
isa
isc L fs
Cdc
Vdc Vdc
Cdc
L fp
Vdc
Cdc
C fp
Critical Loads
ica icb icc L fp
isa isb isc isn
2
2
iLa iLb iLc
L fs
C fp
Series PWM Converter
(a)
iL 0
Parallel PWM Converter
(b)
Lsa vsa sw Lsb vsb Lsc vsc
isa isb isc
Cdc L fs
Cdc
Vdc Vdc
isa
vLa
isb
vLb
isc
vLc
iLa
iLb iLc
ica icb icc L fp 2 2
C fp
iL 0
(c) Fig. 1. Line-Interactive Topologies for three-phase four-wire systems. (a) UPS system with two 3-L VSIs; (b) UPS system with two 4-L VSIs; (c) Proposed UPS system with both 3-L and 4-L VSIs.
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II.
LINE-ITERATIVE UPS SYSTEM TOPOLOGY
The three-phase UPS topology proposed in this paper is shown in Fig. 1 (c). It is composed of two PWM converters, such as the 3-L and the 4-L PWM converters. The converters share a common DC-bus voltage, which is comprised of a battery bank. The 3-L converter is current controlled and performs the series power-line conditioning, making the input currents sinusoidal and balanced. The 3-L converter uses three independent current controllers acting on half-bridge inverters. As can be noted, the output voltages of the 3-L converter (voltages across the series transformers) are obtained by means of the difference between the input and the output voltages. In other words, the amplitudes of these voltages are low, when compared with the amplitudes of the output voltages. Therefore, the DC-bus voltage needed to synthetize the currents of the series converter can be defined as the half to that necessary to synthetize the output voltages of the parallel converter (UPS output voltages). On the other hand, the 4-L inverter is voltage controlled and performs the parallel power-line conditioning, making the output voltages sinusoidal, balanced and regulated. Thus, in the standby operation mode (normal incoming power), the UPS operates with universal filtering capability. Since the series converter behaves as a sinusoidal current source, its high impedance must be enough to isolate the utility of the harmonic currents of the load. Meanwhile, once the parallel converter behaves as a sinusoidal voltage source, its low impedance must be enough to absorb the harmonic currents of the load. As the UPS system operates similarly to a dual UPQC, in the standby operation mode, its efficiency depends on, mainly, the following aspects: 1) the load fundamental power factor; 2) the harmonic contents of the load currents; 3) the difference between the rms input and output voltages; and 4) the power rate used for the battery charging [12]. In other words, its efficiency is directly related to the power rate handled by the PWM converters. Fig. 1 shows the static switches ‘sw’, which are used to protect critical loads. Thus, when an occasional interruption of the incoming power occurs they provide the disconnection between the UPS and the power supply. III.
the coupling inductances and their resistances are assumed to and be identical, as follows: . Thus, from Fig. 1 (c), the state equations of the system are expressed by:
_
.
(2)
_
.
(3)
The state-space system is defined as: x(t)
A. x(t)
B. u(t)
F. w(t)
(4)
_
Where: ( )
; x=
; u=
; w=
_
.
_
The state equation in the synchronous rotating reference frame dq0, is given by (5). ( )
( )
. .
( )
.
(5)
( )
Where: ω
0
ω 0
0
1 0 0
;
0
0 1 0
0 0; 0
1 0 0 0 1 0 . 0 0 1 The block diagram of the physical system in dq-axes is shown in Fig. 2, where Dd and Dq are the duty cycles in the synchronous reference frame, which are obtained from the PWM. The DC-bus voltage is represented by Vdc. R fs
STATE FEEDBACK CURRENT AND VOLTAGE CONTROLLERS
Dd
In this Section the state feedback current and voltage controllers used in the three-phase UPS system are presented. They are implemented in synchronous rotating reference frame (dq0-axes). A. State Feedback Current Controller (Series PWM converter) The control of the 3-L converter is implemented based on SRF controller. Thereby, the mathematical modeling is presented in order to obtain the state space system and the transfer functions in the dq0-axes. To perform the modeling, all
(1)
.
_
Vdc
udpwm +
VCd
1 L fs
+
+
isd
ω.L fs ω.L fs
Dq
Vdc
−
uqpwm +
−
VCq
+
−
1 L fs
isq
R fs
Fig. 2. Physical system model of the UPS in dq-axes for the 3-L converter (Series PWM converter).
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+
udpwm
+ −
− +
isd
+
−
−
+
vCd
L fs ω.L fs .isd ω.L fs .isd
R fs
uqpwm
B. State Feedback Voltage Controller (Parallel PWM converter) The control of the parallel converter is also implemented based on SRF controller. Thereby, the mathematical modeling is presented in order to obtain the state space system and the transfer functions in the dq0-axes. To perform the modeling, all the coupling inductances and their resistances, and the filter capacitor are assumed to be identical, as follows: , and . Thus, from Fig. 1, the state equations of the system can be expressed by:
L fs ω .L fs .isq ω .L fs .isq
R fs
isq
+
−
−
vCq
( ,
.
_
(9) .
Thus, in the synchronous dq-axes, neglecting the crosscoupling, the transfer functions of the system GS(d,q) is given by (6). 1
(8) .
The cross-coupling between the direct and quadrature dqaxes can be eliminated using the decoupled model presented in Fig. 3, where the shaded blocks represent the decoupling terms.
)( )
.
_
Fig. 3. Model of the decoupled system in dq-axes.
.
_
(10)
(6)
.
.
The block diagram of the current controller is shown in Fig. 4 (a), where PI controllers are used according to Fig. 4(b). Thereby, the closed loop transfer function , ( )/ , ( ) is obtained, as follows: ( , )(
) )( )
( ,
( , )
( , ) ( , )
iLa
iLb iLc * Vdc
Current Reference and Current Control
+
Vdc
is ( a,b,c )
* isb
3-L Converter (Series APF)
* isc
(12)
(7)
( , )
The representation of the Current Control block presented in Fig. 4 (a) is detailed in Fig. 4 (b). * isa
(11)
(13) The state equation in the synchronous rotating reference frame dq0, is given by (14).
R fs
vinv
+
_
is ( a,b,c )
1 s.L fs
(14)
_ _
Physical System System Physical
PI
−
Where:
;
(a) * isd
+
isd
isq
* isq =0
+
ω
+
ω.L fs ω.L fs −
0
ω
isd
0
0
isq
+
0 0
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0 0
0 0 ;
0
0
0 0
0 (b)
;
0
+
Fig. 4. Block Diagrams: (a) Current Reference and Current Control; (b) Current Controller.
0
0 ω 0
ω 0 0
0 0 ; 0
;
0
0
= 0
;
0
0
0 =0 0
;
0
0 0 0
0 0 =0 0
;
0 0 0
0 0 ; 0
L fp ω.L fp .iiq ω.L fp .iiq
R fp
0
0
udpwm
+
uqpwm
0
+
iCfpd
vLd
−
R fp
.
+ −
− +
iid
0
0
=
0 0 ; 0
ω.C fp .vLd
iCq
iCfpq
vLq
−
4.L fp
4.R fp
u0 pwm
iCd
L fp ω.L fp .iid ω.L fp .iid
iiq
The block diagram of the physical system in dq0-axes is shown in Fig. 5, where Dd and Dq are the duty cycles in the synchronous frame, which are obtained from the PWM. The quantity Vdc represents the DC-bus voltage.
ω.C fp .vLq
iCfp 0
ii 0
+
iC 0
vL 0
−
The cross-coupling between the direct and quadrature dqaxes can be eliminated using the decoupled model shown in Fig. 6, where the shaded blocks represent the decoupling terms.
Fig. 6. Model of the decoupled system in dq0-axes.
Thus, in the synchronous dq0-axes, neglecting the crosscoupling, the transfer functions of the system, GP(d,q) and GP(0), are given by (15) and (16), respectively.
The series PWM converter is controlled to make the source currents ( , , ) sinusoidal and in phase with the , ). Accordingly, respective power supply voltages ( , the series converter must behave as a current source with high impedance, enough to isolate the line from the load harmonic currents.
( , )(
( )(
1
)
.
)
4
.
GENERATION OF VOLTAGE AND CURRENT REFERENCES OF THE SERIES AND PARALLEL CONVERTERS
iCfp( a,b, c)
1 4
.
(15)
1
IV.
.
(16)
1
iLfp (a ,b,c)
v*La
vsa vsb vsc
R fp
vinv
v*Lb v*Lc
Details related to the Voltage Control block, represented in Fig. 7 (a), are shown in Fig. 7 (b).
1 s.L fp
+
iL − is iLfp +
v L ( a , b, c )
1 s.C fp
v L ( a , b, c )
(a) 1 ZL
R fp
Dd
Vdc
udpwm
+
+
1 L fp
iCd
iid +
+
ω.L fp
Dq
Vdc
uqpwm +
−
1 L fp
iiq
+
iCq
4.R fp
Vdc
u0 pwm
+
v*Lq = 0 +
1 4.L fp
−
vLq 1 C fp
vLq v*L 0 = 0 +
1 ZL
R fp
D0
vLd
ω.C fp −
iC 0
ii 0 +
iLd − isd +
vLd
ω.C fp
ω.L fp −
1 C fp
v*Ld
vL 0
iCfd
iCfq
+ +
+
+
+
iLfd
iLfq
+
+
+
iLq − isq +
+
+
vLq
ω.L fp −
+
iCf 0 iLf 0
vLd
iCfd iLfd
ω.L fp
−
iCfq iLfq
vL 0 iCf 0 iLf 0
+
iL 0 − is 0
(b)
1 ZL 1 C fp
+
vL 0
Fig. 5. Physical system model of the UPS in dq0-axes for the 4-L converter (Parallel PWM converter).
Fig. 7. Block Diagrams: (a) Voltage Reference Generation and Voltage Control; (b) Voltage Controller.
Similarly the parallel PWM converter is controlled to act as a sinusoidal voltage source, such that regulated, balanced and , ) are provided to the sinusoidal output voltages ( , load. Any voltage disturbances such as sags, swells, harmonics and transients are handled by the series PWM converter
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through the series transformer. In addition, the parallel converter must behave as a voltage source with low impedance, enough to absorb the harmonic currents of the load. As with the source current, the output voltage is also controlled to be in phase with the power supply voltage. Furthermore, for the UPS system operation, the parallel converter is continuously working as a balanced and sinusoidal voltage source in both standby and backup modes. Therefore, the reference quantities in dq0-axes are constants and the PI controller (outer loop) and P controller (inner loop) are implemented in dq0-axes. The complete block diagram of the Voltage Control of the parallel PWM converter is shown in Fig. 8. iCfd v*Ld
+
v*Lq = 0
+
−
+
+
+
+
iCfq +
−
iLfq
−
iLd − isd
+
+
iLq − isq
+
−
iLfd
+
ω.L fp +
v*L0 = 0
+
vLd vLq vL0
vLa vLb vLc
+
−
sinθ cosθ
+
ω.L fp
iCf0
sinθ cosθ
+ +
iL0 − is0 iLfd iLfq iLf0 sinθ cosθ
+
vLa vLb vLc
−
Fig. 8. Block Diagram of the Voltage Control (parallel PWM converter).
SRF-based algorithm is used to perform the compensation of the three-phase four-wire UPS system, when single or threephase loads are fed. The SRF-based algorithm provides the sinusoidal source currents (isa, isb, isc) for the series PWM converter as shown in Fig. 1(c). The block diagram of the control scheme for current compensation is shown in Fig. 9. The direct SRF current (id) is obtained by using (17) and (18), where the coordinates of unit vector, sinθ and cosθ, are obtained from the three phase-PLL system [12], which will be identical to the utility phase-angle. In dq-axes, a low-pass filter (LPF) is used to extract the active fundamental component ) of the load currents (iLa, iLb, iLc). ( The total direct current , given by (19), is reached by to the component obtained from the DC-bus adding . Thereby, the current ( ) represents the controller positive sequence component of the load currents added to the used to perform the battery charging and, current additionally, compensate the losses related to the coupling inductances and the switching devices.
2 0 3 1 √2
1 2 √3 2 1 √2
1 2 √3 2 1
+
iLc
sinθ
vsa vsb vsc
cosθ
+
iBdc
* Vdc
+
Vdc
−
Fig. 9. Block Diagram of the Series Reference Current Generation (series PWM converter).
In other words, the PI output signal represents the total active power required to regulate the DC-link voltage. Therefore, to make balance the active power through the UPS DC-bus, the amplitudes of the series reference currents must be controlled. Thus, this task is performed by means of the DCbus controller. The PI controllers are implemented in dq-axes as discussed in the previous section. The complete block diagram of both Current Reference and Current Control is shown in Fig. 10. SIMULATION RESULTS
To verify the behavior of the UPS topology and the strategies used to generate and control the sinusoidal voltage/current references, the computational tool PSIM Version 9.0® was used, in which the three-phase converters operate at 20 kHz switching frequency. The simulations were performed considering unbalanced non-linear loads, which are composed of three single-phase diode bridge rectifiers, followed of R-C loads. The nominal utility rms phase-to neutral voltage is equal to 127 V and the values of the unbalanced R-C loads are: Ra=30Ω; Rb=20Ω; Rc=15Ω and Ca= Cb= Cc=1.5mF. The three-phase utility voltages are assumed to have harmonic contents and unbalances. Table I resumes the parameters used in the simulations, while the Proportional (P) and the Integral (I) gains related to the controllers of the output voltages and input currents are shown in Table II. TABLE I. SIMULATION PARAMETERS PWM Converters
iLa id iLb i i s*d + abc/dq d LPF dc+ iLc + i* = 0 iBdc sq sinθ cosθ * Vdc
+
Vdc
(18)
−
PI
isd
PI −
isq
abc / dq
isd
C fp =360
ω.L fs
PI +
-
L fp = 0.25
isq −
Filter Capacitors (μF)
L fs = 1.5
Vdc = 400
Parallel
√2
Filter inductors (mH)
DC-bus voltage (V)
Series
(17)
(19)
* isd
id dc
id
V.
vsa vsb vsc
iLfpa iLfpb iLfpc
1
iLa iLb
+ +
ω.L fs
sinθ cosθ
dq/αβ +
sinθ
SVM
3-L Converter (series APF)
cosθ
PLL
vsa vsb vsc
isa isb isc
Fig. 10. Block Diagrams: Series Reference Current Generation and Current Control.
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isa isb isc
TABLE II. CONTROLLER PARAMETERS Voltage Controller Gains Outer Inner Loop Loop dq0-axes P I P 10 5000 10 dq 20 5000 20 0
Simulation results were presented in order to validate the theoretical development and confirm the good performance of the proposed line interactive UPS system.
Current Controller Gains P
I
5 -
5000 -
vsa vsb vsc
Fig. 11 shows the input and output voltages of the UPS system. As can be noticed, all the voltage disturbances, such as unbalances and harmonics were compensated. The parallel converter provides sinusoidal, balanced and regulated voltages to the loads with low total harmonic distortion contents. Fig. 12 presents both the load currents and the compensated source currents when load transients occur at 60ms. As can be noted, although the load currents (iLa, iLb, iLc) are distorted and unbalanced, the source currents (isa, isb, isc) become sinusoidal and balanced with low total harmonic distortion contents. The phase “a” voltages and currents of the UPS operating in both standby and backup modes are shown in Figs. 13 and 14, respectively. In Fig. 13 (a), (b) and (c) are shown the UPS input voltage, the series transformer voltage, and the output voltage, respectively. As can be noticed in Fig. 13, the voltage across the series transformer (vca) is the difference between the respective input and output voltages. The UPS currents, such as the load current, the parallel converter current, and the compensated input current, are shown in Fig. 14 (a), (b) and (c), respectively. Fig. 14 shows that do not occur any transient or transfer-time on the output voltages during the operation modes of the UPS (standby-backup and backup-standby). VI.
CONCLUSION
vLa vLb vLc
Fig. 11. UPS voltages: (a) Input voltages ( v sa , v sb , v sc ); (b) Output voltages ( v La , v Lb , v Lc ). iLa
iLb
isa
isb
iLc
isc
Fig. 12. UPS currents for Load Imbalance Compensation: (a) Load currents ( iLa , iLb , iLc ); (b) Input currents ( i sa , i sb , i sc ).
This paper proposed a three-phase line-interactive UPS scheme, which is applied to three-phase four-wire systems, with universal filtering capabilities. Two PWM converters were used to construct the UPS system, such as the 3-L and the 4-L PWM converters, both sharing the same DC-bus composed of a battery bank. The parallel converter was implemented by using the 4-leg VSI topology operating as sinusoidal voltage source, while the series converter, operating as a sinusoidal current source, was implemented by means of a 3-leg VSI topology. The 3-Leg VSI used to compose the series filter was implemented by three independent current controllers acting on half-bridge inverters. Once the voltages across the series transformers are relatively low (around 25% of the nominal utility voltage), it was possible the series PWM converter operates with half of the DC-bus voltage amplitude for synthetizing the series compensating currents. Additionally, in four-wire system applications, the use of the 3-Leg VSI allowed the reducing the number of switching devices when compared to the 4-Leg PWM converter.
Fig. 13. Standby-Backup and Backup-Standby UPS Voltages (phase “a”): (a) Input voltage ( v sa ); (b) Series Transformer Voltage ( v ca ); (c) Output voltage ( v fa ).
ACKNOWLEDGMENT The authors would like to thank the CAPES (Coordination for the Improvement of Higher Education Personnel) for the financial support.
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[6] [7] [8] [9]
[10]
[11] Fig. 14. Standby-Backup and Backup-Standby UPS Currents (phase “a”): (a) Load Current ( i La );(b) Inverter current ( ica ); (c) Input current ( i sa ).
[12]
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[2]
[3]
[4]
[5]
W. H. Choi, C. S. Lam, M. C. Wong and Y. D. Han, “Analysis of DCLink Voltage Controls in Three-Phase Four-Wire Hybrid Active Power Filters,” IEEE Trans. on Power Electronics, vol. 28, no. 5, pp. 21802191, May 2013. V. Khadkikar and A. Chandra, “An Independent Control Approach for Three-Phase Four-Wire Shunt Active Filter Based on Three H-Bridge Topology under Unbalanced Load Conditions,” in Proc. 39th IEEE Power Electronics Specialists Conference, 2008, pp. 4643-4649. Silva, S. A. O.; Feracin, Angelo, Cervantes, S. G. S., Goedtel A., Nascimento, C. F., “Synchronous Reference Frame Based Controllers Applied to Shunt Active Power Filters in Three-Phase Four-Wire Systems”. in: IEEE International Conference on Industrial Technology, 2010, 832-837. S. Bhattacharya and D. M. Divan, “Synchronous Frame Based Controller Implementation for Hybrid Series Active Filter System,” in Proc. 30th IEEE Industry Applic. Society Annual Meeting, pp. 25312540. J.W. Dixon, G. Venegas, and L.A. Morán, “A Series Active Filter Based on Sinusoidal Current-Controlled Voltage-Source Inverter,” IEEE Trans. on Industrial Electronics, vol. 44, no. 5, pp. 612-619, October 1997.
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