Linearization Technique for Binary Phase Detectors in a ... - IEEE Xplore

1226

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 6, JUNE 2014

Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit Byoung-Joo Yoo, Student Member, IEEE, Woo-Rham Bae, Jiho Han, Member, IEEE, Jaeha Kim, Senior Member, IEEE, and Deog-Kyoon Jeong, Senior Member, IEEE Abstract— A multichannel clock and data recovery (CDR) circuit that employs binary phase detectors (PDs) yet achieves linear loop dynamics is presented. The proposed CDR recovers the linear information of phase errors by exploiting its collaborative timing recovery architecture. Since the collaborative CDR combines the PD outputs of the multiple data streams, a deliberate phase offset can be added to each PD to realize a highrate oversampling PD without additional PDs. The analysis shows that there exists an optimal spacing between these deliberate phase offsets that maximizes the linearity of the proposed PD for given jitter conditions. Under these conditions, the loop dynamics of a linear, second-order CDR model agree well with the simulated responses even with a finite latency difference between the proportional and integral control paths. The linearized characteristics of the PD and the overall CDR designed for 45-nm CMOS technology are, respectively, verified by using a time-step accurate behavioral simulation. Index Terms— Binary phase detector (PD), clock and data recovery circuit (CDR), digital control, linearization techniques, serial link.

I. I NTRODUCTION

M

ANY clock and data recovery (CDR) circuits in high-speed serial data communication systems employ binary or bang-bang phase detectors (PDs) because of their high-speed operation and low design complexity in spite of nonlinear characteristics [1]–[3]. In comparison, linear PDs often require full-swing amplification of the incoming data stream and/or propagation of the short pulses [4], which adversely affects the performance-power tradeoff. The nonlinearity of the binary PDs can cause critical problems for the overall CDR system: the jitter transfer characteristic can change depending on the amount of jitter or noise present in the system. To address these problems, prior CDR architectures reported in the literature aimed to make the CDR loop dynamics linear, including the oversampling CDR [5], and the alternating edge-sampling PD [6]. A scrambling-techniquebased time-to-digital converter (TDC) using a digitallycontrolled switched capacitor is also reported [7]. However, many of these approaches incur high hardware cost, which Manuscript received November 19, 2012; revised March 23, 2013 and May 19, 2013; accepted June 9, 2013. Date of publication June 28, 2013; date of current version May 20, 2014. This work was supported in part by the DMC R&D Center of Samsung Electronics Co., Ltd. and the Inter-University Semiconductor Research Center of Seoul National University. The authors are with the Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Korea (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2013.2269616

makes them unsuitable for a multichannel transceiver configurations. The oversampling CDR requires additional samplers and retiming-circuits, and both the alternating edge-sampling CDR and the scrambling-technique-based TDC have limits in the maximum oversampling ratio due to the growing complexity of the phase detection logic and increasing number of delay elements. In this paper, a simple linearization technique for the binary PDs that exploits the collaborative timing recovery architecture of a multichannel CDR is proposed, and is validated with a time-step accurate behavioral simulation. The proposed technique adds different phase offsets to the PDs of the individual channels; hence, the whole set of PDs can effectively act as an oversampling PD. With the hardware cost equivalent to that of the conventional 2×-oversampling CDR, the proposed CDR can achieve PD gain variation of less than ±5% in detecting the phase differences from −0.2 to 0.2 UIs. In addition, it maintains constant linear jitter transfer characteristics for the input jitter ranging from 0.03 to 0.09 UIrms . II. OVERVIEW OF B INARY P HASE D ETECTION Before describing the proposed PD linearization technique, the basic principle of the binary PD transfer characteristic is reviewed first. The average transfer characteristics of bangbang PDs in the presence of jitter was previously analyzed in [8] and [9]. The analysis will be later extended to describe the linearized transfer characteristics of the proposed multichannel PD and find its optimal configuration. The characteristics of binary phase detector in defect of jitter and in presence of jitter are shown in Fig. 1. Unlike a linear PD, a binary PD detects only the polarity of phase error, whether the recovered clock phase is leading or lagging relative to the incoming data timing as shown in Fig. 1(a). Regardless of the amount of phase error (err ), the PD output is always up or down with a constant value. This nonlinearity implies that the PD gain K P D is infinite right at the decision boundary and zero elsewhere. Therefore, a CDR with a binary PD cannot stay locked at one position; instead it keeps dithering back and forth around the locking point and the PD generates pseudorandomly alternating up and down outputs. However, various types of jitter are present either in the incoming data transitions or in the recovered clock; hence, the binary PD can statistically detect the magnitude information of the phase error. Intuitively speaking, the densities of the up and down outputs may gradually change from 50:50 as the phase error increases from zero. In other words, the PD gain

1063-8210 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

YOO et al.: LINEARIZATION TECHNIQUE FOR BINARY PHASE DETECTORS

Φerr

Φerr

1227

Lane #4 Lane #3 Lane #2 Lane #1

Eavg

Data w/o Jitter

Data Deserializer

2X oversampling

Sampling & Jitter PDF

Large leading

Small leading P(up)

1 Probabilities of up and down ΔP

= -1

P(dn)

0

Sampler Edge Sampler

CTLE

Фerr

Drx

Phase Detection

UP/DN

Transition Count

TR#

1

1

PI

0

dCK

PI

ΔP = -1

0

Local Digital Filter

DCO

Deliberate offset D

Φerr

Global Loop

(a)

Eavg Offset0 Offset1 Offset2 Offset3

Data w/ Jitter

1 ΔP 0

Small leading

f(x)

P(up) 1

1

P(dn) 0

0

Small Jitter

Фerr Large Jitter

P(up) 1 ΔP

Half-rate binary PD

KPD

f(x)

P(dn) 0

Data VREF

Edge Edge Edge Sampler Edge Sampler Sampler Sampler

UP/DN Decision

KPD ∝ αT·f(x)

(b)

Synthesized UP/DN Sum & TR-Count

1 to 2 Deserial

data_odd

Data

Sampler

D

Q

D

Q edge_even

DN CLK

CLK

E avg (φerr ) = D B B αT (P(up) − P(dn)) φerr f (x)d x − = D B B αT −∞

+∞ φerr

f (x)d x

(1)

where D B B is the quantized value of the binary PD output, and αT is the data transition density. This result shows that the net average PD output corresponds to a convolution between the jitter pdf and the ideal phase detection gain curve of the binary PD. This agrees with previously reported results [8]. Assuming an even-symmetric function for the pdf, the effective PD gain can be written as follows: K P D |φ=φerr

∂ E avg(φ) = = 2D B B αT f (φerr ). ∂φ φ=φerr

(2)

Therefore, the effective PD gain decreases for low data transition density or large amount of jitter as shown at the right of Fig. 1(b). However, the amount of jitter is often not

#UP/DN

(b)

Fig. 1. Characteristics of the binary PD. (a) Nonlinearity in defect of jitter. (b) Linearization in the presence of jitter.

is effectively smoothened and the PD has a finite range with a constant, linear slope. In most CDRs and PLLs whose PD sampling frequency is much higher than the loop bandwidth, the instantaneous noise (i.e., the quantization noise) of the BB-PD outputs will be filtered out by the loop bandwidth, leaving only the smoothened and linearized transfer characteristics of the binary PD. The linearization of the binary PD transfer characteristics in presence of jitter is shown in Fig. 1(b). Statistically, the average output of a binary PD is proportional to the difference P between the up probability P(up) and the down probability P(dn). Unlike the case of Fig. 1(a) with the constant P, the jitter changes the P proportional to the phase error err . And then, the up and down probabilities can be calculated as an integration of the jitter probability density function (pdf) f (x). When the phase error is denoted as err , the equation can be expressed as follows:

∑UP/DN

/2

eCLK_even dCLK_even eCLK_odd dCLK_odd

Probabilities of up and down

Digital Loop Filter

eCK

KPD≈ ∞

0

Φerr

Sampling & Jitter PDF

Decimator & FD

Local Loop 1

(a)

Large leading

Error Sum.

eCLK_even

Sampler dCLK_even

Sampler

dCLK_odd D

Q

dCLK_odd D

Q

dCLK_odd D

Q data_even

UP

OUTP

OUTN

dCLK_odd D

Q

edge_odd

DN INP

eCLK_odd

Sampler dCLK_odd

dCLK_even D

Q

dCLK_even

(c)

D

Q

data_odd

UP

Ref+

INN

Ref-

Offset Cal.

dCLK_odd

CLK

Offset Cal. CLK

dCLK_odd

(d)

Fig. 2. Block diagram of (a) multichannel receiver with a shared CDR employing the proposed PD linearization technique, (b) front-end, (c) halfrate binary PD, and (d) clocked sampler.

the parameter that a designer can predict or control. In addition, the transition density of incoming data can be changed depending on the data encoding scheme of a transmitter or the data pattern itself. These lead to the variation in the CDR’s loop bandwidth or stability, depending on the jitter condition and the encoding method of the transmitted data. III. L INEARIZATION T ECHNIQUE FOR M ULTICHANNEL B INARY PD S A. CDR Architecture With Collaborative Timing Recovery The overall block diagram of a four-channel serial data receiver that incorporates a collaborative timing recovery CDR [10], along with the proposed PD linearization technique is shown in Fig. 2(a). The receiver of each channel consists of a linear equalizer followed by a set of half-rate data and edge slicers for 2×-oversampling the binary phase detection. The results of the samplers are parallelized by one to two deserializers and are used to calculate a sum of the UP/DN signals and a number of UP/DN events by the synthesized UP/DN decision logic as shown in Fig. 2(b). Basically the binary phase detection logic consists of four-samplers and flipflops for the half-rate bang-bang phase detection as shown

1228


Collaborative Edge Sampling

Rotational Sampling

Error Sum.

Step-by-step Shift

PD gain after optimization UP/DN

UP/DN

CH0 eclk PD

CH1

Optimization

Error Sum.

eclk

Ф

Ф

CH2 eclk CH3

2θ eclk ФSTEP=2θ

ФSTEP ФOFFSET

fg(-3θ) fg(-θ)fg(+θ)fg(+3θ)

Linear Range

f0(x) f1(x) f2(x) f3(x)

σPDF

Jitter PDF fN(x)

Jitter PDF

fg(x)

fg(x)

σjit

0

(a)

Ф

-3θ

-θ

+θ +3θ

Ф

(b)

fg(-2θ) fg(0) fg(+2θ)

Ф

(c)

Ф

(d)

Fig. 3. Proposed linear phase detection process and its jitter PDF. (a) Collaborative edge sampling. (b) Rotational edge sampling. (c) Error summation. (d) Optimization of PD gain linearity.

in Fig. 2(c) and each sampler adopts the architecture of differential clocked comparator with digitally adjustable offset as shown in Fig. 2(d). The outputs of the individual phase detection logics are combined by the global digital filter, which controls the frequency and phase of a digitally controlled oscillator (DCO) to adjust the global clock timing. The global digital filter consists of an error summation block, a decimator, a frequency detector, and a digital loop filter that includes a delta-sigma modulator. The collaborative timing recovery extracts more information on the phase error and lowers the dependency on the data transition density fluctuation by aggregating the PD outputs of multiple channels. The assumption is that the data on the multiple channels are transmitted with a common timing while the data patterns and transition densities of the individual channels are sufficiently random and independent of each other. Because of the aggregation, the change in the condition that affects all the multichannel PDs (e.g., a shift in the common clock timing) is detected with a full PD gain, while the change that is local to just one of the PDs (e.g., fluctuation in the transition density in one of the data streams) is sensed with a 1/4-reduced gain. To suppress the dependency of the PD gain on data transition density even further, the PD outputs are normalized to the total number of data transitions detected before being aggregated. For example, the case with two upsignals out of 10 data transitions has equal consequences with the case with 20 up signals out of 100 data transitions. This decimation helps the CDR to achieve relatively constant loop characteristics, regardless of the data transition density. A local de-skewing circuit is added to each channel’s clock path to compensate for any possible skews between the channels’ propagation delays. The local de-skewing circuit consists of a local digital filter and phase-interpolators. To prevent the interaction between the global loop and the local loop, the bandwidth of the local loop filter is set at about 1000 times lower than that of the global loop. A set

of four local digital filters adjust the local clock skews by accumulating the corresponding PD outputs over time and using the result to control the phase interpolator settings. The implemented phase-interpolator can adjust the timing of the globally distributed clock in steps of 1/30 UI. The shared DCO generates 10 uniformly-spaced clock phases and a phase interpolator stage synthesizes a new phase that is between the two adjacent coarse phases. The deliberate phase offset applied to the PD of each channel is controlled by a digital offset added to the phase interpolation settings. Note that these deliberate offsets for the PD linearization are added only to the edge-sampling clocks so that they do not increase jitter in the data sampling clocks. The deliberate phase offsets are generated by a finite-state machine (FSM) that circulates through a certain pattern that ensures zero-bias in the effective PD transfer and uniform coverage of the sampling positions. The more specific linearization technique using deliberate offsets will be explained in the next subsection. B. Linearization of Binary PD Characteristics The whole process of the proposed binary PD linearization technique is shown in Fig. 3. The key idea of the proposed technique is to intentionally add a time-varying phase offset to each edge slicer. The edge slicer with a phase offset detects the polarity of the phase error compared with the given offset rather than with an ideal zero, as shown in Fig. 3(a). A different offset is applied to each edge slicer using the phase interpolators, and the offset’s position is rotated among the four channels using the FSM, as shown in Fig. 3(b). The phase offsets are rotated among the channels to remove the static phase offsets of each sampling clock caused by the process of local de-skewing. If the jitter pdf of each data is f N (x), as shown at the bottom of Fig. 3(a), the four PDs sampling this distribution with four


1229

The optimal conditions will be derived and discussed in Section IV. C. Rotational Pattern of Deliberate Phase Offset

(a)

(b) Fig. 4. Sampling with rotational phase offsets among channels. (a) Block diagram of the transceiver sampling with the rotational deliberate phase-offset. (b) Pattern of the rotational sampling phase-offset.

different phase offsets can be considered equivalent to a single PD sampling the four overlapped jitter pdfs each with the corresponding offset as shown at the bottom of Fig. 3(b). As the contributions made by the individual jitter pdfs are linearly summed, the effective jitter pdf seen by the multichannel PDs would the one as shown in Fig. 3(c). Again, it should be noted that the data slicers are still triggered by the clock without the phase offsets; hence, they do not see such an increased jitter distribution and the timing margin of the receiver is kept maximized. Introducing these deliberate offsets to the edge-sampling phases in the collaborative CDR enables the PDs to statistically oversample the phase error and recover its linear magnitude information. However, the phase offsets that are positioned at discrete levels can cause quantization effects in the PD gain curve, such as with an oversampling PD or a TDC. Even though the underlying jitter and noise in the system will smoothen the PD transfer characteristic, there may still exists gain variation due to the quantization steps. This quantization steps can be explained by the variation of the effective jitter pdf within the range of linearization, as shown at the bottom of Fig. 3(c). With a finite number of phase offset levels available, there exists an optimal spacing between the phase offset levels that maximize the PD’s linearity for a given jitter condition, as shown in Fig. 3(d). For a specific ratio between the phase offset and the sigma of jitter, the PD characteristics, such as the linearization of the PD gain are largely insensitive to the jitter condition, unlike with the conventional binary PDs.

The rotational sampling example in the receiver block with the deliberate phase offset of each edge-sampling clock is shown in Fig. 4(a). The addition of the deliberate phase offsets for a given PD makes it possible to linearly detect the phase error of global clock, and those rotating also makes it possible to recover the linear information of the skew, while requiring only one pair of sampling clocks, one at the edge and the other at the center of incoming data (i.e., 2× oversampling). It is the edge-sampling clock whose phase is periodically changed by some offsets in accordance with a preprogrammed pattern. When the frequency of this periodic pattern is properly set, phase disturbances do not affect the average behavior of the CDR NOR cause periodic jitter or spurious tones in the local clocks. The frequency components generated from the periodic pattern are harmonics of the divided sampling clock, which is used in local and global loop-filters. Therefore, the phase disturbances caused by the deliberate phase offsets are downsampled close to dc components by PD and removed by very low loop bandwidth. To avoid artificial bias due to the deliberate phase offsets, the sum of the offsets applied to one PD over one update period is always equal to zero. In addition, for uniform coverage of the phase offsets, the sum of the phase offsets applied to the four PDs is always equal to zero at any given time. The rotating pattern of the phase offsets across the four channels and their sums per channel and across the channels are shown in Fig. 4(b). The update period of the digital loop filter is eight DCO clock cycles, so the pattern is repeated every eight cycles. During this period, the global summation G θ and local summation L θ of the phase offsets are always zero. Most of the momentary shifts in the edge-sampling clock phase will be filtered by the low bandwidth of the CDR and will not adversely affect the jitter level of the recovered, data-sampling clock. In the meantime, both the global CDR and local de-skewing circuit can extract the linear phase-error information without any additional hardware other than the 2×-over sampling binary PD. IV. PD G AIN A NALYSIS AND O PTIMIZATION To realize linear system dynamics for the CDR, its PD should have a constant phase detection gain across a wide range of phase error. The phase detection gain corresponds to the slope in the average PD transfer characteristic curve, i.e., the curve of the average PD output E avg() versus the phase error . Therefore, the effective transfer curve of the proposed linearization PD will be analyzed and a condition for its constant slope will be defined in this section. The linearization technique described in Section III effectively realizes a set of PDs that compare the phase error with the multiple phase offsets. The effective PD gain curve computed by the convolution between the jitter pdf and the binary PD transfer curve is shown in Fig. 5. The number of channels is 2N, the maximum total PD output is assumed to

1230


(a)

Fig. 5.

Effective PD gain curve of the proposed 2N-channel receiver.

be ±D B B , and the spacing between the adjacent phase offset levels is 2θ or L /N. The effective PD transfer characteristic can be derived by summing those with their own jitter pdfs, assuming that the all jitter pdfs of all the channels have the same standard deviation of σjit distribution but different offsets. K EPD |φ=φerr = D B B αT

N−1

f (φerr + (2n + 1) · θ )

n=0

(b)

+ f (φerr − (2n + 1) · θ )

= D B B αT f g (φerr )

(3)

where f g (err ) is the combined effective jitter pdf of the 2N channels, as shown in Fig. 3(c). Note that the expression is exactly the same with that for the 2N-times oversampling PD [5]. Assuming a sufficiently large N, the effective PD gain is as follows: lim K EPD |φ=φerr

N→∞

= lim D B B αT N→∞

N−1

f (φerr + (2n + 1)θ )

n=0

+ f (φerr − (2n + 1)θ )

(4)

so that lim K EPD |φ=φerr

N→∞

N−1 D B B f (φerr + (2n + 1)θ ) · θ = lim αT N→∞ θ n=0

+ f (φerr − (2n + 1)θ ) · θ D B B = αT θ

(2N−1)θ 0

f (x)d x +

0

−(2N−1)θ

f (x)d x . (5)

Fig. 6. Simulated jitter PDF of the 4-channel CDR with various ratios between θ and σjit . (a) Shape of the combined effective jitter PDF. (b) Normalized maximum difference of the combined effective jitter PDF within ±4θ .

If the normalized jitter pdf f (x) is practically zero outside the linear range of (err < − L or err > L ), the integral parts of (5) can be assumed to be one. And, as shown in Fig. 5, the output of a single binary PD D B B and the phase spacing between adjacent offsets θ are D B B /N and L /N, respectively. Then, the effective PD gain can be written as follows: DB B ≈ αT . (6) lim K EPD N→∞ φL φ=φerr Therefore, (6) demonstrates that the effective gain of a binary PD using the proposed technique converges to a constant value as the number of channels increases. The converged value is determined only by the maximum output of the PD (D B B ) and the whole linear range ( L ), and is independent of the jitter pdf. However, when the number of channels (2N) is finite, a CDR employing the proposed binary PD linearization technique may have nonuniform PD gain. For instance, if the ratio between the phase offset spacing θ and the jitter standard deviation σjit is too large, (3) predicts that the PD gain may fluctuate within the linear range. On the other hand, if the ratio is too small, the PD gain will be constant but the linear range becomes narrow.


Therefore, there is an optimal ratio between the θ and σjit that makes the PD gain uniform across the widest range instead of increasing the number of channels. As the uniformity of PD gain is dependent on the shape of the effective jitter pdf f g (err ) as expressed by (3), the change of f g (err ) within the linear range by various ratios between θ and σjit should be noted. Assuming a Gaussian distribution for each f (x), f g (err ) is also a function of θ and σjit , and then it can be plotted by the various ratios between θ and σjit as shown in Fig. 6(a). The assumption of f (x) as a Gaussian distribution is reasonable because the jitter histogram of wellequalized data commonly has a similar form to the Gaussian distribution, especially when using a continuous-time linear equalizer. At the much higher ratio of θ/σjit , the effective jitter pdf f g (err ) has multiple lofty peaks and valleys within the linear range between ±2N · θ resulting in fluctuation of PD gain. As the ratio decreases to the optimized value, the fluctuation is reduced and the f g (err ) within the linear range will be constant. However, since the decreased θ means reduced linear range of ±2N · θ , the optimized ratio of θ/σjit should be redefined according to the targeted linear range. The optimized ratio θ/σjit can be easily obtained by calculation of the maximum difference of the peaks and valleys. If the number of channels is even, the peaks and valleys of f g (err )within the linear range are located at phases of kθ and kθ/2 for any integer k. For example, as the effective jitter pdf f g (err ) of a four channel CDR is the summation of four Gaussian functions that are shifted along x-axis, we can write f g (φerr ) = f (φerr + 3θ ) + f (φerr + θ ) + f (φerr − θ ) + f (φerr − 3θ ) − (φerr +3θ )2 )2 − (φerr +θ 2 2 1 2σjit 2σjit √ +e e = σjit 2π +e

) − (φerr −θ 2 2σjit

2

+e

) − (φerr −3θ 2

2

2σjit

. (7)

In the range from −3 to 3θ , the local maximum and minimum are f g (θ ) and f g (2θ ). To define the optimal condition that makes PD gain almost constant, we consider the difference between the maximum and minimum as follows: f g = f g (θ ) − f g (2θ ) = f (4θ ) + f (2θ ) + f (0) + f (−2θ ) − f (5θ ) − f (3θ ) − f (θ ) − f (−θ ) 2 2 2 − 25θ2 − 16θ2 − 9θ 2 1 2σjit 2σjit 2σjit = √ +e −e −e σjit 2π 2 2 − 4θ 2 − θ2 2σjit 2σjit +2e −e +1 .

(8)

We can see f g is determined by the ratio of θ and σjit for a specific jitter condition. The calculated f g , which is also normalized by the average value of the f g within the linear range, for the four channel CDR for various ratios of deliberate phase offset and jitter is shown in Fig. 6(b). The f g remains small for θ/σjit < 1.16 and increases rapidly after that point. In other words, if the ratio θ/σjit is in the

1231

range below the dotted line (θ/σjit = 1.16), the gain variation of the proposed PD will be reduced to under 5%. The exact optimal ratio to minimize the f g while achieving the widest linear range is that θ/σjit = 0.9, which is obtained by solving the differentiated equation. Regardless of the absolute values of the jitter and phase offset, the optimal ratio is always close to 0.9 while the percentage of gain variation is 1.04%. At the ratio of 0.9, the effective jitter pdf has a flat proof as shown in Fig. 6(a). If the channel number is odd, the optimized ratio will be shifted from 0.9 to 0.74. Even though the PD gain is relatively constant regardless of the input noise conditions, the specific values of result can be slightly changed by the number of channels, the form of the jitter pdf, or the noise of devices. In addition, the result of calculation shown in Fig. 6 excludes how the loop dynamic influences the binary PD gain. According to the previous report [9], the loop dynamics of CDR decreases the gain of binary PD as follows: K BBPD (σjit , β K T ) = D B B αT f (0) ⎡ · ⎣1 + e

− 21

Mβ K T σjit

2 ⎤

⎦

(9)

where M is the feedback divider factor, β is a proportional path gain, and K T is the period gain constant of DCO. The result of (9) is always lower than the result of (2), like in a case of more jitter. Therefore, the optimized ratio will be slightly shifted to a lower value. However, the effect is not dominant due to the relatively small β K T , and the optimized ratio σjit /θ always exists close to the ratio 0.9. In the result of the optimized ratio, the gain of the binary PD using the proposed 2N-times linearization technique as in (3) can be approximated to the following linear equation: DB B . (10) 2Nθ As mentioned, the gain within the phase range between ±2N ·θ is only in inverse proportion to the phase offset spacing θ , regardless of the jitter pdf σjit . K P D ≈ αT

V. L OOP DYNAMICS The nonlinear dynamics of a bang-bang CDR or PLL can be analyzed by a nonlinear map plotting the trajectory on a bidimensional phase plane [11]. Even though the analysis is accurate and powerful, its procedure is very complicated. On the other hand, the linear model makes it possible to analyze the loop dynamics more simply and intuitionally. To verify the validity of (10), the jitter transfer characteristic of CDR employing the proposed linearization technique is analyzed and simulated with the z-domain and s-domain models in this section. In addition, the latency effect of the loop dynamics for the accurate CDR modeling is analyzed. Latencies unintentionally added to the paths of the CDR loop cause critical problems, such as the dithering for binary CDRs and the phase margin reduction for linear CDRs. Many studies reported the effect of latency with discrete or continuous models for all-digital PLLs and all-digital CDRs. However, the model for the latency is commonly added to all paths [12],

1232


or is only added to the integral path, while ignoring the latency for the proportional path [13]. In the collaborative timing recovery architecture, the latency of the proportional path cannot be ignored anymore because of its increased number of blocks. Unlike the other CDRs, the collaborative timing recovery requires a summation block and a decimation block for processing errors generated from all the channels before the loop filter. Hence, both the proportional path and the integral path must have more latency than one reference clock cycle. In addition, the integral path commonly has more blocks than the proportional path, such as a delta-sigma modulator and an encoder for DCO frequency control. Therefore, the amount of latency should be applied separately to the proportional path and the integral path of the CDR model. Commonly, the integral path has more latency than the proportional path by a few clock-cycles. Z -domain and s-domain models of the second-order CDR are shown in Fig. 7. Both of them have the different latency model between the integral path and the proportional path. In the z-domain model as shown in Fig. 7(a), K P D is the transfer characteristic of the linearized binary PD [i.e., equal to (10)], then the open-loop transfer function is as follows: G(z) =

K P D K DCO (αz −D P +1 (z − 1) + βz −D I +2 ) (z − 1)2

ω ωref · φerr 2π

where ωref /2π is the update frequency of the loop filter.

H (z) =

Фin(z)

Z-Dp

α

KPD

Integral path

KDCO 1-z-1

Фout(z)

1/s

Фout(s)

Z-Di

β Z-1

(a) Фin(s)

Фerr(s)

KP

e-sTp

KI/s

e-sTi

ωout(s)

ωP

ωI

(b) Fig. 7. Block diagrams of the CDR models for (a) z-domain and (b) s-domain. G( s)

2

ω z ,l = −

⎛ 1 ⎞ KP 1 + ⎜ ⎟ + 2TP ⎝ 2TP ⎠ 4TP 2

ω z ,h =

⎛ 1 ⎞ KP 1 + ⎜ ⎟ + 2TP ⎝ 2TP ⎠ 4TP

0 dB

l arg e TP log (ω) small TP

(11)

zero TP

where D P and D I are the latencies of the proportional and integral paths, and the α and β are their gains, respectively. Then, the closed-loop transfer function from in to out is shown in (12) at the bottom of the page. With z −1 = exp(− j ωT ) and loop-filter update period T , it is clear that the closed-loop transfer function has a lowpass characteristic. Nonetheless, the intuitional analysis is very difficult because the transfer function is not a secondorder system due to the latency components. Sometimes, the z-domain analysis is simpler than the time-domain analysis due to the fact that the z-domain model can be easily obtained. However, the well known z-domain analysis methods, such as the unit circle criterion are not convenient and do not support the quantitative parameters that are familiar to designers, such as phase margin, damping factor, and bandwidth. To analyze the loop more conveniently and intuitively, the s-domain model of Fig. 7(b) is used. In common with the z-domain model, the different latencies are added to each path as the parameters exp(-sT P ) and exp(-sT I ). The parameters K P and K I can be calculated by the discrete forms of PD gain, loop filter gain, and DCO gain [14]. Then, K I can be expressed by the amount of update frequency per cycle of loop filter ω and phase error err as follows: KI =

Proportional path

Фerr(z)

(13)

∠G ( s ) small TP

-135º -180º

PM

ω z ,l

ωc

l arg e TP

ω z ,h

log (ω)

Fig. 8. Amplitude and phase response of the open-loop transfer function under the various conditions of T P .

Under the same conditions, K P can also be calculated by the amount of update phase as follows: KP =

φ ωref . · φerr 2π

(14)

Assuming that the update frequency and phase per single cycle of the loop filter are adjusted by a 1-bit control signal, the phase error err used in both (13) and (14) is equal to the inverse of (10). The open-loop transfer function from err to out is as follows: K P e−sTP s + K I e−sTI . (15) s2 In common with the z-domain model, this result also cannot be analyzed easily because of two terms of latency. Assuming the small value of sT where the frequency of interest is much lower than the Nyquist frequency (i.e., one half of the update frequency), we can simplify the function by substituting the G(s) =

K P D K DCO αz −D P +1 (z − 1) + K P D K DCO βz −D I +2 G(z) = . 1 + G(z) (z − 1)2 + K P D K DCO αz −D P +1 (z − 1) + K P D K DCO βz −D I +2

(12)


1233

written as follows: ωn,0 =

KI (19) KP ζ0 = √ . (20) 2 KI To determine the effect of latency in the open-loop transfer function, (20) can be used. First, if we design the parameter ζ0 as the value 1, we can define the relationship between K P and K I as follows: K P2 = 4K I .

Going back to (16), the location of zeros can be calculated by the quadratic formula of the numerator as follows: ±(K P − K I TI )+ (K P − K I TI )2 + 4K P K I T P . (22) ωz = 2K P T P Assuming K P T P 1 and K P TI 1, the value of K P −K I TI is positive and its approximate expression is K P . This assumption is generally reasonable, because the order of K P is commonly much lower than the orders of 1/T P and 1/TI when the latencies are a few cycles of the update clock. After substituting (21), a high-frequency zero ωz,h and a lowfrequency zero ωz,l are as follows: 1 2 1 KP ωz,h ≈ + + (23) 2T P 2T P 4T P 1 KP 1 2 ωz,l ≈ − + + . (24) 2T P 2T P 4T P

(a)

(b) Fig. 9. (a) Natural frequency and (b) damping factor of the second-order CDR with the various latency conditions.

approximation expression of 1-sT for exp(-sT) [15]. Then, (15) can be written as follows: G(s) =

−K P T P s 2 + (K P − K I TI )s + K I . s2

(16)

Then, its closed-loop transfer function H (s) = out (s)/in (s) is as follows: H (s) =

−K P T P 2 1−K P T P s

s2 +

+

K P −K I T I 1−K P T P

K P −K I T I 1−K P T P

s+

s+

KI 1−K P T P

KI 1−K P T P

.

(17)

The closed-loop transfer function H (s) can be compared with the classical two-pole system transfer function H (s) =

(21)

2ζ ωn s + ωn2 s 2 + 2ζ ωn s + ωn2

(18)

where ωn is the natural frequency and ζ is the damping factor. If we defined ωn,0 and ζ0 as a natural frequency and a damping factor with zero latencies (i.e., T P = 0 and TI = 0), by comparison between (17) and (18), each parameter can be

With these zeros, (16) can be written as follows: −(s + ωz,l )(s − ωz,h ) . (25) G(s) = s2 The value of ωz,h can be considered inversely proportional to the quite small value of proportional-path latency T P , and the phase of the open-loop transfer function around the zero is starting to decrease. As the amount of frequency change in response to T P is much larger than the low-frequency zero ωz,l , the two zeros will be close together as T P increases. The amplitude and frequency response of the open-loop transfer function (16) under the various conditions of T P is shown in Fig. 8. The increased T P moves ωz,h toward ωz,l , which is located at a relatively constant frequency, and the reduced distance between the zeros decreases the phase margin. Therefore, the dominant source of decreased phase margin is the latency of the proportional path, not the integral path. In addition to the phase margin, the natural frequency and damping factor are also affected by the latencies T P and TI . The relationship can be found by comparison between (17) and (18) with nonzero latencies. Note that the secondorder term of the numerator can be ignored when K P T P 1. Then, we can express ωn and the ζ in terms of K P , K I , T P , TI , ωn,0 , and ζ0 as follows: KI ωn,0 ωn = = √ (26) 1 − K P TP 1 − K P TP 1 − KKPI · TI 1 − KKPI · TI KP · √ = ζ0 · √ . (27) ζ = √ 2 KI 1 − K P TP 1 − K P TP

1234


(a)

and the multiplication blocks for dividing the aggregated up/down signal by the data transition count in the digital decimator are also merged to the error summation block. In addition, the encoded up/down signals and transition counts to signed bits for reducing the number of transmitted bits from the each lane to the global error summation block decoded to unsigned bits in the digital loop filter. Even though the analysis using the model 1-sT is not perfectly matched to the real characteristics, it shows the effects of increased latency on the loop characteristics and gives the methodology of designing a CDR that has different latencies between the integral and proportional paths. The comparisons of the closed-loop transfer functions and open-loop transfer functions between the 1-sT and the exp(-sT) model are shown in Fig. 10(a) and (b). It should be noted that the bandwidth and peaking of the closed-loop transfer characteristics increase proportionally to the proportional latency while the phase margin decreases. In addition, as the proportional latency grows, the mismatch between the models becomes significant. When the latency increases excessively, exp(-sT) cannot be replaced by the 1-sT anymore, and the assumption to calculate (23) and (24) is also not correct. VI. S IMULATION R ESULTS

(b) Fig. 10. Comparison of (a) second-order CDR closed-loop transfer functions, and (b) phase plots of those open-loop transfer functions between (dashed lines) exp(-sT ) latency model and (solid-lines) 1-sT latency model with the fixed α and various proportional latency conditions.

The damping factor and the natural frequency of the proposed second-order CDR in response to the various latency conditions are shown in Fig. 9. As shown in Fig. 9(a), the change on T P , and ωn increases of natural frequency ωn only depends √ from ωn,0 by the ratio of 1/ 1 − K P T P as T P increases. The damping factor ζ is changed by both T P and TI . Since TI is always larger than T P , it can be expressed as T P + α. Then, the damping ratio decreases in response to α, and the increased T P accelerates the decrease of the damping ratio, as shown in Fig. 9(b). Therefore, the latency of the proportional path cannot be ignored when designing the CDR with collaborative timing recovery, and it is a dominant source of change in the design parameters, such as phase margin, damping factor, and natural frequency from the first design. To keep the original design parameters, the latency of the proportional path should be considered and minimized first. In the proposed CDR, a lot of functional blocks on the proportional path were merged in single block to reduce the latency. Then, all functions in the block are began and completed within one clock cycle reducing the number of registers. For example, a gain control block of the proportional path is combined to the decimator,

To verify these analytical results, a time-accurate behavioral simulation is performed on the conventional binary PD and the proposed linearized binary PD sampling with the deliberate phase offsets. The model for the time-accurate behavioral simulation is implemented with synthesizable digital blocks, such as a digital loop filter, a decimator, and a FSM, and cell-based analog blocks for the behavioral modeling, such as front end blocks, DCOs, and phase-interpolators. The whole proposed CDR was designed by the model-first flow, which was reported in our prior work [16]. Starting of the design with accurate event-driven functional models to simulate a top-level mixed-signal system helps detect problems due to the interaction between the analog and digital circuits, and improves the design and validation productivity. In addition the fully automated physical design process gives more flexibility to complete the top-design of chip and makes easy porting to technologies with different scales. The gain curves of the conventional binary PD and the proposed linearized binary PD are simulated and compared. As shown in Fig. 11(a), the statistical gain of a conventional binary PD varies with the jitter in the range of 0.01 to 0.09 UIrms . Within this jitter range, the ratio of minimum to maximum gain is about 6.65. On the other hand, the proposed PD maintains a relatively constant gain for various jitter conditions, as shown in Fig. 11(b). Under the same jitter condition with Fig. 11(a), the ratio of minimum to maximum gain is only 1.178. The 211 -1 PRBS data with 0.5 transition density is used for the test. The simulated CDR has the sampling phase offset θ of 0.033-UI between the channels; hence, linearization with constant PD gain can be achieved for the jitter higher than σjit = 0.03 − U Irms (θ /σjit = 0.91). In the case of 0.01-UIrms jitter, the gain is also sufficiently bounded close to (10).


1235

(a) Fig. 12. Simulated jitter transfer curve of CDR under the various jitter conditions. TABLE I CDR L OOP PARAMETERS

(b) Fig. 11. Simulated PD gain curves of (a) conventional binary PD and (b) proposed collaborative edge sampling PD.

When the CDR is simulated with Gaussian random jitter on the incoming PRBS data streams with 3-Gb/s data rate and −105-dBc/Hz phase noise in the DCO at 10 MHz offset, the CDR exhibits a relatively fixed 3-dB-bandwidth around the 7.3 MHz for all the listed jitter conditions, as shown in Fig. 12. As the input noise increased, the jitter transfer curve has lower 3-dB-bandwidth. However, the variation is the same as the gain variation of the result of Fig. 11, bounded within 5% from the targeted loop bandwidth. The 0.09-UIrms jitter caused the largest bandwidth shift with an unrealistic value, because its peak-to-peak jitter is more than 0.6 UI. The relatively high peaking of the transfer curve is due to the increased latencies of proportional path and integral path, as shown in the Fig. 10. The design parameters of the simulated CDR are shown in Table I. The designed CDR employing the proposed PD linearization technique has the proportional latency of three referenceclock cycles, which are generated from the error summation block and the decimator with the inherent one-cycle delay in a sampled-data system. The integral path has two more latencies, which are caused by an accumulator and a deltasigma modulator. With those latencies, the proposed CDR has the phase margin of 55°, the damping factor of 1.067, and the

Fig. 13. Comparison results of the jitter transfer characteristic between the simulation and calculations of z-domain and s-domain.

natural frequency of 18.7 Mrad/s. The jitter transfer function of the designed CDR with those latencies is compared with the z-domain model and the s-domain model of Fig. 7, as shown in Fig. 13. With the PRBS data stream of each channel with

1236


in the behavioral simulation is based on the practical design with the process of Samsung 45-nm CMOS technology. VII. C ONCLUSION

(a)

(b)

A simple yet effective technique to linearize the binary PD transfer characteristics of a multichannel 2×-oversampling CDR was proposed, and the effect of latency mismatch between the integral and proportional paths in the collaborative timing recovery architecture was analyzed. With the proposed linearization technique, a CDR with binary PDs can realize constant, linear loop dynamics, largely independent of the jitter conditions, while only requiring hardware complexity that was equivalent to the conventional 2×-oversampling CDR. R EFERENCES

(c)

(d)

Fig. 14. Simulated jitter histogram of recovered clock (a) without noise sources, (b) with only DCO phase noise of −105 dBc/Hz at 10-MHz offset, (c) with the DCO phase noise and 0.06-UIrms input jitter, and (d) with the DCO phase noise and 0.09-UIrms input jitter.

0.03-UIrms random jitter, the simulated jitter transfer curve is well matched with both models. The amplitude of the jitter transfer out of the cutoff frequency is decreased by more than −20 dB/decade. As the added high frequency zero is shifted to a lower frequency in response to the latency, the amplitude peaking increases. Then, by the imaginary poles with the damping ratio, which falls to below the “1,” the amplitude declines more rapidly at higher frequency than the zero and converges to the same values with the case of zero latency at the much higher frequency, where the effect of the zero is ignored. The jitter of the recovered clock is determined by the noise of the data stream, the DCO phase noise, and the systematic noise of CDR. The jitter histograms of the recovered clock with the various noise sources are shown in Fig. 14. For a condition when the phase noise of the DCO and the input noise of the incoming data stream are excluded, the jitter of the recovered clock is shown in Fig. 14(a), and its rms value is 0.0131. If the phase noise of −105 dBc/Hz at 10-MHz offset is added to the DCO, the jitter increases to 0.0172 UIrms , as shown in Fig. 14(b).The input noise added to the data stream slightly changes the RMS jitter, as shown in Fig. 14(c). Therefore, the dominant jitter source of the designed CDR is the systematic jitter and phase noise of the DCO. Since the CDR employing the proposed binary PD linearization technique shows constant loop bandwidth regardless of the input random jitter conditions, implying constant jitter transfer characteristics, the jitter dominantly caused by the systematic noise or DCO phase noise should be almost a fixed value. However, even if the input noise is a minor source, the jitter of the recovered clock increases proportionally to the noise of the incoming data stream, as shown in Fig. 14(c) and (d), because the noise power within the constant loop bandwidth also increases. The amount of DCO phase noise that is used

[1] J. D. H. Alexander, “Clock recovery from random binary data,” IET Electron. Lett., vol. 11, no. 22, pp. 541–542, Oct. 1975. [2] J. Savoj and B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector,” IEEE J. SolidState Circuits, vol. 38, no. 1, pp. 13–21, Jan. 2003. [3] R. Walker, “Designing bang-bang PLLs for clock-and-data recovery in serial data transmission systems,” in Phase Locking in High Performance Systems. New York, NY, USA: Wiley, 2003, pp. 34–45. [4] C. Thangaraj, R. Pownall, P. Nikkel, G. Yuan, K. L. Lear, and T. Chen, “Fully CMOS-compatible on-chip optical clock distribution and recovery,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 10, pp. 1385–1398, Oct. 2010. [5] Y. Choi, D.-K. Jeong, and W. Kim, “Jitter transfer analysis of tracked oversampling techniques for multigigabit clock and data recovery,” IEEE Trans. Circuits Syst. II, Analog Digital Signal Process., vol. 50, no. 11, pp. 775–783, Nov. 2003. [6] B. J. Lee, M. S. Hwang, S. H. Lee, and D.-K. Jeong, “A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characterisitc stabilization,” IEEE J. Solid-State Circuits, vol. 28, no. 11, pp. 1821–1829, Nov. 2003. [7] M. Zanuso, S. Levantino, A. Puggelli, C. Samori, and A. L. Lacaita, “Time-to-digital converter with 3-ps resolution and digital linearization algorithm,” in Proc. IEEE ESSCIRC, Sep. 2010, pp. 262–265. [8] J. Lee, J. S. Kundert, and B. Razavi, “Analysis and modeling of bangbang clock and data recovery circuits,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1571–1580, Sep. 2004. [9] N. D. Dalt, “Markov chains-based derivation of the phase detector gain in bang-bang PLLs,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 11, pp. 1–5, Nov. 2006. [10] A. Agrawal, A. Liu, P. K. Hanumolu, and G. Y. Wei, “An 8 × 5 Gb/s parallel receiver with collaborative timing recovery,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3120–3130, Nov. 2009. [11] N. D. Dalt, “A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 1, pp. 21–31, Jan. 2005. [12] M. Zanuso, D. Tasca, S. Levantino, A. Donadel, C. Samori, and A. L. Lacaita, “Noise analysis and minimization in bang-bang digital PLLs,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 11, pp. 835–839, Nov. 2009. [13] N. D. Dalt, “Linearized analysis of a digital bang-bang pll and its validity limits applied to Jitter transfer and jitter generation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 11, pp. 3663–3675, Dec. 2008. [14] J. Kim, M. A. Horowitz, and G.-Y. Wei, “Design of CMOS adaptivebandwidth PLL/DLLs: A general approach,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 50, no. 11, pp. 860–869, Nov. 2003. [15] R. B. Staszewski and P. T. Balsara, “Phase-domain all-digital phaselocked loop,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 3, pp. 159–163, Mar. 2005. [16] J. Kim, S. Ryu, B. J. Yoo, H. Kim, Y. Choi, and D.-K. Jeong, “A model-first design and verification flow for analog-digital convergences systems: A high-speed receiver example in digital TVs,” in Proc. IEEE Int. Symp. Circuits Syst., May 2012, pp. 754–757.


Byoung-Joo Yoo (S’06) received the B.S. degree in electrical engineering from Korea University, Seoul, Korea, in 2005, and the M.S. and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, in 2007 and 2013, respectively. He is currently with the System LSI Division, Samsung Electronics, as a Senior Engineer. His research especially focuses on multichannel and lowpower architecture for next-generation wired-line links. His current research interests include digital and analog integrated circuit design for multistandard and high-speed serial data communications.

Woo-Rham Bae received the B.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in 2010, where he is currently pursuing the Ph.D. degree with the Integrated Systems Design Laboratory. His current research interests include integrated circuits for optical interconnection, high-speed I/O circuits, and architectures.

Jiho Han (S’08–M’10) received the B.S., M.S., and Ph.D. degrees in electrical engineering and computer science from Seoul National University, Seoul, Korea, in 2002, 2004, and 2009, respectively. He is currently with the System LSI Division, Samsung Electronics, as a Senior Engineer. His current research interests include high-accuracy clock synchronization, carrier-grade Ethernet, and clock and data recovery.

1237

Jaeha Kim (S’94–M’03–SM’10) received the B.S. degree in electrical engineering from Seoul National University, Seoul, Korea, in 1997, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, USA, in 1999 and 2003, respectively. He is currently an Assistant Professor with Seoul National University. His current research interests include low-power mixed-signal systems and their design methodologies. Prior to joining Seoul National University in 2010, he was with Stanford University as an Acting Assistant Professor from 2009 to 2010; Rambus, Inc., Los Altos, CA, USA, as a Principal Engineer from 2006 to 2009; and the Inter-University Semiconductor Research Center, Seoul National University, as a Post-Doctoral Researcher, from 2003 to 2006. From 2001 to 2003, he was with True Circuits, Inc., Los Altos, as a Circuit Designer. Dr. Kim was a recipient of the Takuo Sugano Award for Outstanding FarEast Paper at the 2005 International Solid-State Circuits Conference and the Low-Power Design Contest Award at the 2001 International Symposium on Low Power Electronics and Design. He served on the technical program committees of the Design Automation Conference, the International Conference on Computer Aided Design, and the Asian Solid-State Circuit Conference. He is currently a Distinguished ACM Speaker in the area of design automation.

Deog-Kyoon Jeong (S’85–M’89–SM’09) received the B.S. and M.S. degrees in electronics engineering from Seoul National University, Seoul, Korea, in 1981 and 1984, respectively, and the Ph.D. degree in electrical engineering and computer science from the University of California, Berkeley, CA, USA, in 1989. He was with Texas Instruments, Dallas, TX, USA, as a Technical Staff Member, from 1989 to 1991, and worked on the modeling and design of BiCMOS gates and single-chip implementation of SPARC architecture. He joined the faculty of the Department of Electronics Engineering and Inter-University Semi-Conductor Research Center, Seoul National University, where he is currently a Professor. He is one of the co-founders of Silicon Image, which specializes in digital interface circuits for video displays, such as DVI and HDMI. He has published more than 100 technical papers and holds 56 U.S. patents. His current research interests include the design of high-speed I/O circuits and silicon photonics interfaces. Dr. Jeong was a recipient of the ISSCC Takuo Sugano Award for Outstanding Far-East Paper in 2005.