IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 5, MAY 2011
1515
Linearizing Dual-Slope Digital Converter Suitable for a Thermistor N. Madhu Mohan, Member, IEEE, V. Jagadeesh Kumar, Member, IEEE, and P. Sankaran
Abstract—To measure temperature using a thermistor as the sensing element, linearization to compensate for the inverse exponential nature of the resistance–temperature characteristic of the thermistor is required. A linearizing dual-slope digital converter (LDSDC) that accepts a thermistor sensor as input and provides a digital output that is directly proportional to the temperature being sensed is presented here. A logarithmic amplifier at the input of the LDSDC compensates for the exponential characteristics. The conversion logic of the underlying dual-slope converter is suitably modified to implement the required inversion and offset correction and thus obtain linearization over a wide range of input temperature. The efficacy of the proposed LDSDC is established through simulation studies and its practicality demonstrated with experimental results obtained on a prototype unit built and tested. Analysis of the proffered method to identify possible sources of errors is also presented. Index Terms—Direct digital converter, dual-slope converter, linearization, logarithmic amplifier, resistance-to-digital converter, thermistor.
I. I NTRODUCTION
I
N ANY control or instrumentation process, the temperature is an important parameter to be measured. Due to its compactness, high sensitivity, accuracy, ruggedness, biocompatibility, as well as low time constant and low cost, the thermistor is a popular choice for sensing the temperature. However, the advantages that the thermistor offers for the measurement of temperature are eclipsed by the highly nonlinear relationship between the resistance Rθ of the thermistor and the temperature θ it is subjected to. The precise nature of this relationship as well as the means to linearize it has been a matter of study for a long time. Though the exponential nature of the resistance–temperature relationship of a thermistor was known as far back as 1946 [1], with Bosson et al. formulating the threeconstant fit for the lnRθ versus 1/θ curve of the thermistor in 1950 [2], the problem of linearizing this relationship has persisted. Of the different methods that have been tried in linearizing the temperature–resistance relationship of a thermistor, the simplest has been to include a resistor in series and/or in parallel with the thermistor [3]. But this technique achieves linearity only over a small range, that too at the expense of Manuscript received June 18, 2010; revised October 31, 2010; accepted November 1, 2010. Date of publication December 13, 2010; date of current version April 6, 2011. The Associate Editor coordinating the review process for this paper was Dr. Theodore Laopoulos. The authors are with the Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai 600036, India (e-mail:
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIM.2010.2092875
drastically reduced sensitivity. This drawback was sought to be overcome by the use of a reciprocal time generator to obtain a digital output proportional to the temperature [4]. The linearity was further improved by employing a four-constant fit for the relationship governing the temperature and the resistance of the thermistor [5], though at the cost of increased complexity as four simultaneous nonlinear equations had to be solved to obtain the constants. Bosson’s three-constant law was also approximated to develop a linear temperature–time period converter, incorporating a thermistor [6]. The circuit provided excellent linearity (∼0.02%) but over a very narrow range of 10 K, the reason being that such a small variation was one of the essential assumptions on which the approximation of the thermistor characteristic was based. An established technique for the linearization of the output of a thermistor involved the use of different kinds of multivibrators [7], [8] where differing degrees of linearity were obtained over limited ranges of temperatures. An improvement on this method using an astable multivibrator has also been reported [9], which provided acceptable levels of linearization over a greatly increased temperature range of 0–85◦ C. The output of a thermistor was also sought to be linearized by including it as part of a logarithmic amplifier network [10]. A modified form of a relaxation-oscillator-based temperature to frequency converter has been implemented using a delay network [11], with promising results. An innovative approach to solving the thermistor linearization problem has been by using the inverse exponential nature of the voltage–time relationship of a charging RC network, which is based on a modified square wave generator [12]. Though these methods achieve desirable levels of linearity over limited temperature ranges, none of the methods reported so far achieves linearity over the entire dynamic range of operation of a thermistor, preserving its high sensitivity. With the advent of digital technology and the easy availability of faster and economically viable processing power, software has come to be increasingly used in the linearization of transducer outputs, making use of ‘look-up tables’ and ‘maps’ [13], [14]. New techniques like artificial neural networks and evolutionary algorithms have been proposed to iteratively linearize the output of thermistor based circuits [15], [16]. The downside of such methods has been the increasing reliance on brute computing power to find the ‘best’ polynomial fit for the temperature–resistance relationship of a thermistor. Except for the software-based techniques, the outputs of most of these linearizing circuits are analog in nature and need to be converted to a digital form before being interfaced to digital
0018-9456/$26.00 © 2010 IEEE
1516
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 5, MAY 2011
amplifier as shown in Fig. 1. In such a condition, the output vlog of the logarithmic amplifier is vlog = ln(Rθ ) − ln(RA ).
(4)
A comparison of (3) and (4) indicates that the value of resistor RA must be equal to A, one of the constants of the thermistor as given in (1). With this condition, the output of the logarithmic amplifier is vlog = ln(Rθ ) − ln(A).
Fig. 1. Schematic of the proposed dual-slope LDSDC suitable for a thermistor.
instruments. It would evidently make for a simpler and more robust system if the analog-to-digital converter becomes an integral part of the linearizing circuit, so that the final output is linear as well as digitally compatible. A linearizing dualslope digital converter (LDSDC) which offers such novelties has been presented earlier and its efficacy validated through simulation [17]. This paper details the experimental validation of the LDSDC suitable for a thermistor. A rigorous analysis of the scheme to identify and quantify various sources of errors is also presented. II. LDSDC S UITABLE FOR T HERMISTORS The equation that relates the resistance Rθ of a thermistor to its temperature θ as derived by Bosson et al. [2] is β
Rθ = Ae θ+γ .
(1)
Here, A, β, and γ are constants specific to a particular type of thermistor. To obtain an output directly proportional to temperature, the following operations are needed in the order given below. (i) First step is to apply natural logarithm to (1) and rearrange to get β = ln Rθ − ln A. θ+γ
(2)
(ii) The second and final step is to invert and manipulate (2) to obtain: θ=
β − γ. ln Rθ − ln A
(3)
In the proposed scheme, whose block schematic is shown in Fig. 1, (3) is implemented with a logarithmic amplifier to obtain ln Rθ − ln A and a suitably modified dual-slope converter to perform the required tasks of inversion and offset subtraction. In a typical logarithmic amplifier, such as the LOG112 [18], the output is obtained as a logarithm of the ratio of two currents. In the present application, the two currents are derived from a single dc reference voltage. The thermistor is connected as one of the current determining resistors while a fixed value resistor RA dictates the second input current of the logarithmic
(5)
The output of the logarithmic amplifier is given as input to a dual-slope analog-to-digital converter (DSADC). The hardware of the DSADC, again shown in block schematic form in Fig. 1, is the same as a conventional DSADC but the conversion logic is suitably modified to obtain inversion and offset subtraction as required to implement (3). As in any typical DSADC, the ADC part of the LDSDC also contains an RC integrator (realized with opamp and resistor R and feedback capacitor C as indicated in Fig. 1), a comparator and a timing and logic unit (TLU). The logic of the TLU is designed to perform two integrations by suitably controlling the input to the integrator through a single-pole three-way analog switch S. While two of the inputs of S are tied to individual reference voltages (+VR and −VR ) of equal magnitude but opposite polarity, the third input is tied to vlog , the output voltage of the logarithmic amplifier. Switch S is controlled by the control lines A0 and A1 emanating from the TLU. If A1 A0 = ‘01’, then position 1 is selected on S and the dc reference voltage +VR is applied as input to the integrator. If A1 A0 is “10”, then position 2 is set on S, so that the input to the integrator is −VR . If A1 A0 = ‘11’, then position 3 is selected and the output of the logarithmic amplifier vlog is chosen as the input to the integrator. A1 A0 = ‘00’ is forbidden. The integrator output voi is fed to a comparator, whose output vc serves as the input to the TLU. If the integrator output voi ≥ 0, then the output of the comparator vc will be “1” (logic high); otherwise, vc will be zero. The timing inside the TLU is accomplished with either an N-bit (for binary output LDSDC) or N-digit (for a binary coded decimal output LDSDC) presettable up/down timer counter, driven by a clock of period Tc (frequency fc ). Before the process of converting vlog can begin, it needs to be ensured that the output of the integrator is at zero. Therefore, as in any typical DSADC, an auto-zero phase is necessary whenever a conversion command is issued afresh. If a new conversion succeeds a previous conversion, the integrator output will be zero at the end of the previous conversion and hence, an auto-zero phase can be dispensed with. Thus, the LDSDC can be operated either in a controlled (start-stop) or in a continuous conversion mode. In the former, an auto-zero phase precedes every conversion cycle while in the latter, the autozero phase is invoked only once at the start of the measurement cycle. A. Auto-Zero Phase When a convert command is given afresh asynchronously, the initial state of the circuit in Fig. 1 may be such that the
MOHAN et al.: LINEARIZING DUAL-SLOPE DIGITAL CONVERTER SUITABLE FOR A THERMISTOR
Fig. 2. Voltage waveforms at the output of the integrator (voi ) and the comparator (vc ) of the LDSDC.
output of the integrator voi is negative which implies that the output of the comparator vc will be low. The condition vc being low is sensed by the TLU and the control logic for this condition ensures that the control lines A1 A0 to the switch S are set at “10”, so that the negative reference voltage −VR is connected to the fixed resistance R. As a result, a constant current ic = VR /R starts flowing through the capacitor C and the output of the integrator ramps up toward zero. voi reaching zero is indicated to the TLU by vc changing state from low to high, marking the end of the auto-zero phase. On the other hand, if the circuit were to come up in a state where the integrator output is positive, this would be indicated to the TLU by the comparator output vc being high. Such a state would cause the TLU logic to set the control lines A1 A0 to “01”, so that the resistance R is connected to the positive reference voltage +VR causing a current −VR /R to flow through the capacitor, discharging it. As a result, the output of the integrator would now ramp down toward zero. When voi reaches zero, vc changes state from high to low, signaling the end of the auto-zero phase to the TLU, which then initiates the appropriate sequence for the conversion phase. Thus, a transition of the comparator state, either from low to high or from high to low, indicates the end of the auto-zero phase. The broken lines in the waveform diagram of Fig. 2 indicate the integrator and comparator outputs during the auto-zero phase. B. Conversion Phase Once the output of the integrator voi reaches zero, either at the end of an auto-zero phase in the start-stop mode or at the end of a previous conversion in the continuous conversion mode, a conversion phase is initiated. At this point, the logic of conversion of the proposed LDSDC differs significantly from the logic employed in a conventional DSADC. In a conventional DSADC, the first integration is performed with the integrator input tied to the input voltage to be converted. Here, the first integration is performed with the integrator input tied to the negative reference voltage −VR by setting the control lines A1 A0 to be “10”. As a result, voi ramps up with a positive slope given by VR /RC as shown by the solid line in Fig. 2.
1517
This state is maintained for a preset fixed period of time T1 , where T1 = N1 Tc . Here, N1 is a preselected integer and Tc is the period of the TLU clock. Typically, this is accomplished by preloading the register, i.e. NT LU , of the timer counter with N1 , setting the mode to “count down” and ascertaining whether NT LU has reached zero. Sensing that NT LU has reached zero, the TLU logic sets A1 A0 to be “11”, switching the output of the logarithmic amplifier vlog , as input to R. Simultaneously, the register NT LU of the timer counter is loaded with a preset value of (Nf s − Nk ) and its mode set to “count up”. Here, Nf s is the full-scale count of the timer counter and the counter rolls over to zero after reaching Nf s (Nf s + 1 ⇒ “00000”). Nk is a constant, dependent on the thermistor characteristic. Since the logarithmic amplifier has been so designed that its output is always positive, voi starts to ramp down with a slope vlog /RC, and reaches zero after a time period denoted by T2 . The output of the integrator reaching zero is marked by a change of state of the comparator from high to low, which indicates to the TLU the end of the conversion phase and thereby, the measurement cycle. At the end of time period T2 , the TLU outputs N2 , the contents of the timer counter (NT LU ) at that instant. During the period T2 , the counter counts Nk clock periods to reach zero and then counts up to N2 . Hence, T2 = (Nk + N2 )Tc . Making use of the fact that the total charge acquired by the capacitor C over the conversion phase is zero, we get: VR vlog T1 = T2 . RC RC
(6)
Substituting the values of T1 = N1 Tc and T2 = (Nk + N2 )Tc in (6), we obtain: VR N1 Tc = vlog (Nk + N2 )Tc .
(7)
Using the value of vlog from (5) in (7) and rearranging, results in N2 =
V R N1 − Nk . ln Rθ − ln A
(8)
A comparison of (3) and (8) indicates that if we choose VR N1 = β and Nk = γ, then N2 = θ.
(9)
Thus, the output count N2 directly provides the temperature being sensed by the thermistor. It should be noted here that while applying the logarithm to the resistance of the thermistor is achieved with the help of a logarithmic amplifier, the inversion and offset correction required for linearizing the thermistor characteristics is realized simply by exchanging the integration sequences in a DSADC and preloading the timer counter of the DSADC with a preset value. In (9), θ, an analog quantity, is measured using N2 a digital number, thus θ will only be measured as an integer and the fractional part of θ will not appear in the output. This problem can be easily solved by making the full-scale count (Nf s ) corresponding to the fullscale θ to be 10k θ, thus realizing k decimal digits in the output. For example, in the prototype developed, the value of T1 and Tc are chosen such the N2 is 10 000 for θ = 100 ◦ C, resulting
1518
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 60, NO. 5, MAY 2011
in a resolution of 0.01 ◦ C. The possible sources of errors in the proposed LDSDC are discussed next and experimental validation of the scheme is given in the sequel.
was employed and the compensated offset was found to be
