43rd, Midwest Symposium on Circuits and Systems (MWSCAS), East Lansing (MI-USA), Vol. 2, pp. 710-713 August 2000
Low-Voltage CMOS Analog Switch For High Precision Sample-and-Hold Circuit Christian Jesus B. FAYOMI 1, Gordon W. ROBERTS 2 and Mohamad SAWAN 1 1
2
Ecole Polytechnique de Montreal, Department of Electrical and Computer Engineering P.O Box 6079, Station ″Centre Ville″, Montreal, CANADA H3C 3A7 Tel: (514) 340-4711 ext. 5943 Fax: (514) 340-4147
McGill University, Department of Electrical and Computer Engineering, McConnell Engineering Building 3480, University Street, Room 516, Montreal, CANADA H3A 2A7 Tel: (514) 398-6029 Fax: (514) 398-4470 Email: fayomi |
[email protected] |
[email protected]
ABSTRACT This paper presents a sample-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch. The heart of this circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced resulting in improved sample-and-hold accuracy. Simulation results using a 0.18 µm digital CMOS process show that a resolution greater than 16 bits can be obtained with a 1.65V supply voltage. Operation is also possible for supply voltages close to transistor threshold (e.g., 0.5 V).
1.
INTRODUCTION
Most analog-to-digital converters (ADC) typically employ a sample-and-hold circuit at the front-end that must achieve high speed, high linearity and high precision with low-power dissipation. In low-voltage systems, analog sampling becomes particularly difficult because the limited headroom severely degrades the tradeoffs among dynamic range, linearity, speed and power dissipation. Among the most serious factors affecting the performance of a high precision CMOS sample-and-hold circuit are charge injection and clock feedthrough [1]. Several methods have been proposed to overcome these problems. These include charge cancellation by a dummy MOS transistor, offset cancellation by adding a compensation network, using a closed-loop architecture, using a Miller hold capacitance and using switched-op-amp based sample-and-hold circuit [2]. Although charge cancellation methods that make use of a dummy transistor produce good simulation results, great care must be exercised when laying out the clock tree controlling the complementary switches. Others methods have either limited input bandwidth or introduce high design complexity. Although the above techniques are useful and commercially utilized, it should be understood that they represent a tradeoff with respect to speed, power consumption and design flexibility. Alternatively, bootstrapped analog switches have been extensively used for rail-to-rail switching functions in low-voltage SC circuits [3]. They show a constant charge injection through the whole range of operating supply voltage at the expense of an input dependent clock
feedthrough. This technique, however, introduces reliability problems, in particular, for devices with reduced oxide thickness, tox. Figure 1 shows the forecasted gate-oxide thickness as a function of time according to the Semiconductor International Association (SIA) roadmap [4]. It also displays the maximum electrical field across the oxide. The electrical field becomes increasingly high as tox shrinks below 2 nm. It's well known that oxide breakdown is one of the limiting factors for circuit reliability. Therefore, utilization of the bootstrapped low-voltage analog switch for advanced VLSI processes will be limited in the next few years by the need for a low-stress clock voltage doubler circuit. To overcome these limitations we propose a novel low-voltage low stress and reliable clock signal doubler. This clock doubler has been used in the implementation of a dummy compensated bootstrapped switch. We will start by a brief review of the basic principle of the analog low-voltage bootstrapped switch in section 2 follow by the development of our main proposal. Section 3 will focus on the preliminary results and will conclude in section 4.
2. DEEP SUBMICRON LOW-VOLTAGE CMOS ANALOG SWITCH Main characteristic of the MOS transistors is that by itself is an analog switch. They are extensively used in switched capacitor circuit gain stages, capacitors and resistors D/A and so one. Drain and source terminals are the two switch terminals and the gate (and sometimes the bulk) terminals are used to control the conductivity. Ideally, the switch in the on state acts as a fixed linear conductance gds. In practice, the conductance is strongly signal-dependent. Equation (1) gives the conductivity of the transistors in function of the power supply voltage VDD and the input signal.
[
(
W kpn ⋅ L ⋅ VDD − Vin − Vtn − γ n 2φ f + Vin − 2φ f g ds = W kp p ⋅ ⋅ Vin − Vtp − γ p 2φ f + VDD − Vin − 2φ f L
[
(
)] nMOS
)] pMOS
(1)
43rd, Midwest Symposium on Circuits and Systems (MWSCAS), East Lansing (MI-USA), Vol. 2, pp. 710-713, August 2000
As shown in equation (1) and corresponding figure 2, the switch conductivity depends not on the absolute potential of the control terminals, but on their potential relative to the others. Also the conductance through the whole range of input is not constant, and depends on the supply voltage, which becomes extremely low. To ensure rail-to-rail switching operations control, signals exceeding the supply voltage range are required. This is known as bootstrapped switching technique. A general block diagram of the bootstrapped switch is shown in figure 3a. It consists of three main elements: the passtransistor (nMOS, pMOS or both types), a control signal generator and, finally, a clock booster. The control circuit generates a signal linearly related to the input signal. The purpose of the clock booster is to generate a clock signal over and above the supply voltage. In the classical case of a transmission gate, the clock booster and the control circuit are absent. A functional diagram of a clock booster is shown in figure 3b and the new low-voltage low-stress clock booster circuit is depicted figure 3c. Feedback transistor Pb4 keeps the gate-drain voltage of transistor Pb3 to a reasonably low level and is subjected to a maximum source-gate voltage of VDD+|Vtp|, which is acceptable in most processes. The bootstrapped switch compensation scheme is depicted in figure 4a while the control circuit (with pMOS–type pass devices) is shown in figure 4b. Several issues have been considered in the type of transistor for the pass device (i.e., nMOS or pMOS). The most important from a dynamic linearity viewpoint are the ON-resistance RON and the channel charge QCH. All of these parameters scale with switch size; in the N-well process used where kpn ≈ 4×kpp and kpp = µCox, a pMOS device will consume 4 times the area of an nMOS device. However, a pMOS device exhibits a relatively constant conductance and channel charge, independent of the input signal, and can therefore be more easily compensated. Hence, we use a pMOS device as the pass device. The dummy analog bootstrapped switch is shown in figure 4c.
3.
PRELIMINARY RESULTS
The proposed implementation (switches and clock booster) has been simulated with HSPICE using BSIMv3 for two differents technologies. In the 0.5 µm technology the threshold voltages are approximately 0.86 V and –1 V for nMOS and pMOS transistors, respectively, whereas in the 0.18 µm technology they are approximately 0.52 V and –0.48 V, respectively. In the 0.18 µm CMOS process, metal-metal capacitors are used in the implementation of capacitors Cc1,
Cc2 and Cb because of the non-availability of poly-poly capacitors. Figure 5 shows a constant ON-resistance variation with supplies voltages in the 0.18µm processes. For ultra low-voltage (VDD < 0.7 V), the transmission gate formed by P*2 and N2, induced a dead band region which introduces a small variation on the conductance (figure 6). Figure 7 shows the transient analysis simulation results. A low offset voltage is observed which correspond to a resolution greater than 16 bits. The layout has been completed and submitted for fabrication. Experimental results will follow.
4.
CONCLUSION
In this paper a low-voltage, CMOS analog switch suitable for high precision sample-and-hold circuit has been presented. The heart of this circuit is a new low-voltage and low-stress CMOS clock voltage double. An important attribute of the design is that the ON-resistance, is nearly constant. Simulation results using a 0.18 µm digital CMOS process show that a resolution greater than 16 bits can be obtained with a 1.65V supply voltage. Operation is also possible for supply voltages close to transistor threshold (e.g., 0.5V). The layout is in progress and some experimental results will follow soon. The rail-to-rail input range capability enables the circuit to be used in high-speed and high resolution applications such as flash, successive approximation and pipelined ADCs, to name just a few examples.
REFERENCES [1] [2]
[3] [4]
P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Holt, Rinehart and Winston, New York 1987. L. Dai and R. Harjani, ″CMOS Switched-Op-Amp-Based Sample-andHold Circuit″, IEEE J. Solid-State Circuits, Vol. SC-35, No.1, pp. 109113, January 2000. J. Steensgaard, "Bootstrapped Low-Voltage Analog Switches", Proc. ISCAS, Vol.2, pp. II 29- II 32, 1999. Semiconductor Industry Association (SIA), "The International Technology Roadmap for Semiconductors", Table 5, pp. 5, 1998 available online at http://notes.sematech.org/ntrs/Rdmpmem.nsf. Equivalent Maximum Electrical field (MV/cm) 5.0
4.0
tox (nm)
The bulk of the nMOS and pMOS transistors are respectively connected to VSS and VDD unless otherwise stated. Plots in figure 2, is the switch conductance versus input signal Vin.
4-5
5
5
3.0
2.0 >5
>5 >5
1.0
1997 1999
2002 2005
2008 2011
>5
2014
Year
Figure 1: SIA forecast of MOS Gate oxide as a function of time.
43rd, Midwest Symposium on Circuits and Systems (MWSCAS), East Lansing (MI-USA), Vol. 2, pp. 710-713, August 2000
On state conductance gds
Φ bt2 Vout
Transmission gate nMOS
Vss
g
P0
|Vtp|
P1
VDD/2
d
Φ bt1
P4
N2 VDD P* 3
c
Vtn
Vss
Cb
P*2
Vin
VDD
P5a
P5b
pMOS
VDD
VDD
Φ
Vin (V)
(b)
Figure 2: On state conductance of MOSFET switch versus the potential of the switched input signal. Vout Pass Transistor (n or p-type)
Vin
P0d
gd
Vout
P*2
Vin
P1
Φ
Cb
dd
VDD P* 3
Φ bt1
P4
N2
cd
Clock Booster
VDD
P5a
P5b
g Control Signal Input Dependent Generator Φ bt2 Φ bt1
Φ bt2
Vss
VDD Φ
(a) φ
φ bt2
Clock Booster
VDD
2*VDD
(c) Figure 4: (a) Bootstrapped switch compensation scheme; (b) Proposed pMOS-type pass transistor implementation; (c) Dummy bootstrapped switch
(b) 2.75
VDD Pb2
b Pb3 Cc1 Φ
Cc2
Φb
VDD
bΦ b
Φ bt2 Φ bt1 Nb2 a Nb1
Vss
Vin
gd P0
RON_1p25v
RON_1p0v
2.15
RON_0p8v
1.95 1.75 1.55 1.35 1.15
(c) Figure 3: (a) Block diagram of a bootstrapped switch (b) Functional diagram of a clock booster (c) pMOS-type clock booster circuit. g
RON_1p50v
2.35
Pb4
b'
Switch ON Resistance (k Ω )
Pb1
RON_1p65v
2.55
0.95 0.75 0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
Input Signal VIN (V)
Figure 5: ON-Resistance variation with supply voltage (0.18 µm CMOS digital process) P0d
(a)
Vout
1.60
43rd, Midwest Symposium on Circuits and Systems (MWSCAS), East Lansing (MI-USA), Vol. 2, pp. 710-713, August 2000
7.6970
25.250 25.248 25.246 25.244
7.6966
25.242 25.240
7.6964
RO N _ 0p6v
7.6962
RO N _ 0p5v
25.238 25.236
Switch ON Resistance (k Ω )
Switch ON Resistance (k Ω )
7.6968
25.234
7.6960
25.232 7.6958 0.00
0.10
0.20
0.30
0.40
25.230 0.60
0.50
Input Sig nal V IN (V )
Figure 6: ON-Resistance variation for ultra-low supply voltage (VDD < 0.7 V)
1.6
Input/Output Voltage (V)
1.4 1.2 1 0.8 0.6 0.4 0.2 0
50
60
70 Time (us)
80
90
Figure 7: Transient analysis of the compensated bootstrapped switch using coherency principle
100
