Low power, high reliability magnetic flip-flop Y. Lakys, W. Zhao, J.-O. Klein and C. Chappert A new design of a non-volatile magnetic flip-flop is presented. The use of a magnetic tunnel junction (MTJ) to store the information brings non-volatility to logic circuits and promises zero standby power. It is based on the thermally assisted switching (TAS) approach and the pre-charge sense amplifier. By using STMicroelectronics’ CMOS 0.13um design kit and a precise TAS-MTJ compact model, transient functional simulations and Monte Carlo statistical analysis have been carried out to show, respectively, its low power and high reliability performances.
Introduction: Recent exploitation of physical effects in magnetic materials has led to the rapid development of emerging components such as the magnetic tunnel junction (MTJ). The latter stores the information with the spin property of electrons and then brings many interesting properties such as non-volatility, high read/write speed, easy interface with CMOS technology and unlimited endurance, etc. [1]. Thereby it promises great potential to realise instant on/off and ‘zero’ standby-power circuits for both logic and memory applications [2]. The flip-flop (FF) is one of the most important building blocks for logical circuits since it synchronises and stores the intermediate computing data. In this Letter, we present a new architecture for a non-volatile magnetic flip-flop (MFF) based on the thermally assisted switching (TAS) technique [3] and the pre-charge sense amplifier (PCSA) [3] for data sensing. It allows low power consumption and high reliability compared with current MFF proposals [4]. Magnetic flip-flop: Fig. 1a shows the diagram of the proposed MFF. The couple MTJ0 and MTJ1, whose magnetisation of the free layer are always in opposite direction, allows saving binary information [3]. TAS technique has been applied in our design since it allows high switching reliability compared with other approaches [5], it is based on the ‘exchange bias’ storage principle and uses a heating current (IHeat) passing through the TAS-MTJ to assist the magnetic switching (IWrite). The MTJ writing operation occurs as the control signal (EN) is high. Biased under Vdd_a (e.g. 2.4V), transistors N1 and N2 are appropriately sized to generate about 350 mA heating current. The PCSA circuit composed of transistors P1– 4 and N3 – 5 detects the information and amplifies it to logical level [3]. Note that transistor N5 is also appropriately sized to carry both the writing and the sensing current. The control logic bloc generates control signals as well as the bidirectional current required to change the direction of magnetisation. The slave block is a conventional latch as in a classical flip-flop, Fig. 1b.
allow the MTJ writing time to be greatly reduced down to subnanoseconds and thus the programming frequency could be further improved up to GHz. Figs. 2b and c show that the non-volatile information stored in the MFF 3 could be retrieved in tr about 700ps (t2-t1). This reading latency is given by the following equation: tr ¼ tsen + tset + tfal. Here, tsen is the delay (300ps) required by the PCSA sensing operation; tset is the setup time (300ps) between the master and slave registers; tfal is the fall duration of the clock (100ps). This high sensing speed allows the logic circuits to realise instant on/off operation and then consume ‘zero’ standby power.
Fig. 2 Transient simulation of MFF a Input b Clock c Output d Heating enable signal: EN e State of an MTJ f Current flowing through transistor N5(IN5)
The whole operating energy consumed by the MFF is as low as 0.46 mW/bit at 20MHz (CLK) which is, in equivalent conditions, about five times lower than its counterpart presented in [4]. This is because there is no static current flowing through the PCSA transistors outside the heating window (see Fig. 2d ) and the MFF consumes only the dynamic energy while data sensing. Reliability simulation: In this Section, we place emphasis on the reliability performance of the MFF. Following the miniaturisation of fabrication technology, the process and mismatch variation increases significantly, and high reliability becomes a crucial performance for logic circuits. The MFF performs with high reliability thanks to the use of the TAS writing technique and the PCSA circuit, which improves dramatically the sensing reliability compared to other sensing amplifiers [3]. Fig. 3 shows the error rate simulation of the MFF based on MonteCarlo corner statistical analysis. We account for an error when the output value is different from the input of the MFF (Figs. 2a and c). The errors appear as the consequence of both the CMOS and MTJ process and the mismatch variation. With an appropriate size of the emitter area of the transistors (P1 –4, N3– 4), this MFF can tolerate up to 30% degradation of tunnel magnetoresistance ratio (TMR) and resistance area (RA) [6] combined with the standard CMOS process and mismatch variation. X is the minimum area fixed by the CMOS technology node.
Fig. 1 Proposed non-volatile magnetic flip-flop (MFF), and conventional master-slave flip-flop (MSFF) a Proposed non-volatile MFF b Conventional MSFF
Transient functional simulation: Fig. 2 shows the functional simulation of the new MFF using STMicroelectronics’ 0.13um design kit and a precise TAS-MTJ compact model [6]. A propagation time t of 11.2ns can be achieved (t2-t0); this is relatively long owing to the TAS writing operation (10.5ns). Thus, it can operate with a ‘CLK’ frequency up to 90MHz. Note that other writing techniques such as spin torque transfer (STT) are currently being investigated [7]. They
Fig. 3 Error rate of MFF (different PCSA size) output according to variation of TMR and RA
Conclusions: A new design of a MFF is presented in this Letter. The non-volatility and high sensing speed of the MFF allows the logic
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circuits to be powered off completely in ‘idle’ mode and all the data can be retrieved in lower than 1ns. In addition, its sensing operation consumes only dynamic power, thus the overall power of the MFF is at least five times lower than the other proposals. The use of the TAS writing approach and the PCSA sense amplifier bring high reliability to the MFF and allow it error-free output. To validate experimentally this design, a prototype was recently sent to a foundry. Meanwhile, new writing techniques to improve the operating frequency are currently under investigation in our laboratory.
Acknowledgments: The authors acknowledge support from the French national project CILOMAG and NANOINNOV SPIN. We also thank G. Prenat and B. Dieny from the SPINTEC Laboratory for decisive inputs, scientific discussions and crucial help with the simulation model of TAS-MRAM, O. Redon from CEA LETI, and K. Torki and G. Dipendina from CMP for the magnetic design kit. # The Institution of Engineering and Technology 2010 27 July 2010 doi: 10.1049/el.2010.2039 One or more of the Figures in this Letter are available in colour online.
References 1 Chappert, C., Fert, A., and Van Dau, F.: ‘The emergence of spin electronics in data storage’, Nature Mater., 2007, 6, pp. 813– 823 2 Lin, C.J., Kang, S.H., Wang, Y.J., Lee, K., Zhu, X., Chen, W.C., Li, X., Hsu, W.N., Kao, Y.C., Liu, M.T., Chen, W.C., Lin, Y.C., Nowak, M., Yu, N., and Tran, L.: ‘45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell’, IEEE IEDM, 2009, pp. 279–282 3 Zhao, W., Chappert, C., Javerliac, V., and Noziere, J.P.: ‘High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits’, IEEE Trans. Magn., 2009, 45, (10), pp. 3784–3787 4 Sakimura, N., Sugibayashi, T., Nebashi, R., and Kasai, N.: ‘Nonvolatile magnetic flip-flop for standby-power-free SoCs’. Proc. of Custom Integrated Circuits Conf., (IEEE-CICC), San Jose, CA, USA, September 2008, pp. 355– 358 5 Prejbeanu, I.L., Kerekes, M., Sousa, R.C., Sibuet, H., Redon, O., Dieny, B., and Nozie`res, J.P.: ‘Thermally assisted MRAM’, J. Phys., Condens. Matter, 2007, 19, article ID 165218 6 Elbaraji, M., Javerliac, V., Guo, W., Prenat, G., and Dieny, B.: ‘Dynamic compact model of thermally assisted switching magnetic tunnel junctions’, J. Appl. Phys., 2009, 106, (12), pp. 123906–123906-6 7 Devolder, T., Hayakawa, J., Ito, K., Takahashi, H., Ikeda, S., Crozat, P., Zerounian, N., Kim, J.V., Chappert, C., and Ohno, H.: ‘Single-shot timeresolved measurement of nanosecond-scale spin-transfer induced switching: stochastic versus deterministic aspects’, Phys. Rev. Lett., 2008, 100, p. 057206
Y. Lakys, W. Zhao, J.-O. Klein and C. Chappert (IEF, Univ. Paris-Sud, UMR8622, Orsay, F-91405, France) E-mail:
[email protected] The authors are also with CNRS, Orsay, F-91405, France
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