Proc. International Symposium on Circuits and Systems (ISCAS), vol. 5, pp 653 -656, Geneva (Switzerland), May 2000
Low Power/Low Voltage High Speed CMOS Differential Track and Latch Comparator with Rail-to-Rail Input Christian Jesus B. FAYOMI 1, Gordon W. ROBERTS 2 and Mohamad SAWAN 1 1
Ecole Polytechnique de Montreal, Department of Electrical and Computer Engineering P.O Box 6079, Station ″Centre Ville″, Montreal, CANADA H3C 3A7 2
Microelectronics and Computer Systems Laboratory, McGill University Montreal, CANADA H3A 2A7 Tel: (514)398-6029 Fax: (514)398-4470 Email: fayomi |
[email protected] |
[email protected]
ABSTRACT A new CMOS differential latched comparator suitable for low voltage, low-power application is presented. The circuit consists of a constant-gm rail-to-rail common-mode operational transconductance amplifier followed by a regenerative latch in a track and latch configuration to achieve a relatively constant delay. The use of a track and latch minimizes the total number of gain stages required for a given resolution. Potential offset from the constant-gm differential input stage, estimated as the main source of offset, can be minimized by proper choice of transistors sizes. Simulation results show that the circuit requires less than 86 µA with a supply voltage of 1.65 V in a standard CMOS 0.18 µm digital process. The average delay is less than 1 ns and is approximately independent of the common-mode input voltage.
1.
INTRODUCTION
Differential circuit techniques have become common in many areas of analog circuit design. They are especially useful in rejecting common mode noise in integrated circuits that perform both analog and digital signal processing. In such circuits, comparators often provide a link between the analog and digital domains. At the same time, designing analog circuits that can operate from a low-voltage supply is important in today's VLSI systems. The demand for lowvoltage systems stems from three differents sources. First, the rapid advent of battery operated portable systems require low power dissipation in order to prolong battery life, and a minimum number of battery cells to reduce the volume and weight of the system. The second and third reasons are due to the smaller feature sizes offered by today’s VLSI technology. Reduced device dimensions require low voltage power supplies in order to reduce internal electric fields and improve device long-term reliability. This is further driven by the need for reduce power dissipation, as a greater number of transistors are integrated on a single die. According to the SIA roadmap [1], power supply levels in the range of 1-1.65 V will be needed to keep pace with the reduction in transistor dimensions corresponding to line widths below 0.18 µm. Nevertheless, reduced power supply levels do not necessarily lead to lower power dissipation for analog circuits. Current biasing levels must also be reduced. A consequence of the lowered power supply is the need for rail-torail input stages in order to compensate for the reduced input common-mode and dynamic range. Such efforts have been underway for several years now [2]. In CMOS op amp circuits, improved input range operation has been achieved by connecting complementary (NMOS and PMOS) differential amplifiers in
parallel. Such circuits are referred to as having rail-to-rail operation. Similar methods have been also used in comparator designs [3]. Most of them use a switched-capacitor circuit design approach [4], [5] or an inverter-based chopper type amplification approach [6]. In [7] a continuous-time CMOS comparator with a rail-to-rail input stage has been reported. The circuit is based on a single ended design configuration. It consists of two operational transconductance amplifiers (NMOS and PMOS in parallel) in a type II active load enhancement configuration [8]. In this paper we will present a new approach to the design of a CMOS differential latched comparator suitable for low voltage, lowpower applications. The new approach makes use of the well-known constant-gm rail-to-rail input stage used in amplifiers. The circuit consists of a constant-gm rail-to-rail common-mode OTA (compared to previous work [4]-[7]) followed by a regenerative latch. The circuit dissipates less than 86 µA with a supply voltage of 1.65 V in a standard CMOS 0.18µm digital process. At the heart of the design is a track-and-latch circuit. This circuit reduces the number of gain stages normally required in an asynchronous or multi-stage comparator [9] thereby reducing the power and silicon area requirements, as well as decreasing the comparator settling time. The net result is a more power efficient comparator. We begin this paper in section 2 by introducing an overview of the architecture of the proposed comparator, followed by an evaluation of its performance in section 3. Finally, conclusions are drawn in section 4.
2.
Comparator Circuit Rail-to-Rail Input Stage
Biasing Circuit
+ -
BP CP CN BN
+ -
Summing circuit with Regenerative Latch IN1 IN2 IP2 IP1
CP
CN Q Qb
VIP VIN CLK
Figure 1:Comparator Circuit block diagram To optimize the performance of a comparator, one has to consider the resolution, speed and power dissipation trade-off (in a situation of reasonable devices size, i.e. offset considerations). To achieve high resolution, large gain structures are necessary. Attempting to achieve this with one power-efficient gain stage results in reduced
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Proc. International Symposium on Circuits and Systems (ISCAS), vol. 5, pp 653 - 656, Geneva (Switzerland), May 2000
2.1.
Biasing Circuit VDDA MPS1
VSSA
MX1
MX2
MP1
MP2
MX3
MX4
MP3
MP4
BP M2
MPS2
VSSA
CP
M3 M1
I
VSSA
VSSA
CN MY3
MY4
MN3
MN4
MY1
MY2
MN1
MN2
BN
1:k Rin = R
VSSA Start-Up
Cascode Bias Current Reference
Figure 2: Biasing Circuit The biasing circuit is shown in Fig. 2. It is a high swing cascode version of the β-multiplier reference of [10]. This circuit utilizes positive feedback and is stable as long as the loop gain is less than unity, which is the case when k > 1 (with k defined as the aspect ratio of transistor MN2 over the aspect ratio of transistor MN1). The biasing current I, is defined by the resistance value R and the aspect ratio, k, using the first-order approximation relation described in [9]. Unfortunately this circuit has a second stable operating point where all the currents are zero. To guarantee that doesn’t happen, we have added a start-up circuit that only affects the operation if all the currents are zero at start-up. The biasing current I is affected by the value of the resistance R. A variation of about ± 20% in the resistance value leads to an approximately ±25% in the biasing current. This induced variation in the biasing current has a direct influence of the comparator resolution by means of the differential input stage gain. A typical loss of 3 bits of resolution has been observed.
2.2.
Constant-gm rail-to-rail input stage
VDDA M5
MBP
M6
PMOS Current Differentiator M9
M10
M7
M8
BP
MC6
MC5
MCBP
MC10
MC9
MC8
MC7
CP IN1 MPC1
IN2
MPC2
MNC1 MN1
MP1
MP2
MNC2
MN2
IP2
VIP VIN
IP1
CN BN
MCN1
M1
MCN2 M2
MCN3 M3
MCN4
MCBN
MC12
M4
MBN
M12
NMOS Current Differentiator
MC11
M11
VSSA
Figure 3: Constant-gm rail-to-rail comparator input stage Figure 3 shows the constant-gm rail-to-rail input stage in a highswing cascode configuration. When a single differential pair is used as an input stage for a comparator, a small input common-mode range is obtained. A well-known technique to realize a rail-to-rail input stage is to place two complementary pairs in parallel. When the common mode input signal is close to the rails, only one of the pairs turns on while the other one is cut off. At the mid range, both the n- and p- type pairs operate. Because of this the total transconductance is not constant across the input common mode range and the delay of the comparator may vary as seen in [7]. The transconductance has twice the gm value of a single pair, assuming both pairs have the same gm. This is an undesirable situation because it gives delay and performance evaluation problems. An easy way to measure and control the transconductance is to tune the biasing currents of the n- and p-type pairs. The complementary input stage with three to one current mirror proposed in [11] has been used. The relation describing the way the current is distributed in the differential constant-gm input pair is well described in [11] and will not be reported here. Offset on this constant-gm differential operational transconductance amplifier will lead to an offset in the comparator circuit. This offset is mainly due to mismatch and threshold variation in the input drivers (n and p-type). At the midrange, when both n-and p-type pairs operate, total offset is the average value of the induced offset from each pair. When the common mode input signal is close to the rails, offset contribution would be the maximum contribution coming from both input pairs. Equations describing those offsets are given below in section 3.
2.3.
Regenerative latch
The regenerative output latch is based on an approach proposed in [12] and is shown in Fig. 4, together with the current summing circuit. The latch consists of discharge transistors (M6-M7), an nchannel flip-flop (M1Y-M2Y) with a pair of n-channel transmission gates for strobing (MS1-MS2), p-channel flip-flop (M2X-M3X), and p-channel pre-charge transistors (M1X-M4X). The flip-flop output is taken at the drain terminals of MS1-MS2 instead of the corresponding source nodes. This is done to increase the regeneration speed and reduce the offset [13]. In addition, the strobing transistors isolate the flip-flop from the comparator output nodes, reducing the load on the flip-flop to the gate capacitance of the flip-flop itself. Offsets caused by the channel length fluctuation (during manufacturing), estimated as the main source of offset voltage, is much lower at zero volt substrate bias [14]. Such an
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To summing circuit
bandwidth due to amplifier gain-bandwidth trade-off. Conversely, medium-speed operation can be obtained by cascading several lower-gain stages at the expense of higher power dissipation. Although individual stages can be made fast, signals require time to propagate through all stages. Possibly the most power-efficient high-speed design method involves combining a low-gain (highbandwidth) stage with a positive feedback track-and-latch circuit. In essence, this achieves a large nonlinear gain with a high-speed and low power design. Such an approach is illustrated in Figure 1. It consists of three main stages: a biasing circuit, a constant-gm rail-torail low-gain amplifier stage and a summing-regenerative latch circuit. The input differential voltage is converted into a differential current using the constant-gm stage. This differential current is then summed and fed to the latch circuit for a decision. Details of each stage are described below. The bulk of all pMOS (nMOS) devices in those circuits are connected to the positive (ground) supply voltage VDDA (VSSA) unless otherwise stated.
Proc. International Symposium on Circuits and Systems (ISCAS), vol. 5, pp 653 - 656, Geneva (Switzerland), May 2000 effect is estimated to be the main source of offset voltage in the latch. Thus, transistors channel length can be reduced and the flipflop speed can be made faster. Summing Current Regenerative Latch
VDDA M0
MC0
M1
MC1
MC3
MC4
CP
M3X M4X
M1X M2X
Clk
IN1 IN2 IP2
Q Qb MS2
MC2
MC5
M2
M5
VSSA
VDDA
MS1
IP1
CN
VDD
M4
M3
MC6
NQ
NQB
Numerous works has been performed on offset contribution due to mismatch problems. An useful offset estimation has been reported by Steyaert [16] and is given by:
M2Y M7
M6 M1Y
VSSA
VDDA
MC7
VSS
length, biasing current of the p-type input pair and threshold variation in the p-type devices (respectively the channel length, biasing current of the n-type input pair and threshold variation of the n-type devices). The first term comes from dimension fluctuation in the differential input pair and the load transistors. Using layout techniques, such as common centroid configurations, the transistor mismatch caused by gradients can be greatly reduced. The second and third come from charge fluctuation. Since surface state density and impurity concentration can be well controlled and since the last two terms are proportional to gate oxide thickness (which is small in our case here) these terms are insignificant compared to the first. The first term is increased in inverse proportion to channel length, therefore this term was assumed dominant for the comparator offset consideration.
VSSA
σ 2 (Voff ) = Figure 4: Summing circuit with regenerative latch
3.
CIRCUIT PERFORMANCE
Our goal is to design a comparator that has high accuracy, low power consumption and high speed with a reasonable transistor size (offsets consideration). Before sizing the circuit, we investigate the main source of offset and what limits the circuit performance. There are two mains source of offset in the circuit and they can be expressed as
V =V +V offset offset , diffpair offset , latch
(1.1)
where Voffset,diffpair and Voffset,latch are the offset contribution form the constant-gm differential input pair and the regenerative latch, respectively. The offset voltage in the latch circuit is systematically minimized by the latch topology [14]. Also, since the offset voltage in the latch circuit is divided by the differential amplifier gain, which is about 84 V/V in our case, most of the offset sources are in the differential stage. There are two kinds of offset sources in a MOS differential pair. They are charge density fluctuation, such as surface states and impurity doping concentration, and dimension fluctuation. Offset associated with the constant gm-input pair consists of contribution from the p- and n-type differential input pairs. Offset contribution of the p-type input pair with n-type load transistor is given by: I k 1 1 bp n ⋅∆VT (1.2) = D ⋅ + V ⋅ + ∆VT + offset , p − p L p n L 2k k p p p n
while the one from the n-type input pair with p-type load is k 1 1 I bn p = D ⋅ + V ⋅ + ∆VT + ⋅∆VT (1.3) offset , n − n L n p L 2k k p n n n
where Dp and Dn denotes the channel-length imbalance between transistors pairs, for both p-channel and n-channel devices; Lp, Ibp, ∆VTp (respectively Ln, Ibn, ∆VTn) are respectively the channel
kp gm ⋅ L
2
Aβ2
4
(VGS − Vt )⋅ AVT2 +
(VGS − Vt )2
(1.4)
where the constants AvT and Aβ are technology dependent. Table 1 in [16] summarized the value of those constants for several industrial CMOS technologies. We observe a decrease in those constants with the decrease of the minimum devices sizes. This is mainly due to the decrease in oxide thickness as has been measured in [17]. The variance reduces with increasing gate area (W/L) and with decreasing oxide thickness. Offset voltage dependence on channel fluctuation has been reported in [12], [13]. Based on those results we choose two times the minimum length for p-channel and n-channel input driver transistors and four times the minimum length for the p-channel and n-channel load transistor. In order to achieve high comparison speed the minimum channel has been used in the latch circuit.
3.1.
Simulation Results
The proposed implementation has been simulated with HSPICE using BSIMv3 0.18µm technology. In this technology, the threshold voltage levels are approximately 0.52 V and –0.48 V for nMOS and pMOS transistors, respectively. Figure 5 shows the sum of the square roots of the tails currents of the complementary differential amplifiers used in the amplifier stage as a function of the input common mode voltage. Although the appropriate transistor scale factor is not included, it serves as a useful measure of how the amplifier gm varies with the input common-mode voltage. In particular, here we see that the sum of the square root of currents varies between 4 and 4.7 mA1/2. A peak occurs at each end of the input common-mode voltage range, corresponding to the condition when one differential pair is partially on, while the other pair is fully on. For the device sizes chosen in our design, this corresponds to a 14% change in gm over the full range of common-mode input voltage, as predicted by the formula provided in [11]. The simulated comparator performance using VDD = 1.65 V, a switching voltage overdrive of ± 0.2014 mV (which corresponds to a ± 0.5 LSB of a 12 bit precision) and an inverter a load (which is the case in our application) is summarized in Table 1. The propagation delay shows little variation, and the delay in all cases remains smaller than 1ns. The propagation delay when the common mode input value is near one of the power supply voltage is only slightly increased above this value.
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Proc. International Symposium on Circuits and Systems (ISCAS), vol. 5, pp 653 - 656, Geneva (Switzerland), May 2000
The propagation delay in Table 1, which has been simulated under static condition (VIP and VIN are set to a DC input level with an overdrive of ± 0.2014 mV), is less than 1ns. An additional simulation has been performed under dynamic conditions using the worst-case driving condition waveform of a comparator described in and displayed in Figure 6. Results show an average propagation delay of about 15 ns. This is due to the speed limitation of both the NMOS and PMOS current differentiator (highlighted in figure 3). This can be improved at the price of increasing the current level.
5.0 4.5
4.
CONCLUSION
In this paper a new rail-to-rail track-and-latch comparator has been presented. An important attribute of the design is that the transconductance of the preamplifier, and therefore the propagation delay, is nearly constant. The circuit operates at 1.65V and draws about 86µA of current, resulting in a power dissipation of 141µW. The propagation delay, in all cases, remains smaller than 1ns. Under dynamic conditions using the worst case waveform, results show an average propagation delay of about 15ns due mainly the differentiator circuit. The layout is in progress and some experimental results will follow soon. The rail-to-rail input range capability enables the circuit to be used in high-speed resolution applications such as flash, successive approximation and pipelined ADCs, to name just a few examples.
IBN 0.5 + I BP0.5 (m A
0.5
)
4.0 3.5
REFERENCES
3.0
[1]
2.5 2.0
[2]
1.5 [3]
1.0 0.5 0.0 0.00
[4]
0.25
0.50
0.75
1.00
1.25
1.50
VCM (V)
[5]
Figure 5: Simulated variation of the sum of the square roots of the tail currents proportional to gm.
[6]
Vcm/VDD 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 AVERAGE
Comparator Output Q tr (ps) tf (ps) tPHL (ps) 46.766 35.398 679.360 46.329 35.399 619.320 42.858 35.413 408.820 41.976 35.420 430.570 41.822 35.421 437.320 41.888 35.421 436.710 41.831 35.421 435.310 42.103 35.418 414.830 44.530 35.405 448.940 46.705 35.499 623.440 46.807 35.399 695.400 43.965 35.419 511.820
[8]
tPLH (ps) 88.499 88.486 88.381 88.319 88.312 88.312 88.313 88.332 88.445 88.491 88.492 88.398
[9] [10]
[11]
[12] [13]
Table 1: Summary of simulation results VDD
VCM
[7]
[14] [15]
CLK LSB/2
VIN VIP
[16] [17]
VSS Time (ns)
Figure 6: Waveform used for the dynamic testing on the comparator
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Semiconductor Industry Association (SIA), ″The International Technology Roadmap for Semiconductors″, Table 5, pp. 5, 1998 available online at http://notes.sematech.org/ntrs/Rdmpmem.nsf. R. Hogervorst et al., ″CMOS Low-Voltage Operational Amplifiers with Constant-gm Rail-to-Rail Input Stage″, Analog Integrated Circuits and Signal Processing, Vol. 5, No.2, pp. 135-146, March 1994. R. Rivoir and F. Maloberti, ″A 1mV Resolution, 10 Ms/s Rail-to-Rail Comparator in 0.5µm Low-Voltage CMOS Digital Process″, Proc. of IEEE Int. Symp. Circuits and Systems, pp. 461-464, June 1997. N. Shiwaku and al., ″A Rail-to-Rail Video-Band Full Nyquist 8-Bit A/D Converter″, Proc. of Custom Integrated Circuits Conference, pp.26.2.1-26-2.4, 1991. R. K. Hester et al., ″Fully differential ADC with Rail-to-Rail Common-mode Range and Nonlinear Capacitor Compensation″, IEEE J. Solid State Circuits, Vol. SC-25, No. 1, pp.173-183, February 1990. T. Kumato et al., ″An 8-bit High Speed CMOS A/D Converter″, IEEE J. Solid State Circuits, Vol. SC-21, No. 6, pp.976-982, December 1986. W.-S. Chu and K. Wayne Current, ″A CMOS Voltage Comparator with Rail-toRail Input Stage″, Analog Integrated Circuits and Signal Processing, Vol. 19, No.2, pp. 145-149, May 1999. R. Wang and R. Harjani, ″Partial Positive Feedback for Gain Enhancement of Low-Power CMOS OTAs″, Analog Integrated Circuits and Signal Processing, Vol. 8, No.1, pp. 21-35, July 1995. D. A. Johns and K. W. Martin, ″Analog Integrated Circuit Design″, John Wiley & Sons, New York, 1997, (Chapter 5). E. Vittoz and J. Fellrah, ″CMOS Analog Integrated Circuits Based on Weak Inversion Operation″, IEEE J. Solid State Circuits, Vol. SC-12, No.3, pp. 224231, June 1977. A. L. Coban, P. E. Allen and X. Shi, ″Low-Voltage Analog IC Design in CMOS Technology″, IEEE Trans. Circuits and Systems I, Vol. 42, No. 11, pp. 955-958, Nov. 1995 A. Yukawa, ″A CMOS 8-Bit High-Speed A/D Converter IC″, IEEE J. Solid State Circuits, Vol. SC-20, No.3, pp.775-779, June 1985 M.J. Deen, J. Wang Z.X. and Z.P. Zuo,”Substrate Bias Effects on Short Channel Length and Narrow Channel Width PMOS devices at Cryogenic Temepratures”, Proc. of Workshop on Low Temperature Semiconductor Electronics, pp.53-56, 1989. A. Roychaudhuri et al., “Substrate Bias Dependance of Short-Channel MOSFET Threshold Voltage- A Novel Approach”, IEEE Trans. Electron Devices, Vol. 35, No.2, Feb. 1988. C. C. Enz and E. Vittoz, “CMOS Low-Power Analog Circuit Design”, Designing Low Power Digital Systems, Emerging Technologies, pp.79-133, 1996. M. Steyaert et al., “Custom Analog Low Power Design: The problem of low voltage and mismatch”, Proc. Custom Integrated Circuits Conferences, pp. 285292, 1997. M.J. Pelgrom and M. Vertregt, “CMOS Technology for Mixed Signals ICs”, Solid-State Electronics, Vol.41, No.7, pp. 967-974, July 1997.
